Investigation of temperature dependent threshold voltage variation of Gd2O3/AlGaN/ GaN metal-oxide-semiconductor heterostructure

Temperature dependent threshold voltage (V th ) variation of GaN/AlGaN/Gd 2 O 3 /Ni-Au structure is investigated by capacitance-voltage measurement with temperature varying from 25 ◦ C to 150 ◦ C. The V th of the Schottky device without oxide layer is slightly changed with respect to temperature. However, variation of V th is observed for both as-deposited and annealed device owing to electron capture by the interface traps or bulk traps. The V th shifts of 0.4V and 3.2V are obtained for as-deposited and annealed device respectively. For annealed device, electron capture process is not only restricted in the interface region but also extended into the crystalline Gd 2 O 3 layer through Frenkel-Poole emission and hooping conduction, re-sulting in a larger V th shift. The calculated trap density for as-deposited and annealed device is 3.28 × 10 11 ∼ 1.12 × 10 11 eV − 1 cm − 2 and 1.74 × 10 12 ∼ 7.33 × 10 11 eV − 1 cm − 2 respectively in measured temperature range. These results indicate that elevated temperature measurement is necessary to characterize GaN/AlGaN heterostructure based devices with oxide as gate dielectric. Copyright 2012 Author(s). This ar-ticle is distributed under a Creative Commons Attribution 3.0 Unported License . metal-semiconductor heterostructure ﬁeld


I. INTRODUCTION
GaN based material system has been intensively studied over the last few decades. [1][2][3][4] GaN based semiconductor has distinct advantages, such as high electron mobility, high breakdown voltage, high frequency operation and high thermal and chemical stabilities. 5 Owing to large spontaneous and piezoelectric polarization in GaN/AlGaN heterostructure, metal-semiconductor heterostructure field effect transistor (MESHFET) or high electron mobility transistor (HEMT) is widely studied for high power and high frequency applications. 6 Conventional Schottky gate limits the device performance due to large gate leakage current. Consequently several approaches have been proposed to reduce gate leakage current and a variety of gate oxide in metal-oxide-semiconductor gate (MOS) structures have been reported. 7,8 Considering electron counting rule, it is relatively easy to define an ideal (100)Si-HfO 2 interface, because Si is non-polar and has a valence number of 4, like Hf. However, the (100) GaAs-HfO 2 interface is harder to define, because (1) GaAs is a polar molecule, and (2) Ga has 3 valence electrons while As has 5 valence electrons. Therefore it is useful to interpose a trivalent oxide matching layer on III-Vs' to allow charge matching across the interface. 9 This may be the reason why trivalent oxide like Gd 2  A standard high frequency C-V measurement is usually performed at room temperature (RT) to analyze the interface and oxide quality of MOS-HFET devices. Owing to complex device structure (two interfaces) and wide band gap nature of GaN/AlGaN, the above mentioned RT characterization may not be adequate to fully understand the interface behavior between AlGaN and insulator. Most of the deep interface states are frozen at RT which can only manifest at higher temperature. 12 Thus, the C-V measurement in elevated temperature is useful to characterize the quality of oxide-AlGaN interface.
In this study, we demonstrate the temperature dependence of the threshold voltage (V th ) of GaN/AlGaN/Gd 2 O 3 /Ni-Au structure by means of capacitance-voltage measurement. Owing to the interface states between AlGaN and oxide, the V th variation is obvious at elevated temperatures. Therefore, thermal stability of oxide/AlGaN interface should be one of the criteria to determine the quality of MOS-HFET devices.

II. EXPERIMENT
The Al 0.27 Ga 0.73 N (25nm)/GaN (4μm) heterostructure was first grown on sapphire substrate by atmospheric pressure metal organic chemical vapor deposition (AP-MOCVD) system. The native oxide of exposed AlGaN surface was removed using dilute hydrochloric acid (HCl:H 2 O = 1:10) for 90 sec. Then 20nm Gd 2 O 3 film was deposited on AlGaN/GaN sample by e-beam evaporation from 99.99% pure Gd 2 O 3 granules under 2×10 −6 Torr chamber pressure with a very low deposition rate of 0.2Å/s. After the oxide film deposition, a rapid thermal annealing (RTA) was performed at 850 • C for 30s in air ambient. Then Ti/Al/Ti/Au metal stack was deposited by e-beam evaporation system followed by RTA at 700 • C for 30s in N 2 ambient for ohmic contact formation. 13 During RTA process of Gd 2 O 3 film, Ti/Al/Ti/Au metal stack cannot be annealed owing to air annealing ambient which may cause oxidation of the metal stack. A lower annealing temperature of 700 • C was chosen for ohmic contact formation. Higher annealing temperature (≥750 • C, N 2 , 30s) degrades the interface (AlGaN/Gd 2 O 3 ) which will cause "smearing out" the C-V curve. In this condition, the C-V curve exhibits no sharp transition from depletion to accumulation region. Finally Ni/Au top electrode (100μm diameter circular dot) was evaporated as gate contact. The crystal quality of GaN/AlGaN heterostructure was investigated by employing high resolution X-ray diffractometer (HR-XRD). To characterize the microstructure of GaN/AlGaN/Gd 2 O 3 sample, high resolution transmission electron microscopy (HR-TEM) was performed using Philips Tecnai F20 FEG-TEM. The capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of fabricated MOS structure were characterized by Agilent E4980A precision LCR meter.  Figure 2(a) shows the (0 0 0 2) diffraction profile of GaN/AlGaN heterostructure. The main two peaks are assigned to be GaN (0 0 0 2) and AlGaN (0 0 0 2). Satellite peaks are also clearly observed in the XRD spectra. Figure 2(b) shows the cross-sectional HR-TEM image of GaN/AlGaN/Gd 2 O 3 structure after annealing at 850 • C for 30s. The HR-TEM image confirms that Gd 2 O 3 has a good interface to AlGaN. The polycrystalline phase formation of Gd 2 O 3 layer after high temperature annealing is also evident from the TEM image.

III. RESULTS AND DISCUSSION
Three different kinds of devices were fabricated with similar process flow i.e. control (Schottky device without Gd 2 O 3 layer), as-deposited (Gd 2 O 3 layer without RTA) and annealed (Gd 2 O 3 layer with RTA treatment). To investigate the effect of measurement temperature on V th of the fabricated devices, capacitance-voltage measurement was performed between room temperature (RT) and 150 • C. The frequency and ac modulation voltage were kept at 1MHz and 25mV respectively. Figure 3 shows the C-V characteristics of control, as-deposited and annealed devices measured in bias range from −10V to 0V. The RT V th of control device is found to be −4.1V whereas V th of as-deposited and annealed device are found to be −4.8V and −8.2V respectively. The less negative V th for as-deposited device is attributed to negative fixed oxide charge in the Gd 2 O 3 layer whereas more negative V th for annealed device is attributed to change of homogeneity of oxide layer and removal of negative charge by annealing. 14 It is well known from the Si based MIS (i.e. Si/SiO 2 ) capacitor C-V analysis that the positive V th shift is attributed to electron trapping in the structure. A positive V th shift is observed for three kinds of devices in elevated temperature. Temperature induced Fermi level movement through built-in potential leads to an opposite shift of the V th . Temperature dependent conduction band discontinuity and sheet carrier density in triangular quantum well (2-DEG) is negligible. The only possibility behind the positive V th shift in the fabricated structure in elevated temperature is electron capture by the interface states or Gd 2 O 3 bulk traps. Figure 4 shows the C-V characteristics of three kinds of devices with varying temperature from RT to 150 • C. For the control device [shown in Fig. 4(a)] the V th at RT of −4.1V is slightly shifted to −3.9V at 100 • C and remains almost constant up to 150 • C. The small positive V th shift is originated from the electron capture in the interfacial layer between AlGaN layer and gate metal. It was reported that a sub nanometer thick interfacial layer (AlOx and NiOx) present between the Ni/Au gate metal stack and AlGaN epilayer. 15 As the V th shift is minimum in the whole temperature range, the control devices shows good thermal stability at elevated temperature. In case of as-deposited device, RT C-V shows a small hysteresis window of 0.2V [shown in inset of Fig. 4(b)]. The hysteresis window is diminished in elevated temperature and V th is shifted from −4.8V at RT to −4.4V at 150 • C [ Fig. 4(b)]. On the other hand, annealed device shows different trapping phenomena during thermal stress [ Fig. 4(c)]. The parallel shift towards positive voltage direction of C-V curve is very prominent with increasing temperature. The resultant V th shift of around 3.2V is observed in the temperature up to 150 • C. For Si based MIS (i.e. Si/SiO 2 ) capacitor, it is well known that any "smearing out" in the experimental high frequency C-V curve indicates the presence of interface states and any parallel shift indicates the presence of fixed oxide charge. 16 However, our measured C-V shows fixed oxide charge like behavior with increasing temperature. The C-V curve of the GaN/AlGaN heterostructure is mostly governed by 2-DEG at GaN/AlGaN interface. As the AlGaN/Gd 2 O 3 interface is located far from the 2-DEG channel, any charge trapping by this interface states or bulk traps give rise to parallel shift of C-V curve. Therefore, large V th shift in elevated temperature is attributed to the electron capture by interface states as well as crystalline Gd 2 O 3 bulk traps which is explained below. The two main ohmic conduction mechanisms in an insulator are Frenkel-Poole emission and hooping conduction which are expressed, respectively, by 17 where C is a material dependent constant, q is the electronic charge, φ B is the barrier height, E f is the electric field, k is the Boltzmann constant, T is the temperature and E ae is the activation energy of electron hopping. The two ohmic conductions are dependent on both electric field and temperature. So the electron capture process is not only restricted in the interface region, but is also extend into the Gd 2 O 3 layer through above the mentioned mechanism during thermal stress.  Fig. 5(c)]. The origin of V th shift under positive pulse in gate is owing to tunneling induced electron transport from two dimensional electron (2-DEG) gas to bulk traps. 18 The tunneling induced electron transfer effect in GaN/AlGaN/Gd 2 O 3 (crystalline)/Ni-Au structure opens up a way to design GaN/AlGaN based memory device and have already been studied previously. 19 During positive gate voltage stress at RT and 100 • C, the tunneling electron from 2-DEG are captured by bulk traps ( V th = 0.8V). However, in the case of thermal stress at 150 • C, most of the bulk traps are previously occupied through ohmic conduction mechanism in insulator whereas very few ( V th = 0.2V) are available for tunneled 2-DEG electrons.
Some estimation of fast interface trap density has been made for both as-deposited and annealed device by single frequency approximation method proposed by W.A. Hill and C.C. Coleman. 20 The interface trap density D it is calculated from conductance-voltage (G-V) and capacitance-voltage (C-V) curves with the following expression where q is the electronic charge, A is the area of the capacitor, G m,max is the peak value of conductance, ω = 2π f; f is the measurement frequency, C ox is the capacitance in accumulation region and C m is the capacitance corresponding to G m,max. The RT C-V and G-V curves at 0.1MHz of annealed device are shown in Fig. 6(a) indicating the specifics of the input data employed for the calculation.
In a similar way, the D it is extracted for as-deposited and annealed device and plotted as function of temperature over the whole temperature range [ Fig. 6(b)]. The density of the fast trap decreased from 3.28×10 11 to 1.12×10 11 eV −1 cm −2 for as-deposited device, and 1. 7.33×10 11 eV −1 cm −2 for the annealed device with an increase in temperature as the energy levels moves deeper into the band gap. The trap density is also calculated from the concept of trapped electron density (N electron ) from the following expression where V th is the resultant threshold voltage change, C ox is the capacitance in accumulation region, q is the electronic charge and A is the area of the capacitor. The trap density are found to be 3.58×10 11 cm −2 and 3.45×10 12 cm −2 for as-deposited and annealed device respectively which are higher, when compared to the calculated D it value owing to contribution of bulk traps. The trap density for the annealed device is around one order of magnitude higher than that of the asdeposited device. This is owing to crystallization annealing of Gd 2 O 3 film. Higher trap density for Al 2 O 3 /AlGaN/GaN MOSHEFT was reported than that of HFETs owing to the gate oxide grown at higher (600 • C) temperature. 21 Therefore it is crucial to understand the properties of trap states for control and optimization of interface between insulator and GaN/AlGaN system.

IV. CONCLUSIONS
In conclusion, temperature dependent V th variation of GaN/AlGaN/Gd 2 O 3 /Ni-Au structure has been investigated through capacitance-voltage measurement. The electron capture by the interface states or bulk traps is responsible for the V th variation in three kinds of devices. In terms of V th variation in elevated temperature, as-deposited device shows a more thermal stability characteristic ( V th = 0.4V) as compared to annealed device ( V th = 3.2V). Single frequency approximation method reveals that D it is around one order of magnitude higher in annealed device (1.74×10 12 ∼7.33 ×10 11 eV −1 cm −2 ) than that of as-deposited device (3.28×10 11 ∼1.12×10 11 eV −1 cm −2 ). Our study demonstrates the importance of elevated temperature C-V measurement to characterize GaN/AlGaN heterostructure based devices with oxide as gate dielectric. It is suggested that the as-deposited oxide will be better for MIS-HEFT devices. On the other hand, high temperature annealed oxide will be useful to realize memory device in GaN/AlGaN system.