Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.


I. INTRODUCTION
As the feature sizes of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) scale down into the nanoscale regime, the devices face the challenge of short channel effects (SCEs), which increase power dissipation and degrade device performance. 1 Numerous structures have been introduced to minimize SCEs, such as fully depleted silicon-on-insulators (SOIs), 2 FinFETs, 3 and nanowire devices. 4 Nevertheless, the drift-diffusion mechanism of MOSFETs is a major obstacle that fundamentally limits supply voltage scaling and reduction of power consumption. Recently, tunnel field-effect transistors (TFETs) have received a lot of attention because they can provide a subthreshold swing (SS) lower than 60mV/dec at room temperature, and they can achieve a higher ratio between on-and off-state currents compared to MOSFET devices. 5,6 The structure of TFETs is a reverse-biased PN junction controlled by the gate, while the working principle is based on the band-to-band tunneling (BTBT) mechanism. Due to their inherent asymmetrical configuration, TFETs can work in on-, off-, and ambipolar-states depending on the polarity of the gate voltage. 7 Many studies have compared the working principle, modeling, and electrical characteristics of TFETs to those of MOSFETs using both numerical simulations and experimental tests. [8][9][10] However, some issues remain unresolved in TFET research. Previous investigations have focused on the development of special structures to boost the on-state current (I on ) of TFETs, such as source-channel hetero-junctions, 11,12 ultra-thin body SOIs, 13 and heavily doped tunnel junctions. 14 However, these special structures require the use of certain key techniques, and these techniques are difficult to achieve using a standard CMOS fabrication process flow. Another concern about TFET devices is based on the implementation of narrow gap materials, e.g., germanium, 7,15 InGaAs, 16 and graphene. 17 The off-state current (I off ) of devices using these materials inevitably increases due to the ambipolar effect, which leads to an enlarged average SS and neutralizes the advantages of these devices. Therefore, we tried to find an effective solution that can increase I on and reduce I off and SS simultaneously to be compatible with the CMOS process.
In particular, the lateral energy band profile and the electric field contour can be tuned by the energy band profile modulation (BPM) effect, which manipulates the carrier tunneling probability and space distribution, thus improving device performance. In our previous work, a hetero-materialgate (HMG) structure was proposed to realize the BPM effect in the source-channel junction. 18 It was shown that the HMG TFET had a higher I on and a lower SS compared to the single-material-gate (SMG) TFET due to the BPM effect. Unfortunately, the ambipolar effect cannot be inhibited using the HMG configuration. Moreover, the ambipolar effect becomes even more pronounced when narrow gap materials are employed. To address this issue, a Si-based TFET design with a symmetrical trimaterial-gate (TMG) structure was developed; the gate structure engineers the energy band profile at both the source and drain sides. The properties of the device were analyzed through numerical simulation. It was determined that the device performance of the TMG TFET was enhanced by the BPM effect.

II. DEVICE STRUCTURE AND SIMULATION
The simulations were performed with the 2D Sentaurus Device simulator 19 using a dynamic nonlocal BTBT model. In contrast to local tunneling models, a nonlocal BTBT model describes a physical picture of the real space carrier transport through the barrier, and it dynamically takes account of the energy band profile along the entire tunneling path. Moreover, the electrons and holes are generated nonlocally at the end of the tunneling path, and the generation rate is obtained from nonlocal path integration. The dynamic nonlocal BTBT model provides a very complex BTBT probability expression, which is decided by both the potential profile and the electric field. Furthermore, the BTBT rate can be reduced to Kane and Keldysh models 20 in the uniform electric field limit: where ξ is the magnitude of the electric field, ξ 0 is 1V/cm, and P = 2.5 for the indirect tunneling process. Parameters A and B are fitting coefficients, and they were calibrated with experimental Zener diode characteristics, as reported by Fair and Wivell. 21 Kane's two-band dispersion relation was utilized due to silicon being an indirect bandgap material. A bandgap narrowing model and Fermi statistics were employed to take into account the effect of high doping concentration in the source and drain regions. The standard drift-diffusion carrier transport model and the Shockley-Read-Hall recombination model were also used. A fine mesh near the tunneling interface was built and carefully assembled.
To ensure fair comparisons, all the SMG, HMG, and TMG device structures described in this study are identical in terms of physical geometry and doping profile; the only difference among these devices is how the gate is engineered. The gate of the SMG TFET uses a single material, as shown in Fig. 1(a). The gate of the HMG TFET consists of two parts, and they have different work functions, as shown in Fig. 1(b). Fig. 1(c) shows our proposed device, which has a symmetrical TMG structure with the gate stack (L gate = L S-gate + L C-gate + L D-gate ) being divided into three parts: the S-gate is close to the source region, the C-gate is above the center of the channel, and the D-gate is at the drain side. In the simulations, the materials of the S-gate, C-gate, and D-gate were designed to be Al, Cu, and Al, respectively, and their work functions were 4.1, 4.7, and 4.1eV, respectively. It is worth mentioning that the work function difference can be precisely tuned by changing a variety of process parameters, such as the type of doping impurity, doping concentration, 22 and germanium mole fraction. 23 The thickness of the silicon film on the buried oxide was 30nm. 3nm-thick HfO 2 was used as a gate insulator, and its dielectric constant was 22. The following device doping levels were used: 10 20 /cm 3 p-type for the source, 10 19 /cm 3 n-type for the drain, and 10 17 /cm 3 for the lightly doped n-type channel. This type of asymmetrical doping profile is useful for suppressing the ambipolar effect. 7 A conceptual process flow was used to achieve the HMG structure based on conventional MOSFET technology, as illustrated in Fig. 2(a). One additional mask is needed for the fabrication of the S-gate, which requires a photolithography resolution that is equal to, or even higher than, that of the gate length. The S-gate can be formed using either an asymmetrical etch or lift-off techniques. 24 Nevertheless, for TMG devices, the S-gate and the D-gate can be fabricated in one step by a self-aligned symmetrical spacer process, so the material and shape of the S-gate and the D-gate are almost identical, as shown in Fig. 2 In our comparisons of the characteristics of TFET devices with different gate work functions, SS is defined as the average slope when the drain current increases from 0.1fA/mm to 1nA/mm. V turn-on and V turn-ambipolar correspond to the gate voltages in on-and ambipolar-states, respectively, when the drain current is equal to 0.1fA/mm. The ambipolar window, which is used to describe ambipolar behavior, is defined as V turn-on -V turn-ambipolar . I on is defined as the drain current when V gs -V turn-on = 1V. These definitions are used throughout this paper.

A. Transfer characteristics
shows the comparison of the TMG TFET's transfer characteristics with those of the HMG and SMG TFETs. The SMG TFET with a work function of 4.1eV is referred to as the LW TFET, and the SMG TFET with a work function of 4.7eV is referred to as the HW TFET. The gate structure parameters are summarized in Table I. It can be observed that the shapes of the transfer curves of the LW and HW TFETs are almost identical, except that V turn-on is 0V for the LW TFET and 0.6V for the HW TFET, which is consistent with the difference in gate work function between these two devices. Due to the heterogeneous gate material, the curve of the HMG TFET follows the curve of the LW TFET in the on-state, and it follows the curve of the HW TFET in the off-state. The modulated band profile of the HMG TFET near the source region leads to a higher I on and a reduced SS. 18 The curve of the TMG TFET coincides with the curve of the HMG TFET in both on-and off-states, which indicates that the switching characteristic is not affected by the additional D-gate of the TMG TFET. Steep switching behavior requires the off-and on-state transition of the tunneling barrier width to be strongly dependent on the gate voltage. In the HMG and TMG TFETs, the tunneling distribution is controlled by the D-gate (C-gate in the TMG TFET) when the devices are in the off-state and by the S-gate when the devices are in the on-state. Fig. 3(b) quantitatively illustrates tunneling barrier width as a function of gate voltage (V gs -V turn-on ) for the SMG and TMG TFETs. In the SMG TFET, the barrier width slowly decreases as V gs increases. When the TMG TFET is in the off-state, the tunneling barrier width is larger than that of the SMG TFET because the energy band is pulled up by the C-gate. Once the E c minimum near the source is below the E v in the source region, tunneling occurs. In this situation, the barrier width of the TMG TFET suddenly decreases, which corresponds to its sharply ascending I ds -V gs curve. Thus, the BPM effect in the HMG and TMG TFETs significantly improves the switching behavior of the devices.
The most obvious difference between the transfer curves of the TMG and HMG TFETs concerns ambipolar behavior. The ambipolar behavior of TFET devices is related to their internal structure: when the valence band of the channel close to the drain side is above the conduction band of the drain region, tunneling can occur at the drain side. In this situation, the device is in the ambipolar-state. As shown in Fig. 3(a), the ambipolar window of the TMG TFET is 269mV, compared to 200mV for the HMG TFET. This difference can be explained by the fact that the ambipolar characteristic of the TMG TFET is improved mainly by the band profile close to the drain region, which is engineered by the additional D-gate. This hinders the occurrence of tunneling and provides a large ambipolar window and much reduced ambipolar current. Fig. 4 shows the typical output characteristics of the three devices and their second derivatives. The devices used in the simulations were identical to those shown in Fig. 1; the drain voltage varied from 0 to 1.5V and the gate voltage (V gs -V turn-on ) was set at 1V. It can be observed that each output curve can be divided into three regions, i.e., exponential, linear, and saturated regions. The exponential region in the output behavior of the TFET devices can be explained by the large quantum capacitance of the accumulation channel in the on-state. In the presence of the surface charge layer, the response of the energy bands in the channel to the external gate voltage becomes very small, but the level at which the channel potential is pinned depends on the Fermi energy in the drain region. For small amounts of V ds , the drain voltage is applied at the source-channel junction directly, thus resulting in the aforementioned exponential behavior. 25 Furthermore, a certain minimum amount of drain voltage is required to turn the device on. Similar to the gate threshold voltage based on the transfer characteristics in MOSFETs, the drain threshold voltage V td in TFET devices is defined as the drain voltage for which the drain current dependence changes from exponential to linear, and V td can be extracted as the drain voltage where the second derivatives of the differential curves reach their maximum values. 26 As shown in Fig. 4, the V td values of these three TFETs are almost identical. This suggests that output behavior is not affected by the BPM effect, although the drain currents of the HMG and TMG TFETs are greater than the drain current of the SMG TFET.

A. Effect of work function difference
In order to analyze the relationship of gate work function and device performance, HMG and TMG TFETs with different gate work functions were examined. Due to the basic principle of the BPM effect, device performance depends on the work function difference of the gate, rather than on specific work function values of each part of the gate. For example, the transfer curve of the HMG TFET with WF S-gate = 4.1eV and WF D-gate = 4.5eV is almost the same as that of the HMG TFET with WF S-gate = 4.3eV and WF D-gate = 4.7eV; the only difference is their V turn-on values, as shown in Fig. 5. This is similar to the case of the HW and LW TFETs. Therefore, in our simulations, WF S-gate was set at 4.1eV, and WF D-gate (WF C-gate in the TMG TFET) varied. Work function difference ( WF) is defined as WF D-gate -WF S-gate in the HMG TFET and WF C-gate -WF S-gate in the TMG TFET. Fig. 6(a) shows different energy band profiles of the HMG TFET depending on WF when V gs = 0.4V, V ds = 1V, and L S-gate = 6nm. As WF increases, the energy band in the middle of the channel is elevated, and the local minimum in E c at the source side becomes more significant. It is worth mentioning that the difference between the local minimum and maximum in E c of the channel region is smaller than WF. As shown in Fig. 3(b), these special band profiles are useful for improving the switching characteristic of the TFET devices. Furthermore, the BPM effect is more obvious when WF increases. As shown in Fig. 7, when WF varies from 0 to 0.4eV, the value of SS decreases significantly as I on increases; when WF reaches 0.4eV, SS decreases slightly. Similar simulations were also carried out for the TMG TFET ( Fig. 6(b)). The energy band profile nearly coincides with that of the HMG TFET in all situations, except that the energy band contour at the drain side becomes less steep. This indicates that the energy band profile at the source side is hardly affected by the additional D-gate in the TMG TFET, which is also consistent with its electrical properties. As shown in Fig. 7, the values of SS and I on of the TMG TFET are almost identical with those of the HMG TFET in all situations. This suggests that the D-gate does not affect on-state characteristics in TMG TFETs; details about device performance in off-and ambipolar-states will be presented in the next section.

B. Effect of the length of the S-gate
To investigate the influence of gate configuration, HMG and TMG TFETs with different L S-gate values were examined. L gate was kept at 50nm and WF was set at 0.6eV. L S-gate in the HMG TFET varied from 0 to 50nm as L D-gate decreased from 50 to 0nm, and L S-gate (L D-gate ) in the TMG TFET varied from 0 to 25nm as L C-gate decreased from 50 to 0nm. The I ds -V gs curves of the two devices are shown in Fig. 8. When L S-gate in the HMG TFET increases from 0 to 10nm, the transfer curves become more steep when the devices turn on, and V turn-on decreases because the channel region controlled by the S-gate is extended. Similar results can be also observed for the TMG TFET.
When L S-gate >10nm, the difference between these two devices is clear. As shown in Fig. 8, the I off current in the HMG TFET increases as L S-gate increases. However, for the TMG TFET, I off remains unchanged. The results illustrated in Fig. 9 are equally distinctive. In these simulations, the energy band profile was extracted when V gs = 0.4V. As L S-gate in the HMG TFET increases, several phenomena concerning the energy band profile can be observed. First, when the local minimum in E c close to the source region is generated gradually, the switching behavior of the HMG TFET is improved by the BPM effect. Second, the local minimum in E c becomes more significant, which enlarges the overlap between E v in the source region and E c in the channel in the same V gs . This means that the gate voltage required to turn the device on is reduced, and V turn-on decreases as L S-gate increases. On the other hand, the tunneling at the drain side is controlled by the D-gate, which is not affected by the increase in L S-gate . Thus, V turn-ambipolar in the HMG TFET remains unchanged, and the difference between V turn-on and V turn-ambipolar is reduced. Once V turn-on = V turn-ambipolar , the tunneling can occur simultaneously at the source and drain sides, and the off-state of the HMG TFET disappears. A further increase in L S-gate results in V turn-on < V turn-ambipolar and leads to an elevated I off , as shown in Fig. 8(a).
In the TMG TFET, the work function of the D-gate is lower than that of the C-gate. The energy band close to the drain region is pulled down by the D-gate, and it becomes less steep as L S-gate increases. As shown in Fig. 9(b), the energy band profile of the TMG TFET nearly coincides with that of the HMG TFET in all situations except for that at the drain side. The special energy band contour suppresses the tunneling at the drain side and reduces V turn-ambipolar simultaneously. The quantitative relationship between the ambipolar window (V turn-on -V turn-ambipolar ) and L S-gate is shown in Fig. 10. The value of the ambipolar window of the HMG TFET decreases continually as L S-gate increases. When L S-gate in the TMG TFET is smaller than 10nm, the value of the ambipolar window decreases as L S-gate increases, but it does so at a slower rate than in the HMG TFET because the D-gate is not large enough to thoroughly suppress the tunneling at the drain side. When L S-gate >10nm, the value of the ambipolar window stops decreasing and starts to rise. In the TMG TFET, V turn-on is always larger than V turn-ambipolar . Thus, when V turn-ambipolar < V gs < V turn-on , no tunneling occurs at either the source or the drain sides, which corresponds to the off-state of the TMG device. Therefore, the TMG TFET can suppress the ambipolar effect and provides a superior design window compared to the HMG TFET.

C. Design window of gate configuration
In the previous two sections, the influence of L S-gate and WF on TFET devices were studied independently. To obtain an optimized design of the gate configuration in the HMG and TMG TFETs, the impacts of L S-gate and WF on the design window were investigated together. In the simulations, L S-gate in the HMG TFET varied from 0 to 50nm, and in the TMG TFET, it varied from 0 to 25nm; L gate was kept at 50nm. WF varied from 0.3 to 0.8eV. As shown in Fig. 11(a), when L S-gate increases from 0 to 10nm, SS decreases significantly due to the BPM effect. Once L S-gate exceeds 10nm, SS in the HMG TFET increases and becomes saturated in the range of 20 to 40nm because of the aforementioned elevated I off due to the ambipolar effect. Similar phenomena can be observed when WF is equal to 0.8eV; the only differences are the minimum and maximum values of SS and the corresponding value of L S-gate . When WF is equal to 0.3eV, I off of the HMG TFET remains 10 -17 A/mm because the ambipolar window is not affected by WF in this situation, as shown in Fig. 11(b). When L S-gate is larger than 15nm, the position corresponding to the local minimum E c is farther away from the source region ( Fig. 9(a)); this means that the tunneling path increases and tunneling current decreases when the device turns on. Thus, the value of SS increases slowly when L S-gate varies from 15 to 50nm. Therefore, optimization of the HMG TFET involves a tradeoff between improved SS and a corresponding increased I off due to the ambipolar effect. In contrast, the

D. Gate length scaling effects
To investigate whether the BPM effect was present when the feature size of the devices decreased, the performances of HMG and TMG TFETs with different gate lengths were also examined. In the simulations, WF was maintained at 0.6eV and the supply voltage was 1V. The devices of HMG and TMG TFETs represent SMG TFETs when L S-gate is equal to 0nm.
As the gate length of the TFET device decreases from 50 to 15nm, the direct tunneling from source to drain regions increases significantly and dominates the composition of the off-state current. Thus, SS increases significantly, as shown in Fig. 12. When the gate length is shorter than 20nm, the curve of the HMG TFET is similar to that of the TMG TFET because the ambipolar current is much lower than the direct tunneling current. Furthermore, the SS values of both HMG and TMG TFETs can be minimized when gate length reaches 15nm, even when the main leakage is not due to the ambipolar effect. The optimized value of L S-gate is maintained around 5nm when L gate varies from 50 to 15nm. Therefore, the optimized value of L S-gate is independent of L gate ; rather, it is largely determined by WF. These results indicate that device performance of TFETs can be enhanced by the BPM effect regardless of the gate length.
To gain more insight into the scaling-down characteristics of TFET devices, the performances of the three TFETs at different levels of supply voltage were thoroughly investigated. In the simulations, L S-gate was set at 6nm and WF was kept at 0.6eV; Other parameters were set at their default values. As shown in Fig. 13, when the supply voltage is 1.5V, I on of the HMG TFET is about three times higher than that of the SMG TFET, but the HMG TFET has a high I off because of the ambipolar effect. The TMG TFET has the same I on as the HMG TFET, but its I off is smaller compared to that of the HMG TFET and is as large as that of the SMG TFET. These results confirm that I off induced by the ambipolar effect can be effectively suppressed by the TMG structure. On the other hand, when the supply voltage is 1V or 0.5V, I off is not decided by the ambipolar effect. I on and I off of both TMG and HMG TFETs are almost identical in these situations. Therefore, it can be speculated that the TMG TFET has superior current performance even at low supply voltage.
Note that an effective approach for boosting the device performance of MOSFETs is to enhance the carrier mobility. However, this method does not make much sense in TFET devices because the electrical characteristics are mainly determined by the space distribution of tunneling probability and The work function difference ranges between 0.3eV (square), 0.6eV (triangle), and 0.8eV (circle). In the HMG TFET, the reason for the increased maximum value of SS is that I off is higher due to the ambipolar effect. However, this effect can be significantly suppressed by the additional D-gate in the TMG TFET.
the energy band profile. In many studies on TFETs, including examinations of hetero-source, 11,12 dual-material-gate, 27 and hetero-gate-dielectric 28 structures, the BPM effect was actually used to improve the properties of the devices, but it was not explained clearly how this was achieved. In our study, the BPM effect was achieved directly by introducing different gate configurations with lateral work function differences. Thus, the energy band contours can be easily tailored to improve the device characteristics of TFETs.

V. CONCLUSIONS
In this paper, a TFET with a symmetrical TMG structure was proposed. Three TFETs with different gate configurations were analyzed and compared in detail. The TMG TFET demonstrated excellent electrical performance. The enhanced on-state characteristic of the TMG TFET was due to the source-channel BPM effect, which led to an abrupt transition between the off-and on-states. In addition, the improved ambipolar-state performance was attributed to the drain-channel BPM effect, which suppressed the ambipolar effect and resulted in a low off-state current. Conventional approaches for suppressing the ambipolar effect involve using an underlapped drain structure 29 or an asymmetrical doping profile between the source and drain regions. 7 The TMG structure was shown to be another effective way to provide a large channel-drain tunneling barrier, which inhibited the tunneling at the drain side in the ambipolar-state. Also, the optimization of gate materials and gate structures was conducted, and it was demonstrated that the TMG TFET had a better design window and a superior process tolerance compared to the HMG TFET. It can be concluded that the device performance of TFETs might be boosted by the BPM effect, which can be achieved directly by gate structure engineering. FIG. 13. I on versus I off for the SMG, HMG, and TMG TFETs with different gate lengths and supply voltages. The length of the S-gate (L S-gate ) was set at 6nm and the work function difference ( WF) was 0.6eV. At nearly every technology node, the TMG TFET has an increased I on and a reduced I off compared to the SMG and HMG TFETs.