Study of impact of LATID on HCI reliability for LDMOS devices

This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation Doping (LATID) techniques for p-body. It seems that optimization of the device with LATID angle for p-body in nLDMOS is important to achieve improved HCI performance and observed that HCI degradation is minimum for 30 LATID for p-body. We observed Si/SiO2 interface trap under various stress conditions, were evaluation based on our Sentaurus simulation, and we compare trapped charge density and distribution for various LATID angles and it was less for 30 tilt. Trap-related models were employed to perform Ron and Id,sat degradations during the HCI stress test. So nLDMOS device with 30 tilt angle for p-body shows better HCI performance compared to other LATID. Also our new proposed device structure shows less HCI degradations when compared with silicon data of HCI degradations for other nLDMOS structure.


Introduction
Lateral DMOS transistors are widely used as integrated high-voltage switches and drivers in mixed-signal integrated circuits. The extended drain structure with isolation either by STI or Thermo-oxide and "RESURF" technology [1] are widely used to obtain high-voltage capability while keeping low on resistance so to optimize the specific resistance versus breakdown voltage trade-off. In past, a rugged LDMOS for a 0.35μm Linear BiCMOS technology, which achieves a strongly enhanced electrical SOA, has been presented [2][3]. A buried body implant was added to suppress the parasitic bipolar transistor; hence no snapback was observed in the I-V characteristics: this important feature enables an extension of the current curves to higher drain voltages, when impact ionization at the drain side of the drift region becomes dominant. Thus, an unusual current "enhancement" is reported at large gate voltages with a subsequent saturation of the current at high drain biases. High operational drain and gate biases make the LDMOS device vulnerable to the damage caused by hot-carrier injection (HCI), and the reliability characterization in STI based LDMOS devices have recently drawn much attention [2][3][4][5][6]. However, very little is known on the hotcarrier injection effects in the rugged LDMOS device when it is operated in the high impact-ionization regime. Mechanism of this reliability issue was not well understood. High kinetic energy of carriers is gained under the influence of high lateral fields in MOSFET channel and pinch-off region of the transistor. Hot carrier will be generated when non-equilibrium energy distribution is reached and impact ionization will be triggered. Sufficient energy, approximately 3.6eV for electrons and 5.0eV for holes in silicon can be acquired by hot carriers to surmount the energy barrier at Si/SiO2 interface or tunnel into the oxide and the effect will be raised when injected carriers interact with the oxide. This instability may appears and cause a device parameter shift in a long term operation of the device [3][4][5]. In this paper, the HCI-induced degradation of the double diffused LDMOS has been investigated for different tilt angle implantations i.e., Large Angle Tilted Implantation Doping (LATID). Special attention has been given to the impact of the current "enhancement" on the ¨∆Id,sat and ¨∆Ron and their dependence on the LATID and selfheating due to the power dissipation.

Experimental setup
The experimental setup was designed as flowchart in Fig.  2. Practically, the comparisons of the device degradation are performed by confrontment of IV curve before and after stress time on the device structures. Thus, degradation trend for on state resistance (RON) and drain current saturation (Id,sat) were calculated for different stress time (0s, 100s, 1000 s, 10,000 s and 100,000 s) but for 100s we didn't get any shift in HCI or may be very less shift and thus we not presented HCI results for this case but we analysed remaining stress times. On-state resistances (RON) were calculated at drain and gate voltage equals to 0.1V and 5V respectively while drain current saturation calculated at 40V of drain and 5V of gate voltage. Degradation, thermionic HCI and classical lucky electron models were invoked in the device simulation to perform This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits distribution, and reproduction in any medium, provided the original work is properly cited.

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Article available at http://www.matec-conferences.org or http://dx.doi.org/10.1051/matecconf/20164402007 the interface trap generation due to HCI. A process of electrons tunnel through a barrier in the presence of a high electric field was taken into account by using Fowler-Nordheim model. While, the lucky-electron model provides an estimate of the probability that some carriers in silicon will be transmitted to the oxide by overcoming the local energy barrier at the Si-SiO2 interface [7][8][9].  We also compared HCI results of our proposed nLDMOS structure with silicon HCI results for other nLDMOS device and we achieved better HCI results as compared to Silicon HCI results. This comparison with silicon HCI data we provide in next section of Results and discussion.

Results and discussion
As we shown in Figure 3, Trapped charges at Si/Sio2 interface are different for different LATID angle implantations. From Table 1. and Figure 3, It is clearly shows that trapped charge is least for 30 0 tilt and worst for 60 0 tilt implant. Further trapped charges for 7 0 and 30 0 seems to be equal in numerical value from Table 1 but area of trapped charges for 7 0 tilt is more than compared to 30 0 tilt. So as we know HCI degradations is because of trapped charges into the oxide region of Si/Sio2 interface and HCI degradation will be more with more traps that occurs in oxide regions. Hence we got good HCI performance for 30 0 tilt and least for 60 0 tilt implant technique. We performed HCI stress test for time 0s, 1e3s, 1e4s and 1e5s and measured on-resistance shift/degrade (∆Ron) and drain saturation current shift (∆Id,sat) and we summarize all HCI results with different LATID angles in Table 1. When we analyse the results we can explain that our new nLDMOS structure shows very good HCI performance. For instance Ron shift for 1e5 seconds HCI stress is 0.057%, which is best and Id,sat shift for HCI 1e5 seconds is 0.398% both for 30 0 tilt angle. So these results very good for HCI stress test concern. It is possible for us to achieve this HCI performance because we put lot of effort to redesign the device so that impactionization hotspot should happen at location away from gate and below the surface so that the hot carriers that generate and experience high lateral applied field should not reach or overcome the Si/Sio2 potential barrier and become trapped into gate-oxide region. So we kept this in mind and re-designed our device which helps to get better HCI performance and device can pass HCI life time reliability test. 02007-p.2 Additionally it can see clearly or can be referred from figure 5, our proposed new nLDMOS structure shows better HCI performance compared to silicon HCI results as ∆Ron% and ∆Id,sat% curves of proposed structure are more flat compared to silicon data of reference structure and further from figure 5, one can notice that ∆Ron% is more severe than ∆Idsat% when compared between proposed and referred structures. So that shows less trapcharges are going into oxide that is gate-oxide and it is because impact ionization rate at offstate bvd is less than referred structure as silicon data. It indicates our device design is good for ensuring long term reliability.

Conclusion
We have studied HCI performance in related to trapped charges at Si/Sio2 interface and that can be optimized by implementing LATID technique for p-body. We also observe that in our proposed n-LDMOS device and may be possible for any nLDMOS devices, the 30 0 tilt angle implantation for p-body shows less traps thereby achieving better HCI results. Therefore the device life time reliability is improved. Hence it's one of the better solution for the devices to be optimized in such a way that impact-ionization hotspot at off-state bvd should be away from gate and below the silicon interface and this type of device design helps to achieve less trap-charges and therefore improve HCI performance.