Computer simulation of electrophysical effects in CAD chip design

. The article discusses the characteristics and functions of modern systems for computer-aided design of submicron microcircuits. The main developers of this class of systems are Cadence Design Systems, Mentor Graphics and Synopsys. The paper analyzes in sufficient detail the composition and functionality of software tools for the development of electronic equipment provided by these companies and allowing solving functionally different tasks within the framework of the VLSI design route. The electrophysical effects of the submicron level are analyzed, which include dynamic effects associated with parasitic parameters, crosstalk, signal stability, ohmic busbar voltage drop, electromigration, and local heating of the crystal .


Introduction
The creation of VLSI, which are the element base of modern electronic equipment, was predetermined by the presence of many intractable problems that arose in the process of developing electronic equipment based on discrete elements, namely: -large dimensions (packing density); -high power consumption and dissipation; -low reliability; -a long technological cycle of step-by-step manufacturing of discrete elements and their installation into a single circuit system; -high labor intensity in manufacturing; -low dynamic parameters of signal processing. Therefore, the development of technology for information processing required the creation of a fundamentally new method of designing electronic equipment. The layout of discrete elements into a single IC began to be used, all elements of which were manufactured simultaneously and in a single technological process in (or on) a single substrate.
At present, the world market of VLSI computer-aided design systems is dominated by three companies that have concentrated a significant part of this rapidly developing area [1]. These firms are Cadence Design Systems, Mentor Graphics and Synopsys. The article is devoted to the products of only these companies, since they meet the needs of almost all specialists in the field of various areas in the development of microelectronic devices.
At present, the world market of VLSI computer-aided design systems is dominated by three companies that have concentrated a significant part of this rapidly developing area [2]. These firms are Cadence Design Systems, Mentor Graphics and Synopsys. The article is devoted to the products of only these companies, since they meet the needs of almost all specialists in the field of various fields in the development of microelectronic devices

Model and method
The products of Cadence, as well as other software developers for the development of electronic equipment, are currently structured according to the so-called platforms, which include packages of unified programs that allow solving functionally different tasks within the framework of the VLSI design route, including. h. system-on-a-chip (SOC) type. Let us consider brief characteristics of some of the design programs corresponding to the most critical stages of VLSI design [3].
1. Verification platform Incisive: -unified simulator Incisive -a simulation program (simulator) built on a single-core architecture that supports open design and verification standards, incl. at the transaction level, allows you to analyze in high-level description languages, generate tests, other programs and utilities for verifying microcircuits with submicron design standards; -Incisive AMS -a single-engine mixed signal simulator that provides verification of the entire project -from design concept to topological implementation; -NC-SystemC -allows you to model projects at the transaction level at a speed hundreds of times faster than with the RTL representation, supports verification procedures using the SystemC language, ideal for analyzing the project architecture, developing a test sequence and verifying embedded software; -NC-Verilog -the most common simulation program in the Verilog language, provides a high level of performance, visual signal control, test coverage analysis; -NC-VHDL -a simulator using the VHDL description language; -Palladium -accelerator / emulator, provides a hundred times or more simulation acceleration and more than 10,000 times acceleration when emulating a circuit in multi-user mode.
The Incisive platform allows you to work with both blocks, incl. with SF blocks, and to perform verification of the entire project as a whole. In fact, block verification goes in tandem with its design using the same description language. Later, system verification is carried out, which is also inseparable from the process of "joining" the project from partsblocks [4,5].
2. Encounter is a product platform for designing digital ICs: -SoC Encounter -a functionally complete program that implements the entire design cycle from RTL description to topological information in GDSII format, the complexity of the project is up to 50 million or more gates, the minimum element size is 180 nm, the next versions are being prepared; -Nano Encounter -supports the end-to-end design of SF blocks and crystals with a nonhierarchical structure with a complexity of up to 10 million gates; -NanoRoute Ultra is a unified routing program that takes into account the "fine" effects of sub-micron projects, tracking signal integrity conditions (SI -signal integrity); -CeltIC Crosstalk Analyzer -the industry's most widely used crosstalk analysis program used by a large number of silicon workshops to provide SI; -SignalStorm NDC -precision "calculator" of ohmic voltage drops, monitors SI also taking into account induced noise; -Encounter RTL Compiler -a new generation synthesizer program with a unique system for building a delay-optimized topology; -BuildGates is also a new synthesis program that provides a significant increase in productivity compared to analogue programs, incl. other firms, requires much less manual intervention during the design process; -Physically Knowledgeable Synthesis (PKS) -a physical (up to the topology level) synthesizer that optimizes placement, timing, power consumption and takes into account crosstalk; -Silicon Ensemble PKS -a placement and tracing program has been added to the PKS package, as well as a number of programs for detecting and correcting errors in the project, incl. taking into account the need for SI; -Encounter Test Solution -test program development tools in accordance with a unified methodology, provides a high level of project coverage with tests; -TSMC Libraries -Cadence is an authorized supplier of 150nm, 130nm-90nm-45nm and 28nm libraries to this world's largest silicon workshop [6,7].
The software products of the Encounter digital platform provide an acceleration in the design of complex VLSI built according to a hierarchical principle, while creating the socalled. silicon virtual prototypes (Silicon Virtual Prototypes -SVP). This technique allows developers to assess the degree of influence of their design decisions on performance and other characteristics of a crystal already at an early stage of design.
In terms of topology design in 180 nm and below projects, Cadence pays special attention to the optimization of interconnect delays, power consumption and signal integrity. PKS pushes the limits of traditional synthesizer software and optimizes placement, timing and other factors at the same time. Virtually eliminates iterations between synthesis and layout-routing, while synthesizing, timing, placement, timing chaining, and routing are linked together for minimal development time [8].
As is known, in nanometer VLSI projects, delays in interconnection circuits play a major role. In this regard, it is also important to take into account the interference induced in interconnections, incl. in terms of signal integrity. Verification of nanometer projects in the topological part should be carried out on the basis of three-dimensional models of parasitic parameters, taking into account ohmic voltage drops across the buses. Crosstalk analysis makes it possible to calculate additional "induced" delays and to identify failures in the operation of the circuit due to interference. Accounting for ohmic voltages, level instability of the "common" bus and electromigration allow at the early stages of design in an optimal way, for example, to design a power bus system.
3. Virtuoso custom VLSI design platform: -Assura DRC -topological tolerance control program (DRC -Design Rule Checker)supports interactive and batch modes of operation, uses a hierarchical representation of the array of controlled data; -Assura LVS (Layout vs. Schematics) -a program for controlling the final topology for compliance with a netlist or description specified in any format; -Assura Parasitic Extraction -an accurate means of extracting parasitic parameters; -Diva Physical Verification -provides topological verification of cells, blocks and small chips in real time: -NeoCell Analog Physical Synthesis -converts analog circuitry into custom optimized topology and synthesized circuits: amplifiers, filters, voltage regulators, etc.; -PacifIC Static Noise Analyzer -analyzes combined noise sources including crosstalk, ohmic voltage drops, etc. for custom digital projects; -Substrate Noise Analyst -analyzes induced substrate noise and allows for accurate calculations of such noise to ensure the integration of the entire crystal; -Virtuoso AMS Designer Simulator -a powerful and efficient simulation program for the design and verification of mixed SoC type ICs; -Virtuoso AMS Silicon Analysis -compares topological design codes and technological limitations, calculates parasitic parameters (resistances and capacitances), analyzes power circuits in analog circuits to detect cases of unacceptable ohmic voltage drops and electromigration; -Virtuoso AMS-HF Silicon Analysis -in addition to the above program provides extraction of inductance, used in the same place; -Virtuoso Chip Assembly Router -a router for custom blocks and the final "assembly" of crystal from SF blocks, compatible with mixed and pure analog microcircuits at any level of hierarchy; -Virtuoso Chip Editor -editor for finishing operations when designing VLSI, fully compatible with the Encounter platform, uses the Virtuoso Layout Editor software environment and infrastructure; -Virtuoso Device Modeling -a package that provides a mechanism for communication between the project and the means of verification during the development of IS; -Virtuoso Layout Editor -the main tool for the layout design of custom chips and blocks, supports the physical representation of digital, mixed and analog circuits at the level of devices, cells and blocks; -Virtuoso Multi-mode Simulation -combines four simulation tools and is able to verify analog, mixed, microwave and full-chip circuits. Compatible with SPICE, FastSPICE, microwave and analog circuit simulation systems, used with all types of circuitry; -Virtuoso Schematic Editor -a multi-level graphical illustrator of the design environment that helps to effectively implement each stage of VLSI development: from the top architectural level, described in a standard language, to the final structural representation; -Virtuoso Specter Circuit Simulator -provides simulation of analog and mixed signals at the transistor level; -Virtuoso Specter RF Simulation Option -microwave and high-frequency IC simulation program, works in conjunction with Virtuoso Analog Design Environment; -Virtuoso UltraSim Full-chip Simulator -in fact, it is a full-size, down to the chip level, version of the FastSPICE simulator used in the verification of a project or an entire system; -Allegro AMS Simulator (formerly known as PSPICE Studio) is an industry-standard program for simulating analog and analog-to-digital circuits, taking into account the influence of the package and the printed circuit board [9,10].
Thus, Virtuoso platform software products basically perform efficient (with an acceptable balance between computational performance and accuracy) device simulation. It is important that when parameterizing library models of elements, the results of real measurements on test structures are widely used, after analysis of which the models are supplemented with the necessary coefficients, specific parameters, and other means that make it possible to bring the results of calculations as close as possible to physical quantities.
Another feature of this platform is the analysis "at the silicon level", i.e. taking into account the real topology and other calculated parameters of semiconductor structures. This includes spurious parameter extraction, underlay noise modeling, signal integrity analysis, and power circuit correctness analysis [11].

Mentor Graphics
1. Model Sim is a tool for modeling digital projects described in Verilog and VHDL languages, a fast and efficient program that also provides the extraction of parasitic parameters; 2. CommLib / ADVance CommLib -libraries of behavioral templates oriented towards telecommunication applications. These libraries are shared with the AccuSim, Eldo and Continuum simulators, and the latest ADVance CommLib is used with the ADVance MS simulator. Libraries include hundreds of functions ranging from primitive logic gates to complex telecommunications devices. Each model is parameterized to allow the customer to customize the designed devices to the existing requirements at the system level. Because CommLib's behavioral models are written in HDL-F or VHDL-AMS, typical SPICE macro models are used most effectively. The CommLib library contains: -analog and digital filters, PLL circuits; -data converters; -modulators / demodulators; -digital cells in a wide range.
3. Eldo RF is actually an extension of the Eldo transistor level simulation program into the field of microwave technology. The use of 3-dimensional models, multi-stage algorithms allows this program to calculate circuits consisting of thousands of transistors with an accuracy not previously available. This package includes: -steady state analysis; -low-signal steady state analysis; -phase analysis of noise at steady state; -analysis of the modulated steady state; -calculation of S-parameters on a small and large signal; -analysis of circuit stability; -optimization; -behavioral modeling in Verilog-A; -microwave signal measurement functions. Eldo RF contains voltage controlled oscillators and frequency dividers, provides accurate prediction of the phase noise density both in the immediate vicinity and in the remote area from the source. The program works with digitally modulated signals and supports common modulation formats such as QPSK, QAM, GFSK, C4FM, EDGE. Eldo RF uses the same models as the main Eldo program and is compatible with the standard SPICE netlist. Design kits including model parameters for Eldo RF are supplied as part of their libraries by leading silicon workshops [12] 5. FPGA Advantage 6.2 is a complete integrated software environment for FPGA design. Includes a full set of functions: circuit input, verification, synthesis, firmware management; 6. As a leader in programmable logic VLSI design, Mentor Graphics provides the most complete and efficient set of synthesis solutions. Precision Physical Synthesis integrates an RTL circuit into a complete solution using an intuitive user interface, the latest optimization technologies, internal debugging and troubleshooting. Precision Physical SA is a popular physical optimization program performed on a third-party EDIF netlist; 7. LeonardoSpectrum -also the industry's most famous FPGA and custom VLSI synthesis package.

Synopsys
Synopsys software products are divided into three basic platforms: 1. The Galaxy design platform is an open integrated system that uses the Milkyway database as a data logical basis (Fig. 1). Galaxy maintains constant control of timing parameters and signal integrity, uses unified libraries of elements throughout the entire VLSI design cycle. This platform is certified by successful projects with a topological norm of 90 nm; 2. The Discovery verification platform (Fig. 2) is an integrated system that allows for equivalence control at the level of RTL descriptions, as well as verification of mixed signal schemes. The procedures used in the platform include analog-to-digital device modeling, system level verification, IP block verification, code coverage completeness analysis, functionality control, test sequence generation, formal analysis. A feature of the platform is the use of verification IPs of the DesignWare family, compatible with industry standards such as PCI, PCI-X, PCI Express, USB 2.0, Ethernet, AMBA, memory of various types, etc., while DesignWare IPs operate in the language environment Vera, Verilog, VHDL, C; − 3. a set of software tools for production purposes, which, in turn, includes: − means of synthesizing information for photomasks − means of compiling information for the production of photomasks; − means of verification of lithographic processes; − means of certification of photomasks; − powerful package of technological modeling programs (TCAD).

Research and results
A few years ago, the complex of works on the physical design of a crystal included only direct design, verification of electrical rules (circuitry) and, from the field of physical verification, control of compliance with the topology of the electrical circuit . At the present stage, when designing SoCs with topological norms from the deep submicron region, the traditional control of various kinds of norms is not sufficient. As the design norms decrease, the delays not of the gates, but of the interconnections, play an increasingly important role. In this case, an increase in the average length of the interconnection route on the chip occurs. This means that in the future, the delays of interconnections will dominate over the own delays of logic elements. In this sense, typical solutions are modern embedded processor cores ("cores"), initially connected to long "global" buses. [14].
SoC verification tools and techniques, in addition to the traditional aspects of norm and design control, must take into account time and power characteristics, signal integrity conditions, electromagnetic effects on a chip, conductor migration and thermal effects. The control of topological design rules is performed after the placement and routing of the chip. Control programs are also used by template and die makers when taking a particular design into production. Electrical code monitoring programs detect short circuits, unconnected traces, and unconnected circuit nodes. Another type of control -for compliance with the topology of the electrical circuit -is based on the extraction of the electrical circuit based on the final topology of the crystal and comparing this circuit with the input description.
When developing VLSI with submicron design standards, it is necessary to take into account a number of electrical and physical effects [15]. These include dynamic effects associated with parasitic parameters, crosstalk, signal stability, ohmic bus voltage drop, electromigration, and local heating of the crystal.
Estimation of parasitic parameters -R, L and C and associated time characteristics of transient processes -for submicron crystals should be carried out at an early stage of design. After the topology is developed, an accurate calculation (extraction) of parasitic parameters is carried out and, taking into account the refined values, the dynamic parameters of the system devices are recalculated. There are three methods used in the extraction of parasitic parameters. Two-dimensional (flat) models assume uniformity of signal propagation in all directions, the three-dimensional nature of crystal elements is ignored. For projects based on the "deep" submicron, this gives distorted calculation results, since three-dimensional effects such as capacitive bulk bonds and non-orthogonal component profiles are not taken into account. The so-called quasi-three-dimensional methods give more accurate results. Three-dimensional methods are the most accurate. For large projects, it requires large computing resources and, accordingly, the cost of computer time. Two-dimensional models are used for preliminary calculations of parasitic parameters. Taking into account these data, as well as taking into account the geometric dimensions, circuit parameters and the number of loads, the circuits that are critical in terms of speed are determined. These circuits are already verified using 3D models [16].
In submicron crystals, inductive effects must also be considered, especially those associated with long traces, such as clock wiring or other low-resistance traces. For short traces and conductors, the influence of parasitic inductance is insignificant, since the duration of the signal fronts is much greater than the signal delay time. Therefore, the induced inductive effect occurs only in situations where the signal paths are sufficiently long and the rise times are short. The exact calculation of the parasitic inductance of the crystal busbars is much more complicated than the parasitic capacitance.
The robustness of a signal characterizes its ability to generate the correct response in a circuit. Thus, this characteristic is related to noise immunity. An insufficiently stable signal can lead to a system failure or to rejection of the manufactured crystal. The reasons why signal instability occurs should be discovered in the early stages of chip development. Signal stability checks are carried out at every stage of the design, in particular at the block level and at the final chip level [17].
Crosstalk is the interaction between signals in two different electrical circuits within the same crystal. The chain that interferes is called the "aggressor", and the one that accepts it is called the "victim". The chain can be both a victim and an aggressor at the same time. When the aggressor switches, and the victim does not change the status of the signal, the victim is affected by interference, while there is some delay in the "mirror" signal. The amplitude of this induced interference depends on the magnitude of the cross capacitance and on the output impedance of the signal source. Buffer signal repeaters are used to limit interference. In addition, the magnitude of crosstalk can be reduced by increasing the distance between the receiver and transmitter of interference and by increasing the width of the conductors. All this, of course, complicates the design and leads to an increase in the area of the crystal.
The ohmic voltage drop on the power buses at modern power consumption can be significant. High clock speeds and thin conductors lead to failures precisely because of the large voltage drops across the buses. Ohmic effects lead, in particular, to a weakening of the load capacity, to a deterioration in noise immunity and to an increase in signal propagation delays: with an additional 5% voltage drop, the delay increases by an average of 15%. This means that it is necessary to calculate the ohmic voltage drops at the early stages of design and further refine them after the topological layout of the crystal [18].
Modern software tools allow, at the stage of a fully designed topology, to conduct a fairly accurate calculation of the power distribution at the transistor level. Such calculations require a significant amount of computer time, so unacceptable ohmic voltage drops should be identified as early as possible in the layout design phases.
For verification of the entire chip, a dynamic estimation of the power distribution at the gate level is more preferable. This evaluation can be performed both before and after placement and routing. Power distribution control is carried out at the design level of each unit. Then the corresponding parameters are integrated at the chip level and used to recontrol the distribution of power across buses and active devices, already taking into account the real topology of the crystal [19].
The most critical and fastest circuits on a chip are usually the distribution circuits for clock (synchronizing) signals. Often, the overall performance level of the system depends on the quality of the clock wiring and the chosen strategy for distributing the clock signals. Submicron crystals have high-frequency synchronizing circuits, in which there are large load branchings. This creates the prerequisites for the occurrence of significant ohmic voltage drops, which, in turn, can disrupt the calculated mode of operation of the synchronization circuits. Therefore, synchronization circuits must be carefully calculated to detect excessive voltage drops that lead to failures in the circuit.
Electromigration itself is a physical effect at the atomic level. At high temperatures and current densities, which is typical for VLSI projects with submicron topological norms, due to collisions of drifting electrons with atoms of aluminum or copper wiring, metal atoms are transferred along the buses at the microlevel, which, accordingly, often leads to rupture or failure. -admissible from the point of view of critical current density to thinning of tires. The effect of electromigration appears primarily in the power distribution rails and signal lines. Therefore, the choice of thickness and width of metallic conductors must always be controlled based on peak current density values that do not lead to electromigration [20].
Another physical effect that manifests itself in the manufacture of submicron VLSIs is the so-called antenna effect, i.e., plasma-induced breakdown of the gate dielectric. At the same time, high-frequency plasma is a technological environment traditional for modern microelectronics, in which a large number of production operations with silicon wafers are performed: etching of layers, deposition of dielectrics, surface planarization. During operations with high-frequency plasma, metal or polysilicon conductors "work" like antennas and induce (accumulate) a charge, which, in turn, can lead to breakdown of a thin dielectric. Therefore, modern verification technologies should provide for calculations to eliminate the influence of the antenna effect.

Conclusion
The use of a "deep" submicron with a design norm of less than 0.25 microns leads to fundamentally new effects that must be taken into account when designing and verifying SoCs. Recently, two new technologies have appeared: phase shift patterns and optical proximity correction. The first of them allows you to work with light sources for lithography with an extremely short (deep ultraviolet) wavelength. The second -allows you to correct in the right direction the diffraction effects that occur when using ultraviolet light sources. Phase shift patterns use optical phase shifters to create an interference pattern that ultimately compensates for optical distortion. Optical proximity correction technology involves changing the pattern of photomasks in order to "inversely" compensate for distortions that arise due to optical effects, diffusion of materials, and chemical effects of photoresist and etchant. This leads, in particular, to the fact that right angles are replaced by more complex smooth figures. The technology provides for the production of test structures for certification of corrected templates. Based on the results of the study of such test structures, the optical proximity models are refined and used to appropriately correct the geometry of "traditional" photomasks. When verifying projects prepared using both types of technology, it must be taken into account that the final pattern of photomasks is no longer an exact copy of their imprints on real silicon.