A universal automatic and self-powered gate driver power supply for normally-ON SiC JFETs

Normally-ON silicon carbide junction-ﬁeld-effect transistors have a simple design and exhibit advantageous performance in terms of losses, elevated junction temperatures and high switching frequencies. However, under a loss of power to their gate, normally-ON junction-ﬁeld-effect transistors are subject to a shoot-through situation, which might be severe for their survivability. This paper presents a universal concept for an automatic and self-powered gate driver power supply circuit for normally-ON silicon carbide junction-ﬁeld-effect transistors employed in high input-impedance circuits. The power to the gate is supplied during start-up and steady-state operations through a mutually coupled inductor with the high input impedance inductor and by employing a typical low-voltage, power supply circuit. The performance of the proposed automatic and self-powered gate driver was evaluated on a DC/DC boost converter rated at 6 kW, as well as in a low-voltage solid-state DC circuit breaker. From experiments it is shown that using the proposed circuit, the start-up process requires approximately 350 𝜇 s, while the steady-state switching process of the junction-ﬁeld-effect transistor during steady-state is also shown. Using the proposed circuit in a low-voltage solid-state DC breaker, a fault current of 68 A is cleared within 155 𝜇 s.


INTRODUCTION
Silicon Carbide SiC power switching devices exhibit lower power losses, enable utilisation of high switching frequencies and can operate at higher temperatures (> 200 • C) compared to state-of-the-art silicon (Si) counterparts [1][2][3][4][5][6][7][8][9][10][11][12][13]. Today, SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) [14][15][16] and the SiC junction-field-effect transistors (JFETs) [17][18][19][20][21] are available with voltage ratings in the range of 650-1700 V. SiC JFETs can be designed as either normally-OFF or normally-ON switches. From a converter performance point-of-view, the normally-ON SiC JFET exhibits a lower specific on-state resistance that results in lower conduction losses and a significantly higher saturation current [10,22]. Moreover, normally-ON JFETs have a lower temperature coefficient compared to normally-OFF counterparts. From the driving perspective, normally-OFF SiC JFETs require a significant gate current for if on-state losses need to be optimised. On the other hand, normally-ON JFET has a voltage-controlled gate.
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. Applications such as current-source and impedance-source inverters [23][24][25], high-power modular multilevel converters [26] and DC circuit breakers can benefit from using normally-ON SiC JFETs [27]. However, the normally-ON characteristics of SiC JFETs impose severe driving challenges when employed in power converters. In particular, the greatest challenge of driving normally-ON SiC JFETs is associated with ensuring a safe turn-OFF of the device not only during switching at steady-state operation, but also at the start-up process [28]. Thus, a sufficiently negative voltage (more negative than the pinch-off voltage, V pi ) must always be present and supplied to the gate driver. Various circuit concepts to deal with the "Normally-ON problem" have been developed and applied either at gate-driver [29][30][31] or converter level [32][33][34]. However, these concepts require an external power supply for energising the various circuit components. The need for external power supplies has been eliminated in the self-powered gate driver for normally-ON SiC JFETs shown in [28]. This circuit concept is able to energise the gate-drive circuit without the need of an external power supply, both at start-up phase of the converter and at steady-state operation. Nevertheless, this concept can only be activated in low-input impedance circuits. This is due to the fact that the self-powered gate driver utilises the energy from the shoot-through current during the start-up phase. If the input impedance is high, the anticipated energy of the shoot-through current might not be sufficient to properly activate the circuit. For steady-state operation, the required power to the gate driver is supplied by the blocking voltage of the JFET via a low-power DC/DC forward converter. A similar circuit concept for normally-ON SiC JFETs has been proposed in [35], but it also needs an external power supply for steady-state operation.
Normally-ON SiC JFET can also be perfect device candidates for solid-state DC breakers compared to other SiC active devices. One main reason for this is their lower expected temperature rise compared to SiC MOSFETs under a short-circuit condition [36]. In addition to this, the normally-ON nature of JFETs eliminates the need for continuously supplying a positive gate voltage (i.e. as in MOSFETs) or a substantially high base current (i.e. as in SiC bipolar junction transistors (BJTs)) during current conduction [13]. In particular, normally-ON SiC JFETs can conduct the load current without biasing the gate-source junction, unless further reduction of conduction losses is targeted by applying a low positive voltage. The absence of gate-oxide layer in normally-ON SiC JFET also induces advantages compared to SiC MOSFETs under repetitive short-circuits when operating in solid-state DC breakers [37].
Under a fault condition, the voltage drop across the normally-ON SiC JFET can be utilised and converted to a sufficiently negative gate voltage in order to turn-OFF the device [27]. However, this type of self-triggered JFET-based solid-state DC breaker requires a complicated circuitry and a sufficiently high voltage drop for proper activation, which might cause excessive heat dissipation in the JFET die. Similar circuit concepts have also been presented for bipolar-injection field effect-transistors (BIFETs) [38], which also exhibit similar disadvantages. This paper presents a generic circuit concept of a universal automatic and self-powered (UASP) gate driver supply for normally-ON SiC JFETs employed in high-input-impedance circuits. The proposed circuit concept utilises the voltage drop across the high input-impedance and supply a sufficiently negative voltage to control the gate. By using the proposed solution, the need for connecting additional circuit components across the SiC JFET is eliminated. The performance and applicability of the proposed automatic supply concept is demonstrated in a switch-mode power converter during start-up and steady-state operations, as well as in a low-voltage solid-state DC breaker employing normally-ON SiC JFETs.
The paper is organised as follows. Section 2 shows the operating principle of the proposed circuit, while the design process and dimensioning of the circuit is presented in Section 3. The experimental investigation of the UASP circuit operated in a DC/DC boost converter is found in Section 4. Section 5 presents both simulations and experimental results of the UASP circuit employed in a low-voltage solid-state DC breaker. Last but not least, conclusions are given in Section 6.

OPERATING PRINCIPLE
The operating principle of the proposed circuit is based on utilising the voltage drop across the high input-impedance and convert it to a sufficiently negative voltage suitable to control the gate. Figure 1 shows a block diagram of the proposed UASP circuit concept operating in a switch-mode converter, where the high input-impedance, L 1 is also depicted. In addition to this, the proposed circuit can also be employed to control the gate voltage in solid-state DC breakers utilising normally-ON SiC JFETs, as shown in Figure 2. For the latter case, the high impedance is basically the current-limiting inductor that is needed to limit the rate of rise of fault current, as well as the peak value of the fault current. In both applications, a second inductor, L 2 , is magnetically coupled with L 1 using a magnetic core and by employing a proper circuitry in the UASP circuit (e.g. a positive and a negative voltage regulators) the desired floated voltages can be generated and supplied to the gate.

UASP in switch-mode converters
In order to present the operating principle of the proposed UASP gate driver in a switch-mode converter, a non-isolated DC/DC boost converter is considered (Figure 3). L 1 operates as the main inductor of the DC/DC converter and L 2 is the auxiliary inductor, which is directly connected with a low-voltage diode rectifier, D b . The direct output voltage of D b , u C DC , is fed to a pair of Zener diodes, D Z p and D Z n that supply the positive and negative voltage to the gate. Any potential high current through the Zener diodes is limited by a series-connected resistor, R leak . This is basically one possible way to realise a power supply for the gate driver. A plethora of various low-voltage source concepts might also be employed in order to convert the voltage across L 2 to suitable voltage levels for the gate driver.
To complete the gate driver design, an optocoupler for signal isolation and a totem-pole integrated-circuit driver (IC-driver) are also employed. Last but not least, for controlling the switching speed of the JFET and preventing breakdown of the gate, a series-connected gate resistor R g and a diode-resistor-capacitor (D g R p C g ) parallel network are connected on the output of the IC-driver [39]. A favourable characteristic of the proposed UASP circuit is the fact that the shoot-through current is only limited by means of L 1 , and thus, the need for a start-up resistor to limit the shoot-through current is eliminated. However, the inductance of L 1 must be properly chosen in order to set the peak value of the shoot-through current in such a way that it will not stress thermally the SiC JFET and that will not saturate the channel of the JFET either. Along with this, the range of the input voltages of the DC/DC boost converter must also be carefully set for ensuring a successful start-up procedure. Additionally, in steady-state operation of the converter, the design of the inductance L 1 must take into account the switching frequency of the SiC-JFET, as well as the input voltage and the load current. Then, the inductance L 2 will be defined accordingly, as mentioned above. It should be noted that a high switching frequency is anticipated due to the utilisation of SiC power semiconductor device and thus, L 1 and L 2 can be low resulting in a high power density DC/DC converter design. However, at elevated frequencies, the power losses associated with the mutually coupled inductors and more importantly the core losses, will also increase. In addition to this, operation at elevated switching frequencies imposes the need for more powerful gate drivers that will be able to supply sufficient gate current peaks for fast switching and to also ensure a stable gate voltage supply. When the start-up process is initiated, it is assumed that the input capacitor C in is fully charged at the input voltage V in . Moreover, it must be noted that the DC/DC converter is energised when the circuit breaker, CB, shown in Figure 4 closes, and thus, C in feeds the circuit.
As soon as the CB is closed and since there is no power to the gate, J m is subjected to a short-circuit condition and the input voltage, V in appears across L 1 and J m . The derivative of the shoot-through current is determined by the values of L 1 and V in . A graphical representation of the current, i J m flowing through J m and current i L 1 through L 1 are shown in the first and second waveforms in Figure 5. From this figure, it is clear that two current peaks are observed on both of i J m and i L 1 waveforms. The different time intervals which can be observed in Figure 5 are analySed as follows.
• t 0 -t 1 : The first current peak in the interval t 0 -t 1 is due to the charging current of the DC-link capacitor of the auxiliary circuit, C DC ( Figure 3). During this time interval, the voltage across L 1 , u L 1 , is rising and has a maximum value of approximately V in . In particular, the main part of V in appears across L 1 , while the voltage across J m is significantly lower due to its low ON-state resistance (fourth waveform in Figure 5). For simplicity, however, it is assumed that V in completely appears across L 1 . • t 1 -t 2 : When u C DC reaches its steady-state value at t = t 1 , the current in the auxiliary winding, L 2 becomes zero. However, a low leakage current i L 2 still flows through L 2 in order to compensate for the losses in the circuit (e.g. leakage current in C DC and Zener diodes). The performance of u C DC is shown in the bottom waveform in Figure 5. • t 2 -t 3 : At the time instant t 2 , the negative supply voltage of the optocoupler and IC-driver, u gs , is sufficiently low and provided that the propagation of the pulse width FIGURE 5 Theoretical performance of the UASP circuit employed in the DC/DC boost converter modulation (PWM) signal to the optocoupler starts at t = t 0 , J m is switching. However, J m is operating in the active region until u gs becomes more negative that the pinch-off voltage of J m , V pi . During this operating phase the drain-source voltage, u ds , is switching between a high and a low positive voltage level and the SiC JFET might be overheated, unless a proper dimensioning of the UASP and converter is made. As soon as u gs exceeds V pi at t = t 3 , the SiC JFET is switching normally in the saturation region. Additionally, the voltage across the primary winding of the coupled inductors, u L 1 becomes negative and i L 1 starts decreasing. This is due to the fact that J m is turned-OFF (operation in active region) and a high blocking voltage appears across the device. Furthermore, the output voltage of the DC/DC boost converter, V out , equals the envelope of the switching waveform of u ds . Thus, con- Block diagram of the UASP employed in a solid-state DC circuit breaker with a normally-ON SiC JFET tive voltage appears across L 1 . After t 2 , u L 1 starts to switch between a high negative and a low negative voltage level until u gs < V pi . • t > t 3 : At t = t 3 , u gs becomes lower than V pi and hence, the steady-state operation of the converter is reached.
If the turns-ratio between L 1 and L 2 is N 1 :N 2 , the value of u L 2 equals (N 2 ∕N 1 ) ⋅ u L 1 . This voltage is supplied to the singlephase diode rectifier of the auxiliary circuit and dictates the value of u C DC . During steady-state operation of the DC/DC boost converter, the square-wave voltage of L 1 is continuously transformed to u L 2 and energises the UASP.

UASP in low-voltage solid-state DC breakers
For presenting the operating principle of the UASP when it is employed in a solid-state DC circuit breaker with normally-ON SiC JFETs, the block diagram shown in Figure 6 will be considered. A vital component of a circuit breaker is the seriesconnected current-limiting inductor, L 1 that limits the rate of rise, as well as the peak value of the fault current. In addition to this, a metal-oxide varistor (MOV) is connected in parallel to the JFET for preventing destructive overvoltage conditions and breakdown. In order to ensure galvanic isolation in the fault line, a residual mechanical switch is also connected in series, which is able to open when the fault current is cleared by the SiC JFET.
Prior to the activation of the UASP, it is assumed that the solid-state circuit breaker conducts the direct line current, i L 1 = I nom , which flows through L 1 and the normally-ON SiC JFET and it is supplied to the load. When a fault occurs ( Figure 6), the line current increases rapidly because the voltage across L 1 equals the direct voltage of the grid, V DC . Similarly to the case of applying the UASP in a switch-mode converter, the voltage across L 1 can be utilised by magnetically-coupling a second inductor L 2 . This inductor L 2 feeds power to the UASP and, thus, the low-voltage and low-power circuit components contained in the UASP can be activated. However, in case of a solid-state breaker, there is no need for switching operation and it is only sufficient to supply a negative gate-source FIGURE 7 Theoretical performance of the UASP circuit employed in a solid-state DC breaker with a normally-ON SiC JFET voltage for turning-OFF the SiC JFET. It should also be mentioned that a damping resistor, R d connected in series with the second winding of the coupled inductors must be considered in order to dump potential voltage oscillations between L 2 and C DC due to resonance.
The expected theoretical performance of the UASP when employed in a JFET-based solid-state breaker is illustrated in Figure 7. The operation of the UASP in different stages during a short-circuit clearance can be seen in that figure and it is analysed as follows.
• t 0 -t 1 : Prior to the time instant that the fault occurs (t < t 1 ), a direct line current flows, the voltage across L 1 is zero (i.e. the resistance of L 1 is assumed to be negligible) and the UASP is inactive.
• t 1 -t 2 : The fault occurs at t = t 1 , and thus the line current starts rising with a slope determined by the values of V DC and L 1 as shown in the first plot in Figure 7. Beyond t 1 , the entire grid voltage V DC appears across L 1 (i.e. u L 1 = V L 1+ = V DC ) and a voltage, u L 2 , is also induced across L 2 with a magnitude that is determined by the turns ratio N 1 ∶ N 2 . In particular, Considering the same implementation of the power supply shown in Figure 3, the induced voltage on L 2 is rectified and appears across C DC . As soon as, u C DC exceeds the sum of the breakdown voltages of the two Zener diodes, the negative and positive voltage supplies to the gate are regulated. However, by utilising the UASP in a JFET employed in a solid-state breaker, the need for a positive gate voltage supply could be omitted, unless conduction power losses are to be further reduced. On the other hand, if the optimisation of the conduction losses is of high design priority, an external positive voltage supply can be used. • t 2 -t 3 : At t = t 2 and after the voltage across the C DC has been stabilised at V C DC , the u gs becomes equal to the pinch-off voltage, V pi , and therefore, the voltage across the JFET, u ds starts rising as illustrated in the bottom waveform with red line in Figure 7. The solid-state breaker employing a normally-ON SiC JFET can be designed to be either self-controlled or externallytriggered. Self-controlled design means that the overall UASP design and dimensioning of the components are such, that when the fault current exceeds a predefined current threshold, the gate-source voltage becomes less negative than V pi , and thus, the JFET turns-OFF. In the externally-triggered design, a positive gate voltage can be supplied by an external voltage source, while the negative gate voltage can be generated by the UASP. However, in this case, an external signal to the optocoupler is needed for controlling the turn-OFF of the JFET. This is crucial when such a solid-state DC breaker operates in a multi-terminal grid, where selective protection might be required.

High-input-impedance converter case
During the start-up process in the high-input-impedance converter, the design of UASP must be such that will not cause an extensive discharge of C in . This means that along with the proper selection of L 1 , C in must also be selected with respect to the allowed input voltage drop during the activation of the UASP. If V in drops to very low values or zero (fully discharging of C in ), the voltage across L 2 will also be either low or zero, and the UASP might not be activated. A generic schematic diagram showing the path of the shootthrough current in a converter is shown in Figure 8. In this figure, L tot is the total inductance seen from the shoot-through current (i.e. combination of the mutually coupled inductors L 1 and L 2 ). It is also assumed that the normally-ON SiC JFET J m has an on-state resistance r on . Based on Figure 8, Equation (1) gives the shoot-through current, i st , as a function of the time t during the start-up phase.
By solving this equation, the analytical expression for i st can be derived. Thus, the energy released from C in and dissipated in J m can also be calculated using Equation (2). In this equation, I st is the peak value of the shoot-through current and t su is the time needed for J m to start its switching process in a converter. Equation (3) gives the energy, ΔE in , released from the capacitor during the start-up phase. In this equation, V in and V ′ in are the voltages across C in before the start-up process is initialised and when J m is turned-OFF, respectively.
In case of dissipation of the entire energy stored in C in , the voltage V ′ in will drop to zero, which prevents the proper activation of the UASP. It is, therefore, necessary to set a criterion for the maximum allowed energy ΔE in,allowed that can be released from C in , as shown in Equation (4). This criterion dictates that ΔE in,allowed must be significantly higher than the expected energy dissipation in the normally-ON SiC JFET. Thus, the anticipated voltage drop in C in will also be kept low, which results in proper activation of the UASP.
The criterion shown in Equation (4) can also be expressed in terms of the peak shoot-through current, I st , as shown in Equation (5).
In the calculation of I st the required turn-OFF time, t su , must also be taken into account. However, the various combinations of I st and t su are, to some extent, directly associated with the value of L tot . On the other hand, t su is also related with the activation time of the auxiliary gate driver power supply. In particular, a specific time is also necessary in order the gate driver to supply an adequately negative gate voltage which turns-OFF J m . This time is associated with the activation of the voltage regulators for V p and V n , optocoupler and IC-driver.
If the input voltage V in drops more than the value set by the design limits, the voltage across the Zener diodes will not be adequately high to reverse-bias them. Consequently, the design of the coupled inductors L 1 and L 2 must also be done with respect to the range of the input voltage.
The voltage at which the C DC , will be stabilised, V C DC , must be at least higher than the sum of the reverse breakdown voltages of the Zener diodes, for operating as voltage regulators. During the startup phase, V C DC depends on the input voltage V in and the turns-ratio of the coupled inductors, N 2 ∕N 1 . On the other hand, in case the UASP is employed in a boost converter operating in CCM, during steady-state operation, the voltage V C DC depends on the input voltage, V in , output voltage, V out , and the duty ratio of the converter, D: The voltage given by Equation (6) must fulfil the following criterion: where V n and V p are the absolute values of the negative and positive voltage supplied by the Zener regulators and V R leak the voltage drop across R leak .

Solid-state DC circuit breaker case
The design of the UASP in the fault-clearing process in a SiC-JFET-based breaker faces different challenges. In particular, the grid voltages are usually higher than the input voltage of a DC/DC boost converter and hence, the discharge of C in is not likely to occur under high input voltages V DC . Therefore, the design of the proposed circuit will not take into consideration the input capacitance of the DC grid. On the other hand, the high grid voltage leads to the use of a different turns-ratio of the coupled inductors compared to the design of the UASP for the case of a switch-mode converter. The voltage in the UASP circuitry and particularly in C DC should be kept at much lower levels than the grid voltage leading to the need for more turns in the primary inductor compared to the secondary side. In addition to that, the importance of the rate of rise of short-circuit current, di L 1 ∕dt should be emphasised since this may lead to high peak currents, which might heat up the JFET die excessively. The fault current rise in the circuit shown in Figure 6, is governed not only by the L 1 , but also by the mutual inductance between L 1 and L 2 , and it is given by the following equation.
where M is the mutual inductance given by: In this expression, c is the coupling coefficient of the coupled inductors. Additionally, as mentioned above, a damping resistor, R d must be considered. The possible oscillations between L 2 and C DC should be damped and thus, the following criterion must be set.
Finally yet importantly, the charging time of the C DC , t ch , given by approximately 5 ⋅ R d C DC , should be set in such a way, that the peak short-circuit current will be within an acceptable limit. The t ch indicates the start of the JFET turn-OFF and hence the peak short-circuit current. Therefore, the following criterion must be set.
where, I nom and I SC max are the nominal line current and the maximum allowable fault current respectively. It should also be mentioned that the capacitor voltage when the last is fully charged, V C DC will be lower than N 2∕N 1 ⋅ V DC , due to the voltage drop in the damping resistor R d . At the same time, Equation (7)

FIGURE 9
Photograph of the experimental DC/DC boost converter prototype employing the automatic start-up circuit must hold true. Therefore, the choice of C DC , R d and L 2 which will set the N 1∕N 2 are of great importance and they must be defined precisely.

EXPERIMENTAL RESULTS FOR OPERATION IN A SWITCH-MODE POWER CONVERTER
The performance of the proposed UASP power supply for normally-ON SiC JFET operating in switch-mode converters has been validated experimentally using a DC/DC boost converter rated at 6 kW. The lab prototype was designed using a 1200-V SiC JFET with an ON-state resistance of 45 mΩ at room temperature, a pinch-off voltage of −5 V and a chip area of approximately 9 mm 2 . A photograph of the experimental DC/DC boost converter prototype is shown in Figure 9.
In order to emulate the start-up process of the circuit, a circuit activation switch employing a silicon IGBT (IXYS IXA55I1200HJ) was connected between the pre-charged C in and L 1 . However, in a realistic converter, the start-up switch might consist of a relay or a mechanical switch. In this paper, however, the main target is to demonstrate the operating principle of the proposed universal automatic and self-powered circuit, and thus, the investigations are not expanded to the design and performance of the circuit activation switch.
The design of the coupled inductors, L 1 and L 2 , is very crucial for the proper operation of the uasp circuit. Assuming the range of the input voltage to be 50-150 V, the steady-state peakpeak ripple on the inductor current to be kept lower than 8 A, and continuous conduction mode (CCM) for the converter, L 1 was calculated to be 125 H.
Moreover, given that the voltages supplied by the Zener regulators equal V n = −30 V and V p = 2.5 V and by taking into account a minimum input voltage of V in,min = 50 V, the turns-ratio must be equal to N 1 ∕N 2 = 1:1. Thus, even if the lowest boundary of the input voltage (V in,min = 50 V) is fed to the converter, the Zener voltage regulators will be activated properly. Table 1 shows the design parameters of the coupled inductors, which prevent magnetic saturation of L 1 . The parameters of the experimental setup are summarised in   This set of experiments has been performed by setting the input voltage to V in =50 V. The complete start-up process of the DC/DC boost converter is shown in Figure 10. In this figure, the measured gate-source and drain-source voltages, as well as the drain current of J m and the current flowing through L 1 are illustrated. As expected, when the start-up process is initialised, the shoot-through current (either I L 1 or I J m ) starts rising. The first current peak, due to the charging of C DC , appears approximately 100 s after the initialisation of the start-up process. After this, the shoot-through current continues rising until the auxiliary gate driver supply is activated. The term "activation" Measured gate-source voltage of J m (yellow line, 10 V/div), voltage across L 1 (purple colour, 50 V/div), drain current I J m (green line, 100 A/div), and inductor current I L 1 (red colour, 100 A/div), (time base 200 s/div) during the start-up process of the converter refers to the time point where the IC-driver is able to supply an adequately negative output voltage V g , which is able to turn-OFF the JFET. Considering that the PWM signal starts simultaneously with the activation of the converter, the switching process of J m also starts as soon as the IC-driver is activated. This can be seen in Figure 10 approximately 350 s after the initialisation of the start-up process. It must be noted that, in order to prevent large overvoltages on the output of the converter, the duty-ratio is slowly increasing from zero up to the steady-state value. Moreover, from Figure 10 it is clear that J m is switching in the active region, because V gs is lower than zero and less negative that the pinch-off voltage of the device (V pi =-5 V). The switching operation in the active region can also be seen from the simultaneous stress of J m with high values of blocking voltage (purple line in Figure 10) and current I J m (green line in Figure 10).
The voltage across the inductor L 1 is shown with the purple line in Figure 11. When the start-up process starts, this voltage is positive and causes a rising current that flows through  Figure 11, respectively). When the PWM switching process starts, the voltage across L 1 becomes negative and I L 1 starts to decrease. This is due to the fact that when the switching operation starts, J m conducts a high current and the device operates in the active region. Moreover, during the start-up process and before the switching process starts, the output voltage of the DC/DC boost converter, V out , equals zero. As soon as V ds starts rising, the output voltage of the DC/DC boost converter, V out , also starts increasing and equals the envelope of the switching waveform of V ds . Thus, V L 1 = V in −V out , which is a negative voltage and I L 1 is decreasing.
The steady-state operation of the DC/DC boost converter is reached a few milliseconds after the time instant that the start-up process is initialised. This time interval depends on the values of the passive components of the power converter and the design of the UASP. A caption shown the normal switching operation of J m at steady-state is presented in Figure 12. From this figure, it is obvious that the converter is operating in CCM at a switching frequency of 50 kHz and a duty ratio slightly higher than 0.5.

Simulation results
The application and performance of the proposed UASP in a solid-state DC breaker employing a normally-ON SiC JFET has been investigated using simulations. For this purpose a lowvoltage DC breaker consisting of a 1200-V SiC JFET that is connected in a DC line has been modeled using LTspice. The SiC JFET is rated at 63 A and has an on-state resistance of 35 mΩ at room temperature. Since the focus of these investigations is to validate the operation of the UASP at device level, a Spice   Table 3 summarises the design and modelling parameters for the breaker and the DC line. It is assumed that during normal operation of the solid-state DC CB, the SiC JFET conducts a line current of 35 A as shown in Figure 13 prior to t =100 s. At this time instant t =100 s a pole-pole fault occurs and, thus, the line current starts rising due to the positive voltage of V DC across L 1 . The induced voltage across L 2 is rectified and the gate-source voltage, u gs starts to develop as shown in Figure 13  fault occurrence, is clamped at the breakdown voltage of the MOV, which has been set to 900 V as shown in Figure 13(b). As long as the residual energy from the line is dissipated in the MOV, the SiC JFET is blocking 900 V, whereas when the energy dissipation is complete, u ds drops to the nominal grid voltage of V DC .
The performance of the various currents during a fault clearing process is illustrated in Figure 14. From this plot, it is obvious that the line current, i L 1 is equal to the sum of the JFET current, i d and the MOV current, i MOV . When the SiC JFET is turned-OFF, the fault current commutates to the MOV, which dissipates the residual magnetic energy of the DC grid. The residual energy dissipation lasts for approximately 135 s. In addition to that, the peak short-circuit current reaches approximately 68 A, which is within the limit set.
A further observation relates to the choice of C DC and its impact on the peak fault current. Figures 15 and 16 show the voltage across the C DC , the gate-source voltage and the anticipated line current for various values of C DC . Two issues must be highlighted regarding these figures. Firstly, the C DC is charged at higher voltage level by decreasing the capacitance as illustrated in Figure 15(a). This holds true due to the shorter charging time, t ch at lower capacitances along with the voltage drop across the damping resistor, R d . Secondly, the peak short-circuit current increases by increasing C DC as shown in Figure 16, because as the value of this capacitor becomes higher, a longer time interval is required for the u gs to reach V pi and turn-OFF J m , as illustrated in Figure 15(b). High currents through the SiC JFET might result in extensive thermal stress and eventually thermal destruction of the device, unless its chip area is sufficiently large to withstand such high surge currents. On the contrary, a very low value of C DC will trip the CB at very low values of fault current. This might cause breaker tripping under load variations, which is undesired in practical applications.
Furthermore, the importance of the design of the secondary inductor, L 2 can be seen in Figures 17 and 18. In particular, Figure 17 shows the voltage across the C DC , u C DC for three values of L 2 . Higher inductance of the secondary inductor leads to smaller turn-ratio and thus the voltage u C DC becomes higher. Therefore, the gate-source voltage reaches sooner the pinch-off voltage, V pi and as a result, the short-circuit current is interrupted at lower peak value, I SC max as depicted in Figure 18. However, significantly high inductance might cause high current in UASP circuitry, as well as, breaker tripping under load variations, similar to the C DC case.
All in all, the choice of both C DC and L 2 , as well the overall design of the UASP must be made based on the design and operating constraints of the specific application. More specifically, if the protected DC line feeds power to very critical and sensitive loads or supplied by sensitive power sources, it is inevitable to tune the breaker and UASP such that the fault is cleared as fast as possible. On the other hand, for not very critical source and loads and especially for those exhibiting variations during normal operation, the tuning of UASP could be more flexible.

Experimental results
The performance of the UASP circuit in a solid-state breaker has also been assessed experimentally using the test circuit illustrated in Figure 19. Similar to the simulations presented in Section 5.1, a 1200-V, 63A normally-ON SiC JFET with an ONstate resistance of 35 mΩ at room temperature from UnitedSiC (UJ3N120035K3S) has been used as the main breaker switch. Besides that, a 3.6 kV and 50A IGBT (IXYS IXBX50N360HV) has been considered as an auxiliary switch S 1 , which is used to initiate the fault condition. In particular, when S 1 turns-on, a fault line current is flowing through the solid-state breaker. A single pulse test was performed as Figure 19 shows. A photograph of the DC breaker prototype along with the UASP circuit is depicted in Figure 20. Tables 4 and 5 summarise the design parameters for the coupled inductors and the test circuit, respectively. On the other hand, Figure 22 shows similar results but in case of C DC = 1 F. The increase of the capacitance prolongs the turn-off process of the normally-ON SiC JFET and hence, the line current increases accordingly. As a result, the peak current in that case reaches 33 A and the fault is cleared within 330 s. The capacitor, C DC , is charged in 20 s reaching a steady-state value of 27.5 V. The last case with C DC = 1 F corresponds well   with the simulation results shown in Figure 14, where the fault current starts at 35 A and reaches a peak value of 68 A.

CONCLUSION
A universal automatic and self-powered circuit for normally-ON SiC JFET employed in high-input impedance circuits was proposed. The main concept of the proposed circuit is to supply an adequately negative gate voltage using the voltage across the high-impedance component and an auxiliary coupled winding during both the start-up process and steady-state operation. Apart from its applicability to switch-mode converters, the proposed UASP concept can also be utilised in a low-voltage solidstate circuit breaker. It has experimentally been shown that applying the UASP in a switch-mode converter, the normally-ON SiC JFET starts switching approximately 350 s after the start-up process is initialised. However, this time depends on the design of the gate driver supply circuit and the converter. In addition, the steadystate operation of the converter using the UASP circuit is also experimentally shown. Based on these experimental results, a normal switching operation of the normally-ON SiC JFET at 50 kHz during steady-state is observed.
The performance of the proposed UASP concept has also been validated in a low-voltage solid-state DC breaker employing a normally-ON SiC JFET by means of both simulations and experiments. From simulations, it has been shown that the SiC JFET clears a fault current of 68 A within approximately 155 s, while in experiments, the solid-state breaker interrupts a 33 A short-circuit current in 330 s. However, a proper and application-oriented tuning procedure is necessary in order to set the tripping current level for the UASP, as well as the expected peak fault currents and thermal stress of the SiC JFET.
It is clear that the design complexity of the proposed UASP gate driver is higher compared to a conventional voltage-source gate driver with external power supply. However, normally-ON SiC JFETs exhibit a better power loss performance in power converters compared to the normally-OFF counterparts. Not only the lower specific on-state resistance and the lower temperature coefficient, but also the voltage-controlled gate-source junction contribute to lower losses.