An interleaved ZVS ultra-large gain converter for sustainable energy systems applications

This paper proposes an interleaved zero-voltage switching (ZVS) ultra-large gain converter. By implementing coupled-inductor (CI) and built-in transformer (BIT) together with a switched capacitor (SC) voltage multiplier cell (VMC), a higher degree of ﬂexibility is achieved for improvement of step-up voltage gain in comparison with those in which only one of these magnetic devices is utilised. Furthermore, the imposed voltage across the semiconductors is reduced by adjusting the turns ratio of the implemented CI and BIT. To further improve the efﬁciency, semiconductor devices with low ON-state resistance can be used. Moreover, to ensure ZVS turn-on, active clamp circuits are located in parallel with the main MOSFETs, which realize ZVS for all MOSFETs during an entire switching cycle. Minimizing the input current ripple as well as attenuating the reverse recovery problem of the diodes are the other advantages of this converter. Therefore, the proposed converter is a suitable candidate for those applications requiring high step-up gain and high conversion efﬁciency, such as renewable energy systems. To validate the performance of the proposed converter, a 600 W prototype with 22–380 V voltage conversion is designed, fabricated, and tested. Experimental results conﬁrm that the proposed converter outperforms the previously presented ones in terms of the voltage gain and efﬁciency.


INTRODUCTION
Renewable energy sources such as photovoltaic (PV) and fuel cell (FC) stack systems have become the most popular types of electricity generation worldwide. However, the output voltage of PV panels and FC stacks is relatively less than the amount required to power local loads and electrical utility. Typically, when a large duty ratio is applied to obtain the high output voltage for DC-DC boost converters, yields such problems as supremely narrow turn-off interval, high peak current, in addition to considerable conduction and switching losses [1]. Switched capacitor (SC) and switched inductor (SI) voltage multiplier cells (VMCs) are well known circuit to extend voltage gain [2][3][4][5][6]. The proposed converter in [4] successfully integrates the SC cells in to a voltage lift circuit to improve voltage gain. However, in the generalized structures, the voltage and current rating of the utilized components in each cell differs with the other cells which makes the design relatively complex. This This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology issue has been discussed and solved in [5] by utilizing of Cock-Croft Walton VMCs. To achieve high voltage gains, the number of VMCs should be increased which increases cost, complexity and current spikes as well. A fourth-order simple common source-load ground structures to increase the operability and power density, low components stress and no sudden changings on capacitors voltage to prevent the instantaneous overcurrent phenomenon has been proposed in [7]. In this case the introduced buck-boost converter achieves high step-up conversion ratio in boost mode. However, due to cascaded power processing stages and utilizing of two power switches, the conversion efficiency is deteriorated. Quadratic converters [8,9] converters can achieve higher voltage gains at lower duty cycles whereas the input current ripple is low. Although, the voltage step-up ratio is enhanced in these converters; however, the common sourceload ground is lost in [8] and due to utilization of the diodes at high current side, the conduction losses is increased. A singleswitch high step-up Zeta converter has been introduced in [10] based on the combination of basic Zeta converter and corresponding coat circuit. By implementing of the coat circuit, not only higher voltage gain is achieved, but also the voltage stress across the semiconductors is decreased. However, the main disadvantages of the zeta based step-up converters is the pulsating input current arising from the series connection of the power switch with the input power source. The Z-source converter utilizes a network of diode-capacitor-inductor between the input power source and the main switch [11,12]. The voltage gain is improved at the expense of limiting the duty cycle. Moreover, in the Z-source converter just like the quadratic ones, the conversion efficiency is deteriorated by implementing of the diodes at high current side.
Although, the transformer-less converters of [2][3][4][5][6][7][8][9][10][11][12] are low cost and easy to implement; however, the only freedom to extend the voltage gain is the duty cycle. Moreover, high transient current and high current spikes are imposed across the active and passive components which leads to considerable conduction losses. Coupled inductors (CIs) are other potential approaches to achieve high step-up voltage gain in the boost converter [13,14] and also in buck-boost converter in step-up mode [15]. The turns ratio is increased to increase voltage gain without a large duty cycle and the voltage stress across MOS-FETs is decreased, as well. In such types of step-up converters passive clamp technique is utilized to recycle the energy of the leakage inductance of the CI and to suppress the high voltage spikes. Meanwhile, the leakage inductances of the CIs, provide zero current switching (ZCS) turn-on for MOSFETs and control the falling current rate of the diodes and the reverse recovery problem is alleviated. This concept is applied to the quadratic [16] and Z-source [17] converters to extend voltage gain. However, the main disadvantages of these types of converters mentioned earlier still exist. To reach higher step-up voltage gain along with lower transient current, CIs are typically implemented with SCs circuits [18][19][20].
To decrease the current stress of the main switches some researches have proposed multiple switches converters with switched-inductors [21,22] and switched-coupled inductors [23,24]. The switches are turned ON and OFF simultaneously to charge the magnetic devices. Although the current stress of the MOSFETs is decreased in these schemes; however, implementation of two gate drive circuits increases the total cost and the main problems of the single switch converters such as high input current ripple and low conversion efficiency at high output power levels still exists.
The input current ripple of single-phase boost converters is rather large, which reduces the service life of PV panels as well as the input electrolytic capacitor. To share the input current in each phase and minimizing the input current ripple, interleaved boost converters (CIBCs) have been introduced, where low step-up voltage gain remains as their common problem. The interleaved converters not only promise the low input current but also it offers higher conversion efficiency at higher output powers due to thermal losses distribution. There are many interleaved approaches that have been developed SI and SC VMCs to rectify this problem and achieve high step-up voltage gain [25][26][27][28][29]. The introduced converter in [25] utilizes active SI and SC to increase the voltage gain. The MOSFETs are switched ON and OFF, simultaneously. However, the input current is pulsating and the common source-load ground is lost which arises safety problems and passing of PV leakage current through the circuit. The two-phase [26,27] and three-phase [28,29] SC based interleaved converters achieve high voltage gain while maintaining the low input current ripple and common source-load ground.
Three winding CIs along with VMCs are utilized in [30][31][32] to extend the voltage gain. The primary windings of the CIs act as the input filter inductor in CIBC. The secondary is inserted at the same phase as well as the primary winding. To enhance the voltage gain and current sharing performance, the third winding is inserted at the other phase. To handle higher amount of power with maintaining the efficiency at high levels, a modular CI assisted converter has been proposed in [33]. However, the input current is not shared equally between the phases of an individual module. To further extend the voltage gain, the secondary windings of the CIs are inserted in series to each other in a voltage doubler which its output is connected directly to the output stacked capacitors [34]. Two sets of VMCs are implemented in [35] to obtain high voltage gain in which one of them is mixed with the secondary windings of the CIs. Unfortunately, the input current is not shared between the two phases equally that is a common disadvantage of the introduced converters in [36]. By implementing of CIs and voltage quadrupler, the converter of [37] achieves high voltage gain at the expense of losing common source-load ground. An interleaved input-parallel and output series converter with high voltage gain is introduced in [38]. However, too many components are needed to extend the voltage gain. The converters of [39,40] share a common CI based VMC between the two interleaved phases and utilizes a voltage lift circuit. In this case high voltage gain is achieved with low number of components and also the input current is shared equally between the phases. The introduced converter in [41] obtains high step-up voltage gain by using two CIs and two VMCs. This topology utilizes the interleaved boost converter in the input side, and the input current is shared with low ripple. On the other hand, a VMC with the secondary windings of the coupled inductors is employed in the output side to achieve the interleaved energy storage. Hybrid series-parallel connection of the VMCs has been introduced in [42,43] to improve voltage gain. However, the common source-load ground is lost in these types of converters.
Built-in transformer (BIT) can be implemented to extend the voltage conversion ratio [44,45]. Due to the zero-average current through the primary winding of the BIT, the RMS current is considerably decreased which enables the designer to utilize cores with lower sizes. Moreover, the core saturation is inherently avoided even with in the small cores.
To further increase the voltage gain, the CI and BIT are simultaneously implemented in the converters of [46][47][48]. In such a case, an extra degree of freedom is obtained for voltage boosting in comparison with those that utilizes one of these magnetic devices. The turns ratio of the CI and BIT together decrease the voltage stress across the MOSFETs, Hence, low voltage rated devices with low cost and low ON-state resistance FIGURE 1 Introduced converter in [48] can be selected that decreases the conduction losses, considerably.
Although the ZCS turn-ON is provided for MOSFETs through the leakage inductances of CI and/or BIT; however, this can not minimize the turn-ON losses. At higher switching frequency in which the size of the components is considerably decreased, the zero voltage switching (ZVS) is a promising solution to reduce the switching losses [49][50][51][52][53][54][55][56][57][58][59][60] that can be achieved by an active clam rather than passive clamp in [30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48]. The active clamp scheme is introduced to satisfy ZVS performance for the main and auxiliary MOSFETs in an interleaved transformerless converter with Dickson VMCs [49]. Here, to provide the required resonance to discharge the parasitic capacitors of the MOSFET, auxiliary inductors are embedded within the SC VMCs. However, additional cores are needed and also too many components should be implemented to increase voltage gain. In the contrary, the leakage inductances of CI or BIT in the converters of [50][51][52][53][54][55][56][57][58][59][60] acts the role of that auxiliary inductors in [49]. Generally, the active clamp consists of a clamp capacitor and an auxiliary MOSFET that is simply connected across the main switch [50-55, 59, 60]. An active clamp cell consisting of a CI, an auxiliary MOSFET, four diodes and one capacitor is introduced to the converter of [30] to achieve soft switching performance for the main switches in whole switching transition [56]. It is clear that the clamp circuit has a complicated structure with too many diodes. A similar concept is also presented in [57]. The clamp circuit is participated in voltage gain extension in a lift circuit scheme connected to the output side of the converter [58]. In such a case, the high voltage gain is obtained as well as low number of the components. Figure 1 shows the introduced converter in [48]. This converter utilizes two sets of CIs and a three windings BIT in which the secondary windings of the CIs are inserted in series with each other with in a voltage doubler cell at the output. The voltage gain is proportional to the sum of the turns ratios of the CI and BIT and the passive clamp scheme is implemented to recycle the leakage energy which loses the ZVS characteristic. In this paper, by inserting the secondary windings of the CIs between the main MOSFETs and the primary winding of the BIT, the voltage gain is proportional to the multiplication of the turns ratios of CI and BIT. It is seen that in the proposed concept, the voltage gain is considerably increased even with a lower winding for BIT. Moreover, ZVS performance is achieved for the MOS-FETs through whole switching transition. Altogether, through the extensive analysis and conducted performance comparison later in the paper, it is proved that the proposed converter has the following advantages: • Ultra-large voltage gain is provided.
• Low voltage stress across the MOSFETs and diodes.
• ZVS performance of the MOSFETs is realized through whole switching transition. • Reverse recovery problems of the diodes are alleviated.
• High efficiency is achieved following to the abovementioned merits.

PROPOSED CONVERTER AND OPERATING PRINCIPLE
The circuit schematic of the proposed high step-up voltage gain converter consisting of two sets of CIs, a BIT and a SC VMC is illustrated in Figure 2. To provide ZVS operation, two sets of active clamps are employed as well. The reflected leakage inductances of the CIs from the secondary to the primary side are symbolized by L Lk1 and L Lk2 . The magnetizing inductances of the CIs are represented by L m1 and L m2 . The overall reflected leakage inductance of the BIT is denoted by L Lkb . S 1 and S 2 are the main MOSFETs; S c1 and S c2 are the active clamp MOSFETs; C c1 and C c2 are the clamp capacitors; C S1 and C S2 are the parallel capacitors; C m1 and C m2 are the multiplier capacitors; C o1 , C o2 , and C o3 are the output capacitors; D r1 and D r2 demonstrate the regenerative diodes; D f1 and D f2 are the output diodes for forward-flyback operation and R out represents the load resistance. The turns ratio of the CIs is given by n = n s1 /n p1 = n s2 /n p2 and turns ratio of the BIT is defined as N = N s /N p .
The main waveforms of proposed converter are plotted in   inductances of the coupled-inductors L m1 and L m2 are directly proportional to the input voltage and are changed by it linearly. The output load is supplied through the capacitors C o1 , C o2 , and C o3 . The current passing through the leakage inductances L Lk1 and L Lk2 is given by: Mode II [t 1 , t 2 ] (Figure 4(b)): At time t 1 , thanks to the parallel capacitor C S1 , the MOSFET S 1 is turned OFF with ZVS and the current of the magnetizing inductance L m1 flows through C s1 . The drain-source voltage of S 1 can be written as: Mode III [t 2 , t 3 ] (Figure 4(c)): At time t 2 , the voltage across the capacitor C s1 reaches the value on the clamp capacitor C c1 and turns the anti-parallel diode of S c1 ON. Since the capacitor C S1 is much smaller than C c1 , the current passing through the magnetizing inductance L m1 flows through C c1 . As a result, the voltage stress across the MOSFET S 1 is successfully clamped to the C c1 voltage: Mode IV [t 3 , t 4 ] (Figure 4(d)): At time t 3 , V DS1 reaches the point that makes D b1 , D r2 and D f1 start conducting. By ignoring the voltage across L Lk1 , L Lk2 , L Lkb , the applied voltage across the primary winding of the BIT is equal to the sum of V Cc1 and the voltage of the secondary side of the CIs. The primary side of BIT charges C m2 via D r2 . The output capacitor voltage V Co1 is equal to the sum of the V cm1 , the primary voltage of BIT (V Np ), and the secondary voltage of the CI (V ns1 ). Finally, the output voltage V out is equal to the sum of the all output capacitors voltages. The stored energy in L m1 and C m1 is transferred to C o1 and R out through D b1 . The voltage of the secondary side of BIT charges C o3 by means of diode D f1 . The current passing through S 2 in this time interval is expressed as: Mode V [t 4 , t 5 ] ( Figure 5(a)): At time t 4 , turn-ON gate pulse is applied to S c1 . Thanks to the antiparallel diode, this MOSFET is turned ON with ZVS.
Mode VI [t 5 , t 6 ] ( Figure 5(b)): At time t 5 , the parallel capacitors C c1 and C s1 make S c1 turned-OFF with ZVS. A resonant circuit is created consisting of L Lkb , L Lk1 , L Lk2 , C s1 , C m1 , and C m2 . The capacitor C s1 begins to be discharged until its voltage reaches to zero at t 6 .
Mode VII [t 6 , t 7 ] (Figure 5(c)): At time t 6 , the voltage across C s1 reaches to zero. Then, the anti-parallel diode of the main switch S 1 is turned ON. The current falling rates of the diodes D r2 , D b1 and D f1 are controlled by the leakage inductances of the magnetic devices. The following equations are held during this time interval: Mode VIII [t 7 , t 8 ] ( Figure 5(d)): At time t 7 , the turn-ON gate pulse is applied to the MOSFET S 1 . The antiparallel diode makes S c1 turned-OFF with ZVS. The current passing through L Lkb reduces and D r2 and D b1 currents linearly decreases to zero. At t 8 , the diodes D r2 and D b1 currents reaches to zero. At the end of this time interval, D r2 and D b1 are turned OFF with ZCS and their reverse recovery problem is attenuated.
Mode IX [t 8 , t 9 ]: At time t 8 , the diodes D r2 and D b1 turned OFF with ZCS. During this time interval, the current flowing through L Lkb continues to decrease to zero. At t 9 , the diode D f1 is turned OFF. As mentioned earlier, because of limitations on the number of subfigures, the figure of this mode is not shown.
As mentioned earlier, because of the symmetrical configuration of the proposed converter, there are similar operating modes for the remaining switching cycles.

STEADY-STATE ANALYSIS OF THE PROPOSED CONVERTER
As the configuration of the proposed converter is symmetric, it is sensible to assume L m = L m1 = L m2 , C m = C m1 = C m2 , and C c = C c1 = C c2 . The leakage inductances of BIT and CIs are regarded zero. In addition, the capacitors are large enough, so their voltage is considered to be constant during one switching cycle.

3.1
Step-up voltage gain By applying the voltage-second law to the magnetizing inductance L m , the voltages across the clamp capacitors can be obtained as: According to the equivalent circuit of Mode V (see Figure 4(d)), the voltage across C m2 can be expressed as (12). Also, the secondary voltages of CIs (V ns1 and V ns2 ) are as Equations (13) and (14).
According to Equations (11)- (14), the voltage across the multiplier capacitors is as follows: The voltages of the output capacitors can be represented as: (17) According to Equations (15)- (17), the output voltage can be obtained as: Finally, the step-up voltage gain can be calculated as: As can be seen from Equation (19), the step-up voltage gain M can be controlled by duty cycle and turns ratio of the CIs and BIT, and a high step-up voltage gain can be achieved without large duty cycles. Based on the performance analysis presented in section II, the leakage inductance of the magnetic devices impacts the stepup voltage gain M. By considering this impact, the output voltage gain can be extracted as follows: where Q c = L Lk1 f s ∕R out and Q b = L Lkb f s ∕R out . It is obvious that the step-up voltage gain M is affected by the leakage inductances, R out , the switching frequency f s as well as the duty cycle D and the turn ratios of CIs and BIT. By neglecting the leakage inductances, Equation (20) results in Equation (19).

Voltage and current stress
The voltage stress of S 1 , S 2 , S c1 and S c2 is equal to the voltage across C c1 and C c2 as follows: From Equation (21), the voltage stress is inversely proportional to the turn ratios of the magnetic devices. Hence, to reduce conduction losses and cost, low-voltage-rated switching devices with low ON-state resistances can be adopted. The following equations for the voltage stresses of the diodes are provided: The root mean square (RMS) value of the currents through switching devices are obtained as:

Conduction losses analysis
To calculate the mathematical conversion efficiency of the proposed converter and to survey the impact of the component's  [51,52]. The simplified circuit schematic is depicted in Figure 6. Because of the removing the active clamp circuits, there are only four basic operation stages during a switching cycle. When the MOSFETs S 1 and S 2 are in ON state, the voltage on L m2 is given by: When S 2 is ON and S 1 is OFF, the following equations are obtained: By applying volt-sec law to L m2 and considering the symmetry of the converter, we have: When S 1 is ON and S 2 is OFF, the following equations are obtained: The voltage across the output capacitors can be calculated as: Finally, from Equations (29)- (38), the converter efficiency as well as the voltage gain can be calculated as: where A1 = [ (4Nn + 4N + 3n + 4)(2Nn + 2N + n + 2 + nD) Step-up voltage gain and conversion efficiency versus duty cycle for various windings resistances For the following power specifications (equal to those for experimental verification), the mathematical conversion efficiency η and the step-up voltage gain M of the proposed converter are illustrated in Figure 7. As can be seen, the conversion efficiency η and the step-up voltage gain M' are influenced by the parasitic components and are also reduced by growing the winding resistances of the magnetic devices.

Soft-switching performance
ZVS turn-OFF for the main switches is fulfilled thanks to their parallel capacitors. For the clamp switches, ZVS turn-ON is realised naturally once their anti-parallel diodes are in ON state. To achieve ZVS turn-ON operating condition for the main switches (when the clamp switches are in OFF state), the stored energy in the leakage inductances must be higher than that in the parallel capacitors of the main switches, which yields the following restriction: To ensure ZCS turn-OFF for all diodes, the current falling rates of the diodes (as Equations (8)-(10)) must be controlled by using the leakage inductances of the BIT and the CIs.

Coupled-inductors and built-in transformer
The design procedure for the circuit components is conducted by using the experimental specifications as 22 V input voltage to 380 V output voltage and 61% nominal duty cycle.
L m1 and L m2 are designed to assure operating in continuous current mode (CCM) at 10% of full load: By considering D min = 0.5, L mB = 53.3¯Hand having L m , n 1 is computed as: where I Lm,Max denotes the maximum value of the current through magnetizing inductance and is ≈(I in ∕2) + (DV in ∕2L m f s ). B Max represents the maximum amount of the magnetic flux density and A C is the core cross-sectional area of the coupled-inductors. For the proposed converter with 97% conversion efficiency at full load condition, I Lm,Max = 17.3 A is obtained. Also, EE55 core is selected with equivalent area of the magnetic core equal to A e = 354 mm 2 and the maximum flux density of 320 mT. Considering 200mT variation in flux density, n p = n s = 13.02 is obtained (using Equation (44)), which is rounded to 13 turns when fabricating a CI with L m = 57 uH and L Lk = 1.2 uH. From Equation (41), it can be inferred that the proposed converter provides ZVS performance at 12% of load.
When switch S 1 is ON and switch S 2 is OFF, the voltage applied to the primary winding of the BIT is obtained as: where A eB denotes the equivalent area of the magnetic core andΔB B represents the variations in the magnetic flux density of the BIT. Selecting EE55 ferrite core yields N p = N s = 12.42 that is rounded to 13 turns for the same reason as that for CIs. The measured value for the magnetizing and leakage inductances of the BIT are about 790 and 2.5 μH, respectively.

Clamp and voltage multiplier capacitors
The capacitors are designed by taking into account the voltage ripple on them. So, the value of the capacitors can be calculated by: where ΔV Cm and ΔV Cc are the voltage ripple on the C m and C c , respectively. V Cc = 56.7 V and V Cm = 100 V are obtained from Equations (11) and (15), respectively. By restricting the voltage ripple across C m and C c to the 1% and 5% of their steady-state values, respectively, their values are extracted as C m = 7.89 μF and C C = 10 μF. Hence, 10 μF value is chosen for multiplier and clamp capacitors.

Performance comparison
In order to probe the advantages of the proposed converter, a performance comparison between the proposed converter and the converters presented in [34, 38, 42-44, 48-53, 55, 56, 58], and [59] is carried out and the results are provided in Table 1, where the voltage across the diodes in the table is the maximum voltage values of the them. Figure 8 illustrate the comparison results of voltage gain and the voltage stress across the switches and diodes. As can be seen in Figure 8(a), the higher step-up voltage gain belongs to the proposed converter. Moreover, according to Figure 8(b) the voltage stress across the MOSFETs in the proposed converter is the lowest from all. In such a case, devices with low ON-state resistance can be adopted to decrease conduction losses and cost. It is seen from Figure 8(c) that the voltage stress across the diodes in the proposed converter is much lower than the output voltage which is due to using forward-flyback topology and adjusting tuning the turns ratio. Also, ZVS operating condition for all the switches in the proposed converter and the converters presented in [49-53, 55, 56, 58, 59] is realized, whereas this feature is not fulfilled for the converters in [34,38,[42][43][44]48]. Total number of the components is a determinative factor for the volume of the converter at a given switching frequency. It is seen from Table 1 that the proposed converter utilizes 19 total number of components which is lower in comparison with the converters of [38,48,49,55,56]. Therefore, it is estimated that the proposed converter has a smaller volume in comparison with the mentioned competitors. Although the proposed converter implements higher number of components with a larger fabricated volume than [42-44, 50-53, 58, 59]; however, it achieves the highest voltage gain and the lowest voltage stress across MOSFETs which covers its higher components. In order to compare the cost of the proposed topology with other converters, the same parameters (V in = 22 V, V out = 380 V, P out = 600 W, N = n = 1) and similar series of the elements are considered for all converters. Depending on the voltage stress of the MOSFETs, IRFB4110, IRFB4127, and IRFB4137 are selected for MOSFETs with voltage stress of less than to 100, 200, and 300 V, respectively. In addition, MUR840, MUR860, and MUR880 are selected for diodes with voltage stress of less than to 400, 600, and 800 V, respectively. EE55 core for CI and BIT, and torpid core for simple inductor are selected. Also, capacitors are categorized based on their operating voltage of less than to 200, 250, 400, and 450 V, respectively. It should be mentioned that PCB and control circuit are not considered in the price and semiconductor and capacitor prices are obtained from mouser.com website and magnetic core are obtained from local sellers. As can be seen, although the price of the proposed converter is almost higher than the other topologies except [49,55,56], the advantages of the proposed converter are greatly improved related to other converters. According to Figure 8(a), the converters of [48,58], and [59] have the highest voltage gain after the proposed converter. Therefore, they are selected to conduct a comparison in the terms of the RMS current through the main MOSFETs and the diodes which is shown in Table 2. The result of the comparison is shown in Figure 9. It is seen that at a given voltage gain the proposed converter and [58] have a lower RMS current through the MOSFETs in comparison with [59]. Moreover, the proposed converter and [48] have a lower RMS current trough the diodes.

EXPERIMENTAL VERIFICATION
To probe the advantageous of the proposed converter, a 22-380 V prototype with 600 W output power is built in the laboratory with the components' specifications of Table 3. The nominal duty cycle is around 61%. Figure 10(a) shows the experimental results of the output voltage and current. It is seen that the output voltage is about 380 V and the output power is about 1.58 A which provides 600 W output power. Figure 10 Figure 11(a) shows the experimental results of the input current, and the currents through the leakage inductances of the CI. The average value of the input current is about 28.3 A. One can see that 622 W power is drawn from the input power source and the conversion efficiency is about 96.4%. The input current ripple is about 5 A which is 17.6% of input current ripple. Moreover, a good current sharing performance is concluded form  Figure 11(b) shows the experimental result of the current through the leakage inductance of the BIT. Figure 12 shows the experimental results of the drain-source voltage and the current of the main and clamp MOSFETs. The voltage stress across the MOSFETs is clamped to nearly 60 V

FIGURE 12
The experimental results of the drain-source voltage and the current of the main and clamp MOSFETs which is about 15% of the high output voltage and utilization of low voltage rated devices is facilitated. Moreover, ZVS Performance is realized for the MOSFETs through whole switching period. Figure 13 shows the experimental results of the voltage stress and current of the diodes. It is clear that the voltage stresses of the diodes are lower than the high output voltage (nearly V out /2). In such a case, low forward voltage diodes can be implemented which decreases the associated losses and improves the circuit performance. Furthermore, all diodes are turned OFF with ZCS performance and the reverse recovery problems is alleviated.
The dynamic performance of the proposed converter is given in Figure 14. From Figure 14(a), it is clear that the output voltage is well regulated at 380 V when the output power is changed between half load and full load. According to Figure 14(b), the voltage stabilization is also achieved sufficiently while the input voltage is fluctuated between 17, 22, and 27 V. Figure 15(a) shows the measured conversion efficiency of the proposed converter along with its theoretical values. The full load efficiency is about 96.4% and the highest efficiency is 96.8% achieved at 500 W output power. At lower loads, the core losses and skin effect, decrease the experimental efficiency in comparison with the theoretical one. However, by increasing of the load the, effect of these losses decreases and the efficiencies match each other. Figure 15(b) illustrates the full load loss breakdown of the proposed topology in which the detailed losses of the components is given in Table 4. As can be seen, the diode, CI and BIT losses are the predominant power losses in the proposed topology. So, the better graded wires for CI and BIT and using diodes with lower forward voltage improves the conversion efficiency and circuit performance. Total power losses is 16.67 W and the calculated efficiency is about 97.3% which is close to the measured value. Table 5 shows the efficiency comparison between the proposed converter and its competitors in discussed in Table 1. The major factors that affect the conversion efficiency are switching frequency, input/output voltage and output power. At fixed output power, lower input voltage causes higher input current to be drawn from the input side which consequently decreases the conversion efficiency. It is seen that the proposed converter with 100 kHz switching frequency, 22 V/380 V voltage conversion and 600 W output power has a higher conversion efficiency in comparison with the converters of [38, 42-44, 50-53, 37]. Although the converters of [34,48,49,55,58,59] have higher conversion efficiencies; however, their input voltage and/or switching frequency are considerably higher and lower, respectively.

CONCLUSION
An interleaved high step-up converter with ZVS performance has been introduced in this paper. By inserting the secondary windings of the CIs between the clamp circuits and the primary