SIDO coupled inductor-based high voltage conversion ratio DC–DC converter with three operations

Here, a single-input, dual output (SIDO) coupled inductor-based high voltage conversion ratio DC–DC converter is proposed. The proposed converter has the capability of operating as a SIDO converter in a way that the terminal of the input voltage source is exchangeable among the three ports. Therefore, there are three different operation modes for the proposed converter. The voltage conversion ratios of the high voltage ports over the low voltage port can be improved by increasing the turn ratio of the coupled inductors. The main advantage of the proposed converter is achieving high voltage gains with lower number of components for the whole range of duty cycles comparing to the conventional multi-port high voltage gain converters. Moreover, two output voltages of the proposed converter can be simultaneously regulated on different constant levels with a good precision. In this study, the voltage conversion ratios, the inductors’ average currents, the voltage and current stress on the switches are calculated theoretically. Finally, an experimental prototype of 30 V input and 410, 260 V outputs with the power 510 W is implemented and the results are verifying the theoretical ones.


INTRODUCTION
In recent years, the multi-port converters have been more interested for using in renewable energy systems such as photovoltaics (PV), fuel cells (FC), and also electric vehicles (EV) [1][2][3]. In the renewable energy systems, it is important to interface different levels of input and output DC voltages. As a result, dual-input, single-output (DISO) converters in [4][5][6][7] and single-input, dual-output (SIDO) converters in [8][9][10][11][13][14][15][16][17][18][19][20] and single-input, three-output converter in [12] are presented. Multi-input converters are needed to be used in hybrid energy sources [4][5][6][7]. Multi-output converters can be used in off-grid solar home systems and should be able to supply the different electrical consumers with different levels of voltages and powers [12,14]. Moreover, in the grid connected renewable energy sources, by using a series connected DC-AC inverter to the DC output voltage of DC-DC converter, the AC Bus 220 or 400 V with frequency of 50-60 Hz should be available for delivering power to the grid. On the other hand, considering that the least two operating regions based on the duty cycle range. Then, these converters have complicated voltage controlling schemes [4,[6][7][8][9][10][11]. In [12], three high voltage gains are obtained using the switched-capacitor modules. In this converter, the voltages of the three output terminals cannot be regulated simultaneously. Similarly, the presented converters in [8,14,20] cannot be easily controlled, because these converters have just one controlling parameter of the duty cycle, where they have two voltage functions, which should be controlled. The presented SIDO converter in [20] has the capability of operating in a way that the terminal of the input voltage source is exchangeable between each of three ports. This converter suffers from low voltage gains, which is like the conventional boost and buck converters. Among the multi-port converters, some converters have boost and buck operations [21][22][23][24], buck and buck-boost operations [25], boost, buck-boost and buck operations [26,27]. The presented converter in [27] has the reduced number of components but both of the input sources are not able to operate and transfer power at the same time.
In this paper, a new coupled inductor-based single-input, dual output (SIDO) DC-DC converter is presented with the following merits; (i) the proposed converter has high voltage conversion ratio, (ii) the proposed converter has the capability of operating as a SIDO converter in a way that the terminal of the input voltage source is exchangeable among the three ports. This ability has made the converter suitable for versatile applications, (iii) there are three different operation modes for the proposed converter including boost, buck and buck and boost operations that have been explained in details separately, (iv) the voltage conversion ratios of the ports can be improved by increasing the turns ratio of the coupled inductors. As a result, the applied duty cycles to the active switches are not high, even if there is a high voltage gains needed at the load side, (v) comparing to the conventional SIDO converters, the proposed converter can provide high voltage gains with smaller number of components, (vi) the proposed converter has a good dynamic response towards the fluctuations of loads or the input voltage. In this paper, the proposed converter is analysed theoretically. Finally, the obtained analytical results, are reconfirmed by using the experimental results.

OPERATING PRINCIPLES OF THE PROPOSED CONVERTER
The proposed converter is shown in Figure 1. Considering that the proposed converter has the three DC-ports, three SIDO operations exist for the proposed converter which can be modelled as Figure 2.
The operations of the proposed converter are categorized in Figure 2(a) and the power circuit of the proposed SIDO converter with the three operation modes are shown in Figure 2(b-d).
Considering Figure 2(b-d), in the proposed converter, each of the three DC ports can be selected as the input voltage source and other two ports can be considered as output ports. In the proposed converter, the voltage V i is lowest DC voltage and the In the first operation of the proposed converter, the input voltage source is equal to V l and two output loads are R H 1 and R H 2 as shown in 2(b). Considering that the voltages V H 1 and V H 2 are higher than the input voltage (V l ), therefore, this operation can be defined as stepped-up operation. In the second operation of the proposed converter, the input voltage source is V H 1 and two output loads are R H 2 and R as shown in Figure 2(c).
In this operation mode, the voltages V H 2 and V are lower than the input voltage source (V H 1 ), therefore, it can be defined as stepped-down operation. The proposed converter in the third operation has the input voltage source equal to V H 2 and two output loads of and R as shown in Figure 2(d). Considering that one lower voltage (V ) and R H 1 one higher voltage (V H 1 ) than input voltage source (V H 1 ) is obtained at the output ports, as a result, this operation is defined as stepped-up and steppeddown operation.
Based on Figure 1, the power circuit of the proposed converter includes switches S 1 , S 2 , S 3 , S 4 , S 5 , and capacitor C 1 . Moreover, it has the first coupling inductor with two-winding transformer of T 1 , magnetizing inductance of L m1 , leakage inductance of L k1 and second coupling inductor with threewinding transformer of T 2 , the magnetizing inductance of L m2 and leakage inductance of L k2 . The first and second windings of the transformer T 1 have n p1 and n s1 turns, respectively. As a result, the turn ratio of the transformer T 1 is considered as n 1 = n s1 ∕n p1 . In the same way, the turns ratio of second transformer is considered as n 2 = n s2 ∕n p2 = n t 2 ∕n p2 . The capacitor C 1 is assumed to be large enough, so, the voltage across capacitor C 1 would be constant as V C 1 .
The switching pattern of switches and theoretical voltages' and currents' waveforms of the proposed converter in three operation modes are shown in Figure 3.
The voltages across the components in the three operations are same as each other. Therefore, in Figure 3(b,c) the waveforms of voltages are not shown to avoid showing repetitive waveforms. Considering Figure 3(a-c), it can be seen that only the direction of magnetizing inductors currents is changed in three operations. As an example, for the practical application of the experimental prototype of the converter, the input voltage source can be selected as a 30 V FC and the higher output voltages are V H 1 = 418.5 V and V H 2 = 262.5 V. The output voltages can be applied to DC/AC inverters (such as; LS Starvert iS7-750W 400V) to provide 220 V-AC at frequency of 50/60 Hz to supply the grid or off-grid consumers. Furthermore, the experimental prototype of the proposed converter can be utilized for some applications of an electric vehicle or in Green houses. Figure 3(a-c), the conducting interval time for the switch S 1 is equal to D 1 T s and the switch S 2 is ON when the switch S 1 is OFF. The duty cycle of switches S 3 , S 5 is equal to D 2 and the switch S 4 is conducting when the switches S 3 , S 5 are OFF. In the analysis of the proposed converter, it is assumed that D 1 ≥ D 2 . Based on Figure 3, the currents of the inductances L m1 and L m2 have the maximum values (I h1 and I h2 ) at t 2 and t 1 instants, respectively and minimum values (I l 1 and I l 2 ), at t 0 . Based on Figure 3, the proposed converter has three Modes during a switching period where the equivalent circuits are shown in Figure 4.

Based on
The equivalent power circuit of this Mode is shown in Figure 4(a). During this Mode, the switches, S 1 , S 3 and S 5 are conducting, while the switches S 2 and S 4 are OFF. Therefore, it should be written as v Im1 = v Lk1 = V . Con- . Therefore, the currents of the magnetizing inductances are written as: Figure 4(b) shows the equivalent power circuit of this Mode. In this Mode, the switches, S 1 and S 4 are conducting, while the switches S 2 , S 3 and S 5 are OFF. Consequently, the voltage v Lm2 is calculated as v Lm2 = −V C 1 ∕(1 + n s2 + k 2 ). Therefore, the current i Lm2 should be as follows: where, k 2 = L k2 ∕[L m2 (1 + n s2 )]. The inductor current i Lm1 is obtained from Equation (1).  Mode 3 [t 2 ≤ t < t 3 ]: Figure 4(c) shows the equivalent power circuit of this Mode. During this Mode, S 2 and S 4 are conducting, while the switches S 1 , S 3 and S 5 are OFF. Based on Figure 4(c), it can be concluded that i Lk1 = i Lm1 ∕(1 + n s1 ). Accordingly, the voltage v Lm1 is calculated as (V C 1 + V − V H 1 )∕(1 + n s1 + k 1 ). As a result, the current i Lm1 is calculated as follows: where, k 1 = L k1 ∕[L m1 (1 + n s1 )]. The voltage v Lm2 and current i Lm2 is calculated with the same equations as in Mode 2.

VOLTAGE GAIN AND VOLTAGE ON CAPACITOR
By considering the average voltage balance law of the inductors in steady state, the average voltages of v Lm1 , v Lm2 , v Lk1 and v Lk2 during single switching period should be equal to zero. Therefore, the Equations (5)-(7) are as follows: By considering Equation (7), V C 1 ∕V can be calculated as follows: As a result, the voltage conversion ratio of s is calculated as follows: Based on Equations (6) and (7), the voltage conversion ratio of G 2 is calculated as follows: By neglecting the leakage inductances of the coupled inductors, the voltage conversion ratio equations can be simplified as G 2 = (1 + n s2 )∕(1 − D 2 ) and In Figure 5(a,b), radar chart and 3D plot of the voltage conversion ratio of Port 2 with the calculated voltage gain of G 1 considering the number of turn ratio of the coupled inductors along with the duty cycle of the switches is shown to demonstrate the effects of these parameters on the voltage gain of the Port 2. From Figure 5(b), it can be seen that the Port 2 of the proposed converter has the largest operational area (shown in blue) for providing conversion ratios up to 20 times larger than the input voltage. In the same way, Figure 5(c,d) show the voltage conversion ratio of Port 3 which is calculated as G 2 considering the number of turn ratio of the coupled inductors with the duty cycle of the switches. From Figure 5(d), Port 3 of the proposed converter has the large operational areas (shown in blue and dark pink) for providing conversion ratios up to 10 times (blue area) and from 10 to 20 times (dark pink) larger voltages than the input voltage.
In Figure 5, the number of turn ratio of the coupled inductors are considered the same values as n s1 = n s2 = n s and is considered variable as n s = 1, 2, 3, 4, 5, 6, 7, 8, 9. Considering Equations (9)-(10), for an example in first operation mode, by using controlling parameter of duty cycle D 1 , the output voltage V H 1 can be regulated. Moreover, by using the controlling parameter of duty cycle D 2 , the output voltage of V H 2 is regulated.
As a result, the output voltages V H 1 and V H 2 can be easily regulated at each preselected value. For controlling output voltages PI-controller is used. As shown in Figure 6, the switching controlling pulses of the output voltages would be produced.

VOLTAGE STRESS ON SWITCHES
Considering Figure 4(c), the voltage stress on switch S 1 during Mode 3 [(1 − D 1 )T s ] is obtained as follows: Moreover, the switch S 2 is turned off during Modes 1 (D 2 T s ) and 2 [(D 1 − D 2 ) T s ]. Therefore, the voltage stress on the switch S 2 during Modes 1 and 2 is calculated as follows: The switch S 3 is turned off during Modes 2 and 3 [(1 − D 2 )T s ]. Therefore, Considering Figsure 4(b,c), the voltage stress on switch S 3 during Modes 2 and 3 [(1 − D 2 )T s ] is written as follows: The voltage stresses on switch S 4 during Mode 1 [(D 2 T s )] and switch S 5 during Modes 2 and 3, are obtained as follows:

AVERAGE CURRENTS OF SWITCHES, INDUCTORS AND THE OUTPUT CURRENTS
Referring to Figure 1, the average currents passing through the switches S 1 , S 2 , S 3 , S 4 and S 5 during a switching period in steady state are calculated as follows: As a result, in the boost operating mode, the normalized current stress on switches based on the input current in the boost operating mode is calculated as follows: To calculate the normalized switches currents based on the input current I i = (G 1 I o1 + G 2 I o2 ) in the above equations, the output powers of the converter P o1 and P o2 are considered equal to each other (P o1 = P o2 ).
Accordingly, the RMS value of switches currents are calculated as follows: Therefore, the average magnetizing inductance current of i Lm1 is calculated as follows: By considering the current balance law for the capacitor C 1 , the following equation can be written.
Accordingly, the average value of the inductor current of i Lm2 is calculated as follows: According to the power balance law in the proposed converter, I at the low voltage side would be obtained as; The average currents of DC voltages I H 1 , I H 2 , I in the above equations are obtained based on the operation type.
In the first operation, based on Figure 2(b), the output currents I o1 and I o2 are equal to respectively. The output powers should be written as In the second operation, based on Figure 2(c), the output currents I o3 and I o2 are equal to I o3 = −I = V ∕R and I o2 = −I H 2 = V H 2 ∕R H 2 , respectively. The output powers would be obtained as The total output power (P oT ) is written as P oT = P + P H 2 .
In third operation, considering Figure 2(d), the output currents I o3 and I o1 are equal to I o3 = −I = V ∕R and I o1 = −I H 1 = V H 1 ∕R H 1 , respectively. The output powers would be obtained as P = V 2 ∕R and P H 1 = V H 1 2 ∕R H 1 . The total output power (P oT ) is equal to P oT = P + P H 1 .
The currents' ripple of the magnetizing inductances are The maximum and minimum values of the inductor current i Lm1 is calculated as I h1 = I Lm1 + Δi Lm1 ∕2, I l 1 = I Lm1 − Δi Lm1 ∕2, respectively. The maximum and minimum values of the inductor current i Lm2 is written as I h2 = I Lm2 + Δi Lm2 ∕2 and I l 2 = I Lm2 − Δi Lm2 ∕2, respectively.

DESIGN CONSIDERATIONS
In order to achieve continuous conduction mode (CCM) operation of the proposed converter, the average value of the currents passing through the inductances L m1 and L m2 has to be higher than the half of their current ripples. As a result, the following inequalities has to be verified.
Considering [12], to obtain the more accurate designing of capacitors, then, the peak-to-peak value of the total voltage ripple which is mostly considered as ΔV CT = 0.01V C is equal to sum of the voltage ripple across each capacitor (ΔV C ) and voltage ripple caused by the ESR of capacitor (ΔV C −ESR = r C ΔI C ). As a result, the minimum value of capacitors for the maximum C H 1_ min For boost and buck-boost operations

C H 2_ min For boost and buck operations
C _ min For buck and buck-boost operations Proposed ripple free single-input two-output converter voltage ripple of them equal to ΔV C = 0.01 V C − r C ΔI C are calculated as given in Table 1. About the design of output capacitors, the hold-up time requirement for step-load response is also considered [12].

DEVELOPED CONVERTER WITH INPUT CURRENT RIPPLE CANCELLATION
In this part, the developed converter is proposed to eliminate input current ripple of the main proposed converter thoroughly for all ranges of duty cycles considering the method used in [29]. In the developed converter, two extra switches of S 1i and S 2i which have the duty cycles of D 0 and 1 − D 0 , respectively. The duty cycle of D 0 can be selected as the values between zero and one D 0 (0 < D 0 < 1) regardless of the duty cycles D 1 and D 2 . Also. It has used two extra capacitors of C 1i and C 2i , respectively. These capacitors are assumed to be large enough, therefore, the voltages across them would be constant as V C 1i = V i , V C 2i = V , respectively. As shown in Figure 7 one coupled inductor with the inductance of L P for the primary winding, L S for the secondary winding and M for the coupling inductance are used to eliminate the input current ripple. The analytical results of the proposed converter in Figure 7 are summarized as Table 2.
In this part, the required conditions of achieving zero input current ripple at the low voltage side (i ) are obtained during a switching period. According to the Figure 1, the values of inductances L p1 , L s1 , M ps1 , can be replaced based on the used parameters in Figure 1(b) as follows: The voltages across the windings of the first coupled inductor in Figure 1(a) can be written as follows: In the proposed developed converter in Figure 7, during mode 1 (switch S i is on), the following equation can be written: As a result, the voltages v Lp1 and v Lt 1 are equal to V . Time Interval of D 1 T s < t < T s : In this state, based on Figure 1(a), the switch S i is off, therefore, it would be written: It can be written that Considering Equation (38), the required condition to eliminate input current ripple is resulted as following: As a result, the required conditions for achieving zero input current ripple at first stage is obtained as follows: L si = M psi or n si 2 L mi = n si L mi or n si = 1 (43) The maximum and minimum values of current i Lm1 The maximum and minimum values of current i Lm2 The maximum and minimum values of current i Lmi Voltage stress on switches Accordingly, the proposed developed converter in Figure 7, not only eliminates input current ripple at the DC port with high current (low voltage port) for whole ranges of duty cycles, but also increase the voltage gains between input voltage and output voltages (the voltage gains of proposed converter multiplied in the voltage gain of conventional boost converter) by using five elements (S 1i , S 2i , C 1i , C 2i and one coupled inductor). Table 3 presents comparative results of the proposed converter with other dc-dc single input, two-output converters from different aspects including voltage gains of each port (G port ), simultaneous control of output voltages (SCOV), maximum normalized voltage stress on switches based on maximum output voltage (V S n,max = V S −max ∕V o_ max ), normalized current stress for the switch with the maximum voltage stress on it, (I S RMS,n | S ∶VS =VS max ), maximum power for switches of converter (V S , n I S RMS , n ) max , maximum normalized current stress on switches based on average input current ripple (I S RMS, n−max = I S RMS−max ∕I i ). The total voltage gain G T in the two-output converters is defined as Figure 8(a) shows the total voltage gain over duty cycle. Based on Figure 8(a), G T for the proposed converter is higher than other conventional SIDO converters in Table 3.

PERFORMANCE COMPARISON
On the other hand, the voltage gain of two output ports and total voltage gain G T of proposed converter and conventional converters for the specified duty cycle of D = 0.6 and n = 1 are calculated as column 3 of Table 3, which shows that G T for the proposed converter is obtained equal to G T = 12 which is higher than that for the other conventional dual output converters. Figure 8(b) shows the maximum normalized voltage stress on switches over duty cycle. Based on Figure 8(b), V S n,max for the proposed converter (which is the voltage stress on switch S 2 ) is the medium value comparing to other conventional SIDO converters in Table 3.
In the other hand, V S n,max in the proposed converter is lower than the presented converters in [9] and is higher than the presented converters in [8,20,28]). Figure 8(c) illustrates the normalized RMS current over the duty cycle for the switch which has the maximum voltage stress (switch S 2 in the proposed converter). Based on Figure 8(c), I S RMS n | V S =V S max for the proposed

Third converter in [8] ([8]-C)
Proposed converter The cost of converters can be compared with their voltage and current stress on the semiconductors. If the current and voltage stress on each semiconductor multiply together, an equation will be achieved. By this equation (here called S and defined as power of switch), the cost, voltage and current stress on the semiconductors can be compared. As a result, the maximum value for the equation of power of switch S max can be written as follows: Figure 8(d) is plotted to show that, the obtained maximum power of switches (S max ( in the proposed converter (switch S 2 in the proposed converter) has almost the minimum value comparing to other conventional converters of the same type for the duty cycles higher than 0.3 regarding that the proposed converter has the medium value for maximum normalized voltage stress on switch based on Figure 8(b). Also, the maximum normalized current stress on switch (I S RMS,n − max ) is plotted as Figure 8(e). Figure 8(e) shows that the proposed converter has the medium value of I S RMS,n − max comparing to other conventional converters of the same type.
In order to have a simple comparison in Table 3 and Figure 8, all the duty cycles of the compared converters are considered as a same parameter of the duty cycle D(0 < D 1 = D 2 = D < 1). The turns ratio of coupled inductors is considered as n s1 = n s2 = n = 1 in Figure 8. Table 3 shows that the proposed converter and the converter in [20] have the maximum number of operation modes (N Op = 3) and exchangeable place for the input voltage source among each of three ports. Moreover, the proposed converter and presented converters in [9] and proposed converter have the capability of simultaneous control of output voltages.

EXPERIMENTAL RESULTS
In order to reconfirm the analytical results, the experimental results are extracted for first operation (stepped-up mode) of the proposed converter in Figures 8-10. The values of the different elements are summarized in Table 4. According to Equations (8)-(10), the capacitor voltage and output voltages for the parameters in Table 4 (21) and (22), the inductances L m1 and L m2 to achieve CCM operation of the proposed converter,     As a result, the calculated values are reconfirmed by the voltages stresses results in the experimental results in Figure 10. The output currents are calculated as I o1 = −I H 1 = 0.837A, I o2 = −I H 2 = 0.75A. Therefore, considering Equations (17) and (19), the average value of inductors' currents are calculated as I Lm1 = 9.207A and I Lm2 = 13.88A. The current ripple of the magnetizing inductances are calculated as 6A. Accordingly, the maximum and minimum values of current i Lm1 are calculated as I h1 = 11.262A and I l 1 = 7.152A that are almost equal to the illustrated values by experimental results in Figure 9(c).
The maximum and minimum values of the current i Lm2 are calculated as I h2 = 15.68A and I l 2 = 12.08A that are similar to the obtained result in Figure 9 Figure 11, the voltage regulation of both two output ports are achieved at the same time in an acceptable way and the changes of the output voltages are not considerable by the changes of input voltage. Note that the spikes in Figure 11 happens when a sudden change happens in the input port. The implemented prototype of the proposed converter is shown in Figure 12.

POWER LOSS AND EFFICIENCY
In this section, the conduction and switching losses of proposed converter are calculated to obtain the efficiency. As a result, the internal resistors of switches (r S ), inductors (r L ), capacitors (r C ), forward drop voltage of switches (V FS ), rise time (t r ) and fall time (t f ) of switches are considered for calculating power losses. According to [12], conduction losses of switches (P Cond ,S ), switching losses for the switches (P sw,S ), total power loss of switches (P S ,Tot ), total conduction loss of inductors (P Cond ,L ), P Loss E f ficiency P Loss = P S ,Tot + P Cond ,C + P Cond ,L + P Core , E f ficiency = P o ∕(P o + P Loss ) FIGURE 13 (a) Efficiency of proposed converter versus output power; (b) power loss distribution among switches, inductors and capacitors for the output power equal to P oT = 510 W total core loss of inductors (P Core_total ), total conduction loss of capacitors (P Cond ,C ) and total power loss (P Loss ) are calculated as shown in Table 5. Figure 13(a) shows the efficiency of the proposed converter versus output power. The power loss distribution of the proposed converter among switches, inductors and capacitors for the output power of P oT = 510 W is illustrated in Figure 13(b). The switches are considered as Table 2. Therefore, the parameters of switches are as 5 m Ω, r S 4 = r S 5 = 6.6 m Ω, t rS 1 = 105ns, t fS 1 = 74ns, t rS 2 = 13ns, t fS 2 = 10ns, t rS 3 = 320 ns, t fS 3 = 130ns, t rS 4 = t rS 5 = 32ns, t fS 4 = t fS 5 = 14ns. Moreover, the internal resistors of capacitors and inductors are considered as r C = 0.5 Ω and r L = 0.1 Ω, respectively.

SIMULATION RESULTS OF THE PROPOSED DEVELOPED CONVERTER
The used simulation parameters of the proposed developed ripple free converter are shown in Table 6. Table 7 illustrates the analytical results of voltages on switches, capacitors, average currents of switches, average input current and output voltages of the proposed ripple free converter according to the given parameters in Table 6. The calculated results of capacitor's voltages and output voltages which are shown in Table 7 can be verified by simulation results in Figure 16.
The voltage stresses on switches which are calculated in Table 7 during first (0 < t < DT S ) and second (DT S < t < T S ) modes, respectively, are verified by Figure 15.
Based on Table 7, the analytical results of average currents of switches are shown which are almost equal to the obtained average currents of switches by simulation results in Figure 15. For example, according to Figure 15(a,b), the obtained average current of switches S 1i and S 2i by simulation results are as I S 1i | 0<t < DT s ≃ 43.6A, I S 2i | 0<t < DT s ≃ 43.6A (verify calculated analytical results from Table 2 equal to I S 1i | 0<t < DT s ≃ 44.8A, I S 2i | DT s <t < T s ≃ 44.8A). The average value of inductor's currents from Table 7 is verified by Figure 14. The input current waveform is shown in Figure 14(c) which as it can be seen it is almost free ripple DC current with average value of I i = 43.53 A from simulation results (verify theoretical analysis which is seen in Table 7 equal to I i = 44.8A). Figure 14 shows the Simulation results of currents of input side of proposed developed converter to confirm how the developed converter achieve zero input current ripple. By considering the developed converter in Figure 7, the sum of magnetizing inductor current (i Lmi ) and current of first winding of coupled inductor (i Tpi ) would be constant DC value equal to input current of i i as shown in Figure 14. Figure 15 shows the simulation results of voltage stresses on switches. Figure 16 shows the simulation results of voltages of capacitors and output voltages.

CONCLUSION
In this paper, a SIDO high voltage gain coupled inductor-based DC-DC converter is proposed. The proposed converter can be In this converter, the input voltage source can be replaced by any of each three ports. The voltage conversion ratios can be increased by increasing the turns ratio of the coupled inductors. The proposed converter has achieved high voltage gains with low number of components comparing to the conventional multi-port, high voltage gain converters. Moreover, two output voltages of the proposed converter can simultaneously be regulated on different constant levels. In this study, the voltage conversion ratios and the voltage and current stress on switches of the structure is analysed theoretically. Additionally, to demonstrate the validity of calculation results, a 30 V/410 V/260 V Currents passing through the switches at each moment I S 1 Average current passing through the switch S 1 during a switching period in steady state I S 1,n Normalized average current passing through the switch S 1 based on input current for boost operation I S 1−RMS ,n Normalized RMS current passing through the switch S 1 for boost operation I S 2 Average current passing through the switch S 2 during a switching period in steady state I S 2,n Normalized average current passing through the switch S 2 based on input current for boost operation I S 2−RMS ,n Normalized RMS current passing through the switch S 2 for boost operation I S 3 Average current passing through the switch S 3 during a switching period in steady state I S 3,n Normalized average current passing through the switch S 3 based on input current for boost operation I S 3−RMS ,n Normalized RMS current passing through the switch S 3 for boost operation I S 4 Average currents passing through the switch S 4 during a switching period in steady state I S 4,n Normalized average current passing through the switch S 4 based on input current for boost operation I S 5 Average currents passing through the switch S 5 during a switching period in steady state I S 5,n Average currents passing through the switch S 5 based on input current for boost operation I S 5−RMS ,n Normalized RMS current passing through the switch S 5 for boost operation I Lm1 Average magnetizing inductance current of magnetizing inductance of first coupled inductor I Lm2 Average magnetizing inductance current of magnetizing inductance of second coupled inductor i C 1 Average current passing through the capacitor C 1 I l Average current passing through DC voltage port 1 I H 1 Average current passing through DC voltage port 2 I H 2 Average current passing through DC voltage port 3 I o1 Output current of port 1 in boost operation I o2 Output current of port 2 in boost operation I o3 Output current of port 3 in boost operation P Input power from port 1 P H 1 Input Output power from port 2 P H 2 Input power from port 3 P oT Total output power Δi Lm1 Currents' ripple of the magnetizing inductance L m1 Δi Lm2 Currents' ripple of the magnetizing inductance L m2 ΔV CT Peak-to-peak value of the total voltage ripple of the capacitors V C Average value of the voltage across the capacitors ΔV C The voltage ripple across the capacitors ΔV C −ESR Voltage ripple across the capacitors caused by the ESR of capacitors r C Inner resistance of the capacitors ΔI C Current ripple of the capacitors during V C Average voltage across the output capacitor in port 1 V CH 1 Average voltage across the output capacitor in port 2 V CH 2 Average voltage across the output capacitor in port 3 C 1_ min Minimum designed capacitance value for the capacitor C 1 C l _ min Minimum designed capacitance value for the output capacitor at port 1 C | ESR Minimum capacitance value for the output capacitor at port 1 considering Equivalent Series Resistance (ESR) C | THT Minimum capacitance value for the output capacitor at port 1 considering Total holding Time (THT) C H 1_ min Minimum designed capacitance value for the output capacitor at port 2 C H 1 | ESR Minimum capacitance value for the output capacitor at port 2 considering Equivalent Series Resistance (ESR) C H 1 | THT Minimum designed capacitance value for the output capacitor at port 2 considering Total Holding Time (THT) C H 2_ min Minimum designed capacitance value for the output capacitor at port 3 C H 2 | ESR Minimum designed capacitance value for the output capacitor at port 3 considering Equivalent Series Resistance (ESR) C H 2 | THT Minimum designed capacitance value for the output capacitor at port 3 considering Total Holding Time (THT) R Output load at port 1 R H 1 Output load at port 2 R H 2 Output load at port 3 I S Average current passing through the switches I S −ON Average current passing through the switches at the turning on moment r S 1 , r S 2 , r S 3 , r S 4 and r S 5 The internal resistors of switches S 1 , S 2 , S 3 , S 4 and S 5 r L The internal resistors of inductors r C The internal resistors of capacitors V FS 1 , V FS 2 , V FS 3 , V FS 4 and V FS 5 Forward drop voltage of switches S 1 , S 2 , S 3 , S 4 and S 5 t rS 1 , t rS 2 , t rS 3 , t rS 4 and t rS 5 Rise time of switches S 1 , S 2 , S 3 , S 4 and S 5 t fS 1 , t fS 2 , t fS 3 , t fS 4 and t fS 5 Fall time of switches S 1 , S 2 , S 3 , S 4 and S 5 t r Fall time of switch t f Rise time of switch P Cond _S Conduction losses of switches P SW ,S Switching losses for the switches P S ,Tot Total power loss of switches P Cond ,L Total conduction loss of inductors P Core_total Total core loss of inductors P Cond ,C Total conduction loss of capacitors P Loss Total power loss P Core Losses of the cores of the inductors ΔB Lm1 and ΔB Lm2 Flux density of inductors P C 1 and P C 2 Power density of inductors [kW/m 3 ]