A soft switching four-phase converter with ultra-high step down conversion ratio and automatic uniform current sharing

This paper introduces a new high step down four-phase converter with soft switching and automatic uniform current sharing. The phase number of the introduced topology can be expanded. In this converter, the main switches are turned on under zero voltage zero current switching condition and turned off under zero voltage switching. Also, the auxiliary switches and diodes operate respectively under zero voltage switching and zero current switching conditions. In the proposed architecture, the duty cycle is extended and the semiconductors voltage stress is reduced by applying series capacitors and coupled inductors. The leakage energy associated with the coupled inductors is absorbed and the reverse recovery losses of diodes are eliminated. Uniform current sharing between four phases is achieved without any extra current sharing control circuit. Furthermore, by utilizing the interleaved method, the current stress and the output current ripple are reduced. This converter provides above advantages while its input and output grounds are connected. As a result, the introduced topology can provide high step down conversions at high frequen-cies. The converter operation and its characteristics are analysed in detail. The accuracy of the theoretical analysis is veriﬁed by a laboratory prototype.


INTRODUCTION
Recently, DC-DC converters with high step down conversion ratio and large output current have received increasing interests in various applications such as uninterruptable power supplies, unidirectional chargers, electric vehicles, light emitting diode lamps and so on [1][2][3][4]. In electric vehicle applications, a high step down converter is utilized to feed the electronic loads. The multiphase converters are desirable for high current applications. In these topologies, the current is distributed among the phases and thus the current stress of elements would be reduced. For non-isolated conversions where output current ripple is vital, the multiphase interleaved buck converter (IBC) is an appropriate candidate [5], [6]. However, the conventional IBC is not suitable for ultra-high step down applications. In these applications, the extremely narrow duty cycles can ruin the converter proper function. Also, the semiconductor elements have to endure a voltage stress which is equal to the input voltage. Therefore, overrated elements with high conduction loss and severe reverse recovery must be employed. Current sharing between interleaved modules is another important issue in utilizing IBC. Even if control chip generates high consistent multichannel pulse width modulation (PWM) signals, the parameters of drive circuits and power switches are different. Consequently, mismatch between the duty cycle of switches is unavoidable [7]. The gain of interleaved modules is the same, thus a little mismatch between the duty cycles of two modules makes one of them automatically operates in discontinuous conduction mode (DCM). In this situation, the module with higher duty cycle operates in continuous conduction mode (CCM) and the current sharing becomes unbalanced [8].
Switching frequency is an important item in design of DC-DC converters. As the switching frequency increases, the converter size is reduced and the dynamic response is improved. Nevertheless, high switching frequency causes high switching loss and electro-magnetic interference (EMI). Soft switching is an attractive technique to resolve the mentioned difficulties. Therefore, the major research is carried out to provide soft switching condition as well as uniform current sharing in interleaved converters.
Among the various non-isolated step down converters, the series-capacitor buck converter stands out as an appropriate topology. This converter has an extended duty cycle and natural current sharing [9]. Two high step down converters based on the blocking capacitors are introduced in [10] and [11]. The voltage conversion ratios of these topologies are respectively equal to one-third and one-fourth of the conventional buck gain. However, these converters operate under hard switching condition. In [12][13][14][15], the coupled inductor technique is applied to the series-capacitor buck converter. In these topologies, high step down conversion ratio is achieved and high switch voltage spike is eliminated. Also, in [12][13][14], the currents of phases are balanced automatically. The converters introduced in [12] and [13] suffer from hard switching. In the zero voltage switching (ZVS) topologies proposed in [14] and [15], the maximum switch voltage stress is high and equal to the input voltage. A high step-down converter based on the energy-transferring capacitor and non-isolated transformer is presented in [16]. This structure provides the ZVS condition for all switches and reduces the output current ripple. Nevertheless, the voltage stress across main switches is equal to the input voltage. Moreover, in [15] and [16], the currents of phases can be unbalanced due to the complementary operation of the main switches. Twophase converter introduced in [17] can provide high step down conversion ratio. Although this topology reduces the maximum switches voltage stress to half of the input voltage, it requires two extra series inductors to provide the ZVS condition. Four-phase interleaved converters presented in [18] and [19] can quadruple the effective duty cycle. In these converters, the voltage stress on three out of the four switches is equal to half of the input voltage. The voltage stress of diodes is a quarter of the input voltage and uniform current sharing is achieved automatically. In [20], a four-phase converter with low voltage stress and high step-down conversion ratio is introduced. However, the above four-phase converters operate under hard switching condition. A new four-phase ultra-high step down converter is introduced in [21]. In this topology, coupled inductors and series capacitors are applied to improve the voltage conversion ratio. The maximum voltage stress across semiconductors is equal to half of the input voltage and the current sharing between phases is automatic. Nevertheless, the switches turn on under zero current switching (ZCS) and turn off under hard switching condition.
In this paper, a new ZVS four-phase converter with ultrahigh step down conversion ratio is proposed. By combining the series capacitor and coupled inductor techniques, operating duty cycle is considerably extended and the voltage stresses across the semiconductor elements are reduced. Uniform current sharing is achieved without utilizing any extra current sharing control circuit. In addition, ZVS condition is provided for all switches and ZCS condition is achieved for all diodes. Above merits along with common input and output ground improve the overall efficiency of the proposed converter.
The remaining contents of this paper are arranged as follows. In Section 2, the introduced converter is analysed and its operating modes are explained in detail. Section 3 focuses on the converter characteristics and design guidelines. The results of

TOPOLOGY DESCRIPTION AND OPERATING PRINCIPLES
The introduced four-phase converter is depicted in Figure 1. This topology consists of four main switches S 1 , S 2 , S 3 and S 4 , two auxiliary switches S 5 and S 6 , four diodes D 1 , D 2 , D 3 and D 4 , three series capacitors C 1 , C 2 and C 3 , two snubber capacitors C S1 and C S2 , output filter inductors L 1 , L 2 , L 3 and L 4 , output filter capacitor C o and two pair of coupled inductors which n 1 , n 2 , n 3 and n 4 are the coupled windings. The auxiliary switches S 5 and S 6 are used to handle the leakage energy of coupled inductors and to provide the ZVS condition for the main switches at turn on instants. S 5 and S 6 must be four-quadrant switches because they have to be capable of conducting currents and blocking voltages of both polarities. Figure 2 illustrates the equivalent circuit of this converter. Each of the auxiliary switches is realized by connecting two MOSFETs in a common source configuration. These two connected transistors can be controlled by one control signal and simultaneously turned on and off. When both of transistors are on, one of them operates in synchronous rectification mode. The coupled inductors are modelled as magnetizing inductances L m1 and L m2 , leakage inductances L lk1 and L lk2 and ideal transformers where n = n 1 /n 2 = n 3 /n 4 . Capacitors C ds1 , C ds3 , C ds51 , C ds52 , C ds61 and C ds62 are the drain-source capacitors of S 1 , S 3 , S 51 , S 52 , S 61 and S 62 . The drain-source capacitors of S 2 and S 4 are respectively combined with C S1 and C S2 since they are parallel to each other.
The proposed converter operates with the duty cycle D smaller than 0.25. Hence, not only the high step down conversion ratio but also the automatic current sharing can be achieved. To simplify the converter analysis, some assumptions are made as follows. All semiconductor devices are ideal. Series capacitors are large enough so that their voltages V C1 , V C2 and V C3 are almost constant. The input voltage V in and output voltage V o are constant in a switching cycle. The currents of output filter inductors I L1 , I L2 , I L3 and I L4 are almost constant. The magnetizing inductances L m1 and L m2 are considered large enough to ignore the magnetizing currents. Back to back connected MOSFETs are the same and thus C ds51 = C ds52 = C ds5 and C ds61 = C ds62 = C ds6 . The proposed converter operates in CCM and its theoretical key waveforms are shown in Figure 3. The input source and the switch S 1 are placed in series with each other and thus the input current is the same as the current of S 1 . Therefore, the input current is discontinuous.
The converter operation in one switching period can be divided into 22 intervals. Each operating mode is analysed based on its equivalent circuit, and the voltage and current equations of elements are derived. Some of these equations are presented for each interval. By applying the KVL and KCL principles, other current and voltage expressions can be simply obtained from mentioned equations. The voltage and current equations of elements verify the converter operation in each mode. Some of these formulas are required for steady-state analysis and design considerations which are discussed in Section 3. Moreover, the theoretical waveforms shown in Figure 3 are drawn according to these equations. Before the first operating mode, it is assumed that both auxiliary switches and all of diodes are on while the main switches are off. Mode 1 (t 0 < t ≤ t 1 ) (Figure 4(a)): At the beginning of this interval, the auxiliary switch S 5 is turned off. A resonance occurs between L lk2 , C S1 , C ds51 and C ds1 . During this interval, C ds1 is discharged and the voltage across S 1 decreases to zero. Simultaneously, C S1 and C ds51 are charged and their voltages increase to V in −V C2 and V in −V C1 respectively. Therefore, ZVS is achieved for S 51 and S 52 at turn off. The current expressions of L lk2 and D 4 , and the voltage expressions of S 1 , S 2 , S 3 , S 4 and S 5 for this interval are: Mode 2 (t 1 < t ≤ t 2 ) (Figure 4(b)): At t 1 , the body diode of S 1 begins to conduct. Thereby, this switch can be turned on under ZVS. The voltages of S 2 and S 5 are respectively clamped to V in −V C2 and V in −V C1 . As long as the sum of coupled windings currents has not reached the output current of fourth phase, the diode D 4 stays on. In this situation, the difference of input voltage and C 1 voltage is placed across L lk2 . Therefore, the current of L lk2 becomes zero and then increases in the reverse direction. The current of L lk2 and the voltages of L lk2 , S 2 , S 3 , S 4 and output inductors during this interval are: At the end of this interval, the diode D 4 turns off under ZCS because the L lk2 current reaches I L4 /(n+1). Mode 3 (t 2 < t ≤ t 3 ) (Figure 4(c)): In this interval, S 1 , S 6 , D 1 , D 2 and D 3 are on and other semiconductor devices are off. Thereby, the power is transferred from the input source to C 1 and the output load. The output inductor L 4 is charged while L 1 , L 2 and L 3 are discharged. Important equations of this interval are: Mode 4 (t 3 < t ≤ t 4 ) (Figure 4(d)): This interval starts by turning S 1 off. Capacitors C S1 and C ds51 begin to discharge. On the other hand, capacitors C ds1 and C ds52 begin to charge. Therefore, ZVS is achieved for S 1 at turn off. This interval ends when the voltages of D 4 and S 5 decrease to zero. The voltage expressions of S 1 , S 2 , S 5 and D 4 for this interval are: Figure 5(a)]: At t 4 , the auxiliary switch S 5 is turned on. Also, D 4 turns on under ZCS condition. During this interval, the auxiliary switches S 5 and S 6 and diodes D 1 , D 2 , D 3 and D 4 are on while the main switches S 1 , S 2 , S 3 and S 4 are off. Important equations of this interval are: These modes are respectively similar to modes 1, 2, 3, 4 and 5. As a result, they are briefly explained. At the beginning of mode 6, the auxiliary switch S 6 is turned off. A resonance occurs between L lk1 , C S2 , C ds61 and C ds3 . In this interval, C S2 and C ds61 are charged and thus ZVS is achieved for S 61 and S 62 at turn off. Simultaneously, the voltage of S 3 decreases to zero. During mode 7, the body diode of S 3 and diode D 2 are  S 6 are clamped to V C2 and V C2 −V C3 respectively. Mode 9 starts by turning S 3 off. Capacitor C ds3 begins to charge and ZVS is achieved for S 3 at turn off. The voltages of D 2 and S 6 decrease to zero. Finally, at the beginning of mode 10, the auxiliary switch S 6 is turned on. Also, D 2 turns on under ZCS condition. In this interval, S 1 , S 2 , S 3 and S 4 are off and other semiconductors are on. The voltage expressions of S 1 , S 2 , S 3 , S 4 , L lk1 and L lk2 are the same as Equations (20) and (21). Also, the currents of L lk1 and L lk2 during mode 10 are: Mode 11 (t 10 < t ≤ t 11 ) (Figure 6(b)): At t 10 , the auxiliary switch S 5 is turned off. The C ds1 and C ds52 voltages increase through a resonance with L lk2 . Simultaneously, the voltage of C S1 decreases and reaches zero at the end of this interval. The L lk2 current and the voltage equations of S 1 , S 2 , S 3 , S 4 and S 5 for this interval are: Mode 12 (t 11 < t ≤ t 12 ) (Figure 6(c)): This interval starts when the body diode of S 2 begins to conduct. In this situation, S 2 is turned on under ZVS. During this interval, D 3 stays on and the voltages of S 1 and S 5 are respectively clamped to V in −V C2 and V C2 −V C1 . Therefore, the difference of C 1 and C 2 voltages is inversely placed across L lk2 . So, the L lk2 current decreases to zero and then increases in the reverse direction. At the end of this interval, D 3 turns off under ZCS because the L lk2 current reaches −I L3 /(n+1). The current of L lk2 and the voltages of L lk2 , S 1 , S 3 , S 4 , L 1 , L 2 , L 3 and L 4 are: Mode 13 (t 12 < t ≤ t 13 ) ( Figure 6(d)): In this interval, S 2 , S 6 , D 1 , D 2 and D 4 are on and other semiconductors are off. Thus, C 1 is discharged and its energy is transferred to C 2 and the output load. The inductor L 3 is charged while L 1 , L 2 and L 4 are discharged. Important equations of this interval are: (Figure 7(a)): At the beginning of this interval, S 2 is turned off. A resonance occurs between L lk2 , C S1 , C ds1 , C ds51 and C ds52 . Capacitors C ds1 and C ds52 begin to discharge, C S1 and C ds51 begin to charge and ZVS is achieved for S 2 at turn off. This interval ends when V D3 decreases to zero. The current of L lk2 and the voltages of S 1 , S 5 and D 3 are: (Figure 7(b)): At t 14 , the diode D 3 turns on. During this interval, the voltage of S 1 decreases to V in −V C1 . Simultaneously, the voltage of S 5 increases and reaches zero at the end of this interval. The L lk2 current and S 5 voltage expressions for this interval are:   (20) and (21). Also, the current of L lk1 is:

DC conversion ratio
The conversion ratio is derived by using the volt-second balance principle on the output inductors. The fourth, ninth, fourteenth and twentieth modes are neglected due to their very small durations. The durations of second, seventh, twelfth and eighteenth modes are calculated as: (46) By applying the volt-second balance principle on L 1 , L 2 , L 3 and L 4 , the following relations are obtained respectively. where T is the switching period and D is the duty cycle of main switches. From Equations (47) and (48), the voltages of C 2 and C 3 are: Based on Equations (49) and (50), the following equations are derived.
(52) According to Equations (51) and (52), V in is calculated as: (n + 1) DT (53) By replacing I L1 , I L2 , I L3 and I L4 with I o /4 (which is discussed in the next Section (Section 3.2)), the following equation is derived.
Finally, the voltage conversion ratio of the proposed converter is obtained as: where R is the output impedance and I o is replaced with V o /R in the calculation process. If the leakage inductances are ignored due to their negligible values, the voltage conversion ratio is expressed as:

Automatic uniform current sharing
To confirm the converter automatic uniform current sharing characteristic, the currents of output inductors are assumed constant. By ignoring the change of C 1 voltage in modes 1, 4, 11, 14 and 15 due to its negligible value, the C 1 current waveform can be presented as Figure 9.
Based on Equations (8) and (28), the following durations are calculated.
(58) By applying the ampere-second balance principle on C 1 and utilizing Equation (52), the below equation is obtained. (59), it is simply derived that I L3 = I L4 . Similarly, the ampere-second balance principle on C 2 and C 3 are not valid unless I L2 = I L3 and I L1 = I L2 . On the other hand, the output current I o is the sum of the output inductors currents. As a result, the following relation is derived.
Based on Equation (60), the automatic uniform current sharing between four phases is proven. With unequal duty cycles (main switch on-times), there is a shift in the inductor currents. The proposed converter is simulated by OrCAD for the output power of 400 W, output voltage of 10 V, and input voltage of 400 V. The component specifications are denoted in Table 2. Figure 10 shows the impact of increasing or decreasing the duty cycle. In Figure 10(a), the duty cycle of all main switches is 0.21. In Figure 10

Voltage stress across semiconductor devices
For symmetrical operation of the proposed converter, the value of L lk1 should be equal to L lk2 value. From Equations (51), (52) and (61), the voltages of C 1 , C 2 and C 3 are: By applying the KVL principle on intervals 3, 8, 12 and 18, the voltage stresses across the switches are obtained as: Also, the voltage stress on diodes is determined by applying the KVL principle on intervals 3, 8, 13 and 19.

ZVS condition
The snubber capacitors limit the rate of voltage change for the switches at turn off instant and thus provide the ZVS condition.
On the other hand, the voltage of switches must be reduced to zero just before turn on instant for providing ZVS at turn on. As a result, to achieve the ZVS condition for the switch S 2 , its voltage must reach zero at the end of interval 11. So, according to Equation (25), the below inequality should be satisfied.
Also, the ZVS condition for the switches S 1 , S 3 and S 4 is achieved when their voltages respectively reach zero at the end of intervals 1, 6 and 17. Therefore, inequalities related to these switches can be achieved in a similar way. Finally, by substituting Equations(60)-(62) into obtained inequalities, the ZVS condition for all of main switches is achieved when:

Capacitors C 1 , C 2 and C 3
By utilizing the voltage ripple equation, the value of C 1 is calculated according to Figure 9 and Equation (60).
Also, the values of capacitors C 2 and C 3 are obtained in a similar way. Consequently, based on Equations (61) and (62), capacitors C 1 , C 2 and C 3 can be designed as follows: where f is the switching frequency and ΔV Ci is the voltage ripple of each capacitor. If the leakage inductances are ignored due to their negligible values, the capacitors C 1 , C 2 and C 3 can be designed as:

Magnetizing inductances
To decrease the conduction losses, the amount of magnetizing inductances should be chosen large enough. In practice, to design the magnetizing inductances, the values of magnetizing currents are selected less than 10% of the maximum current of transformers in each direction. As a result, L m1 and L m2 can be designed as below: According to Equations (60)-(62), the following equation is derived.
If the leakage inductances are ignored due to their negligible values, L m1 and L m2 can be designed as:

Loss analysis
In this section, the approximate loss of each converter element are calculated. In the proposed converter, the switching losses and the capacitive turn-on losses of the switches are approximately eliminated due to soft switching. Also, the inductor core loss is ordinarily small in comparison to other losses. Therefore, the mentioned losses can be neglected. The conduction losses of switches are: , R ds5 and R ds6 are respectively the drain-source resistance of switches S 1 , S 2 , S 3 , S 4 , S 5 and S 6 .
The conduction losses of diodes are: where V F and r f are respectively the forward voltage drop and dynamic resistance of diodes. The conduction losses of inductors are: where R L1 , R L2 , R L3 , R L4 , R L5 , R L6 , R L7 and R L8 are respectively the winding resistance of inductors L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , L 7 and L 8 . Finally, the conduction losses of capacitors are: where R C1 , R C2 and R C3 indicate the equivalent series resistance (ESR) of the capacitors C 1 , C 2 and C 3 respectively. Loss analysis results of the proposed converter at full load are illustrated in Figure 11. These results are obtained based on the component specifications of presented prototype in Section 4.

Comparison of the introduced converter with recent counterparts
A comparison between the proposed converter and recent counterparts is provided in Table 1. In comparison to the conventional IBC shown in Figure 12, the introduced method uses three extra capacitors, two extra pairs of back to back connected MOSFETs and two pairs of coupled inductors for four-phase structure. If this method is applied to two-phase structure, only one extra capacitor and one extra pair of connected transistors and coupled inductors are required. Moreover, each pair    As it can be seen in Table 1, the presented topology in [17] uses two extra switches, three extra capacitors, two extra inductors and one pair of coupled inductors for two-phase structure. In [22], three extra switches, three extra capacitors and one pair of coupled inductors are used for one phase. The introduced method in [23] requires two extra capacitors, one extra switch and one extra inductor for two-phase structure. In [24], two extra switches, three extra capacitors and two pairs of coupled inductors are used for two phases. The three-phase converter proposed in [25] uses five extra capacitors, four extra diodes and two extra inductors. In [26], it can be seen that the current is inherently shared among two phases of the series capacitor buck converter. In [27], a current sharing strategy for three-phase series capacitor boost converter is introduced. In this topology, the input current is inherently shared between three phases in 2/3 < D ≤ 1 operating mode, and thus no other current sharing operation is required.
In [28] and [29], the coupled inductor technique is respectively applied to the buck converter and series-capacitor buck converter. In these topologies, the ZVS condition is provided for all switches. However, the voltage conversion ratios are not improved. In addition, the output current ripple in these con-verters is larger than the hard switching counterparts. To reduce this additional ripple, the turns ratio of coupled windings must be increased. In the proposed soft switching technique, the output current ripple is low, and the extreme step down conversions can be obtained by adjusting the turns ratios of coupled windings.
Switching frequency, voltage conversion ratio, output current ripple, voltage and current stresses, and common ground between the input and output ports are important items in design of high step down converters with large output current. In the proposed converter, the currents of phases are balanced automatically. Also, by utilizing the switching algorithm shown in Figure 3, the current ripple of each phase is significantly reduced by the current ripple of other phases. Therefore, compared to the topologies with lower phase number, this converter has lower current stress and output current ripple. In the introduced topology, the voltage stress across the main switches is equal to half of the input voltage. The voltage stresses on the auxiliary switches and diodes are equal or less than onefourth of the input voltage. Furthermore, its input and output grounds are connected. The three-phase converter introduced in [25] suffers from hard switching and separated ground. The four-phase converters proposed in [18][19][20] operate under hard switching condition and their voltage conversion ratios depend only on the duty cycle. Thus, their duty cycles would be narrow in ultra-high step down applications. Moreover, in [19] and [20], the separation of input and output grounds can limit the converter applications.
In the introduced topology, the voltage stress across the main switches is equal to half of the input voltage. Also, the voltage stresses on the auxiliary switches and diodes are equal or less than one-fourth of the input voltage. In comparison to other high step down four phase converters, this one provides ZVZCS condition for the main switches at turn on instant. Also, all of switches turn off under ZVS condition. Therefore, the turn-on switching loss and the capacitive turn-on loss of the FIGURE 13 Comparison of the voltage conversion ratio versus duty cycle switches are eliminated. In addition, the turn-off switching loss is very low due to ZVS and low current and voltage stresses. In the proposed converter, all of diodes turn off under ZCS condition and thus the reverse recovery losses associated with the diodes are eliminated. These achieved soft switching conditions reduce the switching losses and EMI noises. The above advantages along with very extended duty cycle can provide high step down conversions at higher frequencies. Consequently, the size of magnetic components and capacitors is reduced. Figure 13 shows the voltage conversion ratio of the introduced topology compared with recent counterparts when n = 1. The introduced method can be applied to K phases, where K is even. The voltage conversion ratio of the proposed K-phase topology is: According to Equation (96), the conversion ratio can be reduced by increasing the number of phases. Based on the mentioned above, the introduced converter is efficient for several applications such as light emitting diode lamps, uninterruptable power supplies, voltage regulator modules, communication systems, electric vehicles, unidirectional chargers and hybrid electric vehicles.

EXPERIMENTAL RESULTS
A 400 W laboratory prototype of the introduced topology is implemented at 400 V input, 10 V output and 100 kHz operating frequency. IRFP254 is used for the main and auxiliary switches. The duty cycle of all main switches is 0.21. It expands in comparison to the duty cycle of switches in the conventional IBC and the conventional series capacitor buck converter proposed in [18]. For the input voltage of 400 V and output voltage of 10 V, the duty cycles of switches in these conventional topologies are respectively equal to 0.025 and 0.1. According to Equation (73), the value of selected magnetizing inductances is equal to 100 μH. Four 100 μH inductors are used for the output inductors. Also, two 5 nF capacitors are used as the snubber capacitances. The value of output capacitor is equal to 220 μF. In addition, based on Equation (69), three 10 μF capacitors are used as C 1 , C 2 and C 3 . The component specifications of the prototype are denoted in Table 2.
The experimental waveforms are illustrated in Figures 14-17. As it can be observed, the voltages of switches S 1 , S 2 , S 3 and S 4 are reduced to zero just before increment of switches currents and thus the ZVS condition is achieved at turn on instants. Also, the ZVS condition at turn off instants is provided for these switches because the rate of their voltage changes has been limited. All of diodes turn off under ZCS condition because their currents decrease to zero just before increment of diodes voltages. Moreover, the currents of D 2 and D 4 remain zero after their voltages reach zero. When the current of D 3 reaches zero, a resonance occurs between L lk2 , C ds1 , C ds3 , C ds51 , C ds52 and the parasitic capacitance of D 3 . Therefore, the voltage waveforms of S 1 , S 3 , S 5 and D 3 have oscillations which are respectively damped to (1+2n)V in /4(1+n), (2+n)V in /4(1+n), −nV in /4(1+n) and V in /4(1+n). Also, when the current of D 4 reaches zero, a resonance begins between L lk2 and the parasitic capacitance of D 4 . Thus, the voltage waveform of D 4 has oscillations which are damped to V in /4(1+n). The similar resonances occur when the diodes D 1 and D 2 turn off. The current waveforms of output inductors L 1 , L 2 , L 3 and L 4 are illustrated in Figure 17. As it can be seen, the current ripple of each phase can be significantly reduced by the current ripple of other phases. The efficiency of the proposed converter versus the output power is presented in Figure 18. The efficiency has been measured for various loads when the input and output voltages are constant. The efficiency can be expressed as where P o is the output power and P i is the input power. The efficiency has been measured for the output currents of 5, 10, 15, 20, 25, 30, 35 and 40 A, when V in and V o are respectively fixed at 400 and 10 V. Then, the efficiency curves are drawn based on the measured efficiencies. Even though the efficiency curves do not match exactly, the profile of both plots is similar. In simulation, some of the parasitic elements are ignored, and some of them cannot be modelled exactly due to the difference between parasitic elements values of fabricated components (as it can be observed in various datasheets, there are minimum and maximum values for each parameter of elements). In addition, the parasitic resistances of tracks can also impact on the measured efficiencies. A picture of the prototype is presented as Figure 19.

FIGURE 19
Picture of the prototype

CONCLUSIONS
A new soft switching four-phase interleaved converter is presented in this paper. The number of phases can be expanded to K, where K is even. Introduced topology, by utilizing a new switching algorithm, provides the ZVS condition for all switches and the ZCS condition for all diodes. Therefore, the turn-on switching loss and the capacitive turn-on loss of the main switches are eliminated. Also, the turn-off switching loss is very low and the reverse recovery losses associated with the diodes are eliminated. This converter utilizes the series capacitors as voltage sources to decrease the input voltage and clamp the switches voltage stress. In addition, it uses the coupled inductors and thus extreme step down conversions can be obtained by adjusting the turns ratios of coupled windings. Furthermore, automatic uniform current sharing between four interleaved modules is achieved due to the charge balance principle of capacitors. Common input and output ground, low output current ripple and low voltage stresses on the semiconductor devices are other important strengths of the proposed converter. The validity of converter operation and relevant analysis is confirmed by implementation of an experimental prototype.