Modiﬁed grey wolf optimisation based reduced device count 17-level hybrid multilevel inverter

A 17-level hybrid multilevel inverter (HMLI) using modiﬁed grey wolf optimisation (MGWO) is proposed here. The proposed HMLI requires only a single dc source and a lesser number of circuit elements to obtain a multilevel voltage level. The proposed HMLI can also enhance the input voltage and has reverse current carrying capability. The selective harmonic elimination pulse width modulation technique is implemented through MGWO for determining the optimal switching angles of the proposed HMLI to eliminate lower order harmonics. The MGWO algorithm gives improved results as compared to other existing optimisation algorithms in terms of ﬁtness value, convergence speed and harmonic proﬁle of the output voltage. The proposed HMLI is also compared with some of the other existing HMLIs in terms of the number of circuit elements, peak inverse voltage and total blocking voltage to exhibit its advantages. Finally, a 550 W prototype is fabricated in the laboratory to evaluate the effectiveness of the proposed HMLI.


INTRODUCTION
The requirement of high-power quality in industrial and renewable energy applications such as photovoltaic and wind has influenced the introduction of multilevel inverters (MLIs). In recent years, MLIs have drawn much attention in medium and higher power applications for their low switching frequencies and capability to resist higher voltages [1]. The principal benefits of MLIs are lower total harmonic distortion (THD), lower EMI, and higher efficiency. MLIs are categorised into diode-clamped [2], flying capacitor [3], and cascaded H-bridge topologies [3], [4] in general. Diodes and capacitors are used to obtain the voltage levels in diode clamped and flying capacitor MLIs. However, these MLIs need more number of power switches, capacitors and diodes to obtain voltage levels. In cascaded H-bridge (CHB) MLIs do not require capacitors or diodes but CHB-MLIs need more number of dc power supplies for obtaining a greater number of voltage levels.
The use of a greater number of input dc sources in cascaded H-bridge MLIs increases the cost of the overall system. In order to reduce the number of input dc sources and switches in cascaded H-bridge MLIs, hybrid cascaded H-bridge MLIs have been reported, where capacitors are used to reduce the number of input dc sources [5][6][7][8]. As hybrid H-bridge MLI topologies use capacitors and dc sources, the voltage balance of capacitors is an intrinsic problem. Different control methods are proposed for balancing the capacitor voltages in hybrid H-bridge MLIs. All the structures make these topologies more complicated and costly. In [9] and [10], coupled inductor-based MLIs are presented; however, more number of inductors are required to obtain higher voltage levels, which increases cost and make the overall system bulkier. Moreover, the possibility of extending the number of output voltage levels is also not feasible in these MLIs.
During the last decades, several modular multilevel converters (MMC) have been proposed [11][12][13]. Submodule (SM) is the basic component of MMC. The submodules are classified into two categories: two-level submodule topologies with a single source and multilevel submodule with multiple voltage sources. The half-bridge submodule is the popular configuration because it is simple among all the SM topologies [11]. However, the components in these topologies are high and capacitor balancing is one of the major issues, which also need voltage sensors. A new type of self-balancing submodule is proposed in [12] and [13]. It uses a half-bridge SM with an inductor and one diode. The component counts and the use of the inductor increase its cost.
Switched-capacitor multilevel inverters (SC-MLIs) have emerging technology to solve the problems of capacitor voltage balancing and the required numbers of circuit components used in conventional MLIs. The topology presented in [14] uses battery cells to obtain the output. The proposed topology uses lesser passive devices but the required number of active devices is high. Several topologies of SC-MLIs have been reported in recent years [15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In the topologies [15][16][17][18], single source is used. However, total blocking voltage (TBV) and peak inverse voltage (PIV) increase rapidly with the increased number of output voltage levels. The topologies presented in [20], [22] and [24] possess low PIV but they require more number of switches. Topologies in [19] and [25] possess low TBV, but the required number of switches in these MLIs are very high. The topology presented in [28] has low TBV and PIV, and it also requires lesser number of capacitors. However, its boosting ability is restricted. Thus, it has been observed that for increasing the output voltage levels in existing SC-MLIs, the number of active and passive elements increases, which makes the overall system voluminous and expensive.
Among the aforementioned issues, a number of dc voltage sources and switch count are identified as one of the most important issues in the implementation of a hybrid multilevel inverter (HMLI), since each switch requires an extra gate driver, protection unit, and voluminous heat sink which adds up to the cost and volume of the overall system. In order to take care of these issues, a new 17-level self-voltage balanced SC-MLI is proposed, which generates higher output voltages using a single dc voltage source and a lower number of switches along with the reduced TSV and PIV, thus lowering the rating of power devices used. The topology possesses reverse current capabilities. It can also be scaled to generate higher voltage levels as per necessity. The capacitors are periodically charged and discharged without any additional balancing mechanism. Output voltages higher than input voltage are achieved by the proposed HMLI, thus signifying the boosting property of the converter.
Different pulse width modulation (PWM) techniques used in HMLIs are categorised based on their switching frequencies.
Sinusoidal pulse width modulation and space vector modulation (SVM) are the commonly used high-frequency switching techniques. In these switching techniques, losses will be more, and distortion in the output voltage is also high. The complexity in computation is one of the major disadvantages of SVM. Higherorder harmonics can be eliminated using low-pass filters, but lower-order harmonics cannot be completely eliminated using conventional PWM techniques. Selective harmonic elimination PWM (SHEPWM) is a popularly used PWM technique to determine optimal switching angles so as to eliminate lower order harmonics by solving non-linear transcendental equations. The iterative techniques such as Newton-Raphson and the theory of resultant methods are taken to solve the non-linear transcendental equations. However, the use of these methods is not practical for a large number of switching angles to be solved as the degree polynomials in the non-linear transcendental equations increase for higher number of harmonics and have to be removed. Evolutionary algorithms have been used to overcome limitations of conventional iterative methods [29][30][31][32][33][34][35][36][37] such as genetic algorithm (GA) [29], ant-colony optimisation (ACO) [31], firefly algorithm (FA) [32], bee algorithm (BEE) [30], particle swarm optimisation (PSO) [33] and fish swarm optimisation (FSO) [34]. Genetic algorithm (GA) is one of the early developed evolutionary algorithms [19], which works on crossover and mutation. The early convergence, high computational time and weak local searching capability are the demerits of GA. GA has a slower convergence rate in comparison to BEE and ACO. Particle swarm optimisation (PSO) is another widely used bioinspired evolutionary algorithm. It has been observed that for PSO outstrips ACO and BEE in terms of convergence, PSO does not possess any evolutionary criterion like mutation and crossover, but its convergence speed is less and it also fails to find global optima precisely. This problem can be solved by applying FA. It gives better convergence and less possibility of being trapped at local minima in comparison to PSO, but FA possesses lesser convergence speed as compared to PSO. Newly, PSO redeveloped fish swarm optimisation has been proposed [34]. It provides better performance as compared to FSO and PSO.
Grey wolf optimisation (GWO) algorithm is one of the recently developed meta-heuristic algorithms. GWO impersonates the hunting behaviour and ladder of grey wolves [36]. It uses four different stages to attain global optima such as searching, surrounding, stalking and attacking the prey. However, GWO agonises from poor convergence speed and infirm local searching capability because of its simple location updating strategy. To take care of this problem, a modified GWO (MGWO) algorithm-based switching technique is used in this work [37]. MGWO keeps the balance between exploitation and exploration of searching mechanism. MGWO avoids stagnation of local minima using the weighted sum of best locations in its position upgrade strategy. The rate of convergence of MGWO is faster as compared to GA, PSO and GWO. The present work investigates MGWO optimised reduce device count 17level HMLI.
Section 2 delineates the proposed 17-level HMLI and its operation. Section 3 explains MGWO algorithm and its implementation for harmonic elimination in HMLI. The capacitor calculation of the HMLI is given in Section 4. The comparison of HMLI with other reported HMLIs is given in Section 5. In Section 6, the experimental verification of the proposed 17level HMLI is deliberated. Finally, the conclusion of the paper is described in Section 7.

PROPOSED 17-LEVEL HYBRID MULTILEVEL INVERTER
The structure of the proposed 17-level HMLI is depicted in Figure 1. It follows series-parallel combinations of capacitors and voltage source to obtain levels. It consists of a single dc source, four capacitors C 1 -C 4 , five diodes D 1 -D 5 and eleven switches S 1 -S 5 , M 1 -M 2 and Q 1 -Q 4 . The capacitor voltages of C 1 , C 2 and C 3 are maintained at the input voltage V DC , whereas the capacitor voltage of C 4 is maintained at V DC /2. The voltage balancing mechanism of capacitor C 4 is given in the Appendix. The switching and capacitor states for each voltage level of 17-level HMLI are given in Table 1. In the column of switches, 1 represents turn ON and 0 for turn OFF. In the column of diode, 0 and 1 represent reverse blocking and forward conduction, respectively. The direction of current of each positive voltage levels are depicted in  Level 2V dc , Figure 3a: It is achieved using voltage source V dc diode D 3 , and switches S 2 , Q 1 , M 2 and Q 4 . The capacitors C 2 and C 3 charge in this interval through (D 2 , D 4 , S 4 , S 2 ) and (D 3 , D 5 , S 4 , S 2 ) and capacitor C 1 discharges through D 3 , S 2 , Q 1 , M 2 and Q 4 .
Level 5V dc /2, Figure 3b: This voltage level is achieved using diode D 1 and switches S 1 , S 3 , Q 1 , M 1 and Q 4 . The capacitors C 2 and C 3 are in series with source and discharge using D 1, S 1 , S 3 , Q 1 , M 1 and Q 4 to obtain output. The capacitor C 4 gets charged in this interval.
Level 3V dc , Figure 3c: It is achieved using diode D 1 and switches S 1 , S 3 , Q 1 , M 2 , and Q 4 . The capacitors C 2 and C 3 are in series with dc source and discharge through path D 1, S 1 , S 3 , Q 1 , M 2 and Q 4 to generate output voltage.
Level 7V dc /2, Figure 3d: It is achieved when the current flows in the diode D 1 and switches S 2 , S 1 , S 3 , Q 1 , M 1 and Q 4 . The C 1 , C 2 and C 3 are in series with dc source and they discharge using D 1 and switches S 1 , S 3 , Q 1 , M 1 and Q 4 to generate the required output voltage. The capacitors C 4 charges in this interval.
Level 4V dc , Figure 4: It is achieved using diode D 1 and switches S 2 , S 1 , S 3 , Q 1 , M 2 and Q 4 . The C 1 , C 2 and C 3 are in series with source and discharge using switches S 2 , S 1 , S 3 , Q 1 , M 2 and Q 4 to generate the required output voltage. Similarly, other voltage levels can be obtained through switching patterns given in Table 1.

Scaled structure of the proposed 17-level HMLI
The extended structure of the proposed HMLI is attained through the addition of another unit (m) which consists of a switch S 3a , one capacitor C 3a and two diodes D 3a , D 5a. Each such extended unit adds four voltage levels. The extended structure of the proposed HMLI (generalised; 17+4m) is depicted in Figure 5. The voltage levels in the extended structure can be obtained by adding switches S 3a , S 3b ,…, S 3m ; capacitor C 3a , C 3b ,…, C 3m and diodes D 3a , D 3b , D 3c ,…, D 3m and D 5a , D 5b , D 5c ,…, D 5m . To obtain higher voltage levels (more than 17), the proposed 17-level HMLI does not need any extra dc voltage source or capacitor balancing mechanism.

Generalised structure of the proposed 17-level HMLI
The number of circuit components for generating 4n + 1 (n = number of capacitors) voltage levels (N l ) in generalised 17level HMLI is given as where N source , N switch and N diode are the number of dc sources, switches and diodes, respectively. The total blocking voltage (TBV) across the switches of the proposed HMLI is calculated by summing the respective PIV of each switch. The PIV across each switch is given in Table 2. For the HMLI, the TBV can be derived as follows: Switching angles of the proposed 17-level HMLI Substituting the values as listed in Table 2 and generalising for HMLI with n capacitors: The per-unit TBV (TBV pu ) is derived as the ratio of TBV to maximum PIV across HMLI.
Substituting the values, TBV pu is obtained as

SWITCHING SCHEME
SHE switching method is applied using MGWO to obtain optimum switching angles for 17-level HMLI. Switching angles along with different voltage levels are shown in Figure 6.
The quasi-square output voltage waveform of the 17-level HMLI is given as where ω is the angular frequency. The amplitude modulation index (M of ) is stated as The switching angles for 17-level HMLI θ i (i = 1-8) are obtained using cos 1 + cos 2 + cos 3 + cos 4 + cos 5 + cos 6 where h is the number of harmonics to be eliminated from the output voltage. The harmonics such as 3rd, 5th, 7th, 9th, 11th, 13th and 15th are taken to obtain optimum switching angles.

Modified GWO
In GWO, grey wolves are categorised into social ladders as α, β, δ and ω. In order to mathematically model the social hierarchy of wolves, α is considered as the fittest solution. Consequently, the second and third best solutions are named β and δ, respectively. The rest of the candidate solutions are assumed to be omega ω. The positions of grey wolves are updated using Equations (9) and (10), given as: where j is the current iteration; X: position vector of wolf; X pp : position vector of prey, and A and C are coefficient vectors. The vector A is written as: and vector C as: where a is a coefficient vector; r 1 and r 2 are random vectors. Generally, higher exploration of search space results in a lower probability of local optima stagnation. In order to further improve the convergence rate of the GWO algorithm, the following modification (in co-efficient vector a) is employed to enhance the exploration-exploitation balance of GWO algorithm as follows: where β and θ are two control parameters, which regulate the convergence behaviour of GWO algorithm over the iterations k for each point. In addition, by converting the vector a to a random nonlinear vector, both exploratory and accelerated convergence is achieved in the proposed MGWO algorithm.
Chaotic search technique is used for improved local search and stagnation of local minima [38]. Chaotic equation for local refinement is described as where x j is a variable ( j = 0, 1, 2 ⋅ ⋅⋅) and is the control variable. The chaotic search is given as where cx n j denotes the chaotic variable and n indicates iteration number.
The steps used for the searching mechanism is given as follows: Step 1: The decision variables x n j (x min, j , x max, j ) is mapped into chaotic variables cx n j using Step 2: The chaotic variables cx n+1 j are calculated for the next iteration using (14).
Step 3: The chaotic variables cx n+1 i are converted to decision variables x n+1 j using x n+1 Step 4: New results are determined using the variable x n+1 j .
Step 5: If the optimum result is obtained or maximum iterations are achieved, then the obtained optimum solution is taken as the final solution; or else, return to step 2.
To attain faster global optima, the position update equation is weighted in each iteration as given in Equation (20). The coefficient vectors are calculated using Equation (13) and A 1 , A 2 and A 3 are obtained using Equation (11).
where w 1 , w 2 and w 3 are the corresponding weights.
The wolves update their position as an average of the three best grey wolves α, β and δ. This leads to premature conver-gence. In order to overcome this demerit, the weighted distance criterion is employed to further improve the performance of the GWO algorithm. Therefore, Equation (20) is weighted in each iteration and is redefined as: The weight of α, β and δ are denoted as w 1 , w 2 and w 3 . The weights should always satisfy w 1 ≥ w 2 ≥ w 3 . Mathematically, the weight of α is changed from 1 to 1/3 during the searching procedure. At the same time, the weights of the β and δ is increased to 1/3 from 0. The complete flow chart of MGWO is depicted in Figure 7.

Application of SHE using MGWO in the proposed 17-level HMLI
The objective function f used for SHE in the proposed HMLI is given as subjected to where h s is the S th harmonic order.  Figure 8c. It can be concluded from Figure 8c that MGWO has a faster convergence rate as compared to GWO, PSO and GA for the same number of iterations and population size. Total harmonic distortion (%THD) of algorithms for different m a is calculated considering harmonics order up to 20 and are shown in Figure 8d. MGWO optimised HMLI gives lesser harmonic content as compared to other reported algorithms discussed in this work. The fitness value and the rate of convergence of all algorithms are compared and given in Table 3. The convergence rate and fitness value of MGWO are better than GA, PSO and GWO.

CAPACITOR CALCULATION
To calculate capacitances, the charge-discharge cycle of each capacitor is considered [16]. For demonstration, the largest discharge period is calculated for C 1 . The largest discharge interval and the corresponding currents through resistive load R L for these intervals are calculated to define total charge and are given in Table 4. The maximum discharging value Q C 1 of capacitor C 1 is calculated based on discharge cycles and is given as: Similarly, the maximum discharging values Q C 2 , Q C 3 and Q C 4 of the capacitors C 2 , C 3 and C 4 can be obtained. The maximum allowable voltage ripples across the capacitor C i is kV C i (i = 1, 2, 3 and 4), where k is the ripple factor. Using the derived values of Q C 1 , Q C 2 and Q C 3 , the values of capacitors C 1 , C 2 , C 3 and C 4 are obtained as: The function of load current, I L (t) for R-L loading condition is derived [16] as: here I max is maximum load current and is phase difference. The capacitances for inductive load are given as: DC (31) For voltage ripple k = 0.05 and 0.1, the optimal capacitor values can be determined from Equations (29)- (31). The capacitor values are inversely varying with ripple factor and output frequency. The variations of C 1 , C 2 , C 3 and C 4 for several ranges of load values are depicted in Figure 9a to validate the effect of  load resistance on optimum capacitance. The optimum capacitor values are also determined for different values of phase angle as shown in Figure 9b.

COMPARISON WITH REPORTED HMLIs
The proposed 17-level HMLI is compared with recently reported MLIs. The proposed HMLI is compared in terms of active and passive components, PIV and TBV to exhibit its merits as given in Table 5. It can be observed from Table 5 that the proposed HMLI requires a lesser number of capacitors to achieve 17-level output voltage as compared to other HMLIs. Topologies [15], [16], [17], [22], [24] and [25] utilise almost twice the number of capacitors compared to the proposed topology for the same number of voltage levels attained. The number of capacitors in [13] and [14] is also very high to generate 17-level voltage levels. However, the proposed HMLI requires a lesser number of power devices as compared to others as given in Table 5. The topology [14] requires zero number of diodes but the number of capacitors is very high. Topology presented in [17], [24] and [15] possess larger TBV for obtaining a higher number of levels whereas topologies [15] and [25] need more diodes to generate the same output voltage levels. While topology [28] has lower PIV and the number of capacitors for generating a similar number of output voltage levels as HMLI, it has very limited boosting capacity with the maximum boosting possible as two and uses a higher number of switching devices than HMLI.

EXPERIMENTAL VERIFICATION
In order to validate the performance of the proposed 17-level HMLI, a 550 W laboratory prototype is developed as shown in Figure 10 and the required components are given in Table 6. The dc source voltage is taken as 60 V and the experimentation is carried out using TI-TMS320F28335 DSP processor.   mately 2200, 2600, 2600 and 1500 μF, respectively. The output voltage V 0 and current I 0 experimental waveforms of the proposed 17-level HMLI for a resistive load (R = 45 Ω) are shown in Figure 10a. The measured rms values of output voltage and current are 158.43 V and 3.47 A, respectively. The topology is also tested for R-L load (R = 45 Ω, L = 90 mH) at input voltage 60 V. The output voltage V 0 and current I 0 are depicted in Figure 10b and measured as 158 V and 3.09 A, respectively. The harmonic spectrum of the V 0 is depicted in Figure 10c and %THD is measured as 7.14%. The magnitude of lower order harmonics at m a 0.7 for GA PSO, GWO and MGWO are given in Table 7. It can be noticed that magnitude of lower order harmonics in the output voltage of HMLI has been reduced significantly using MGWO technique as compared to other reported algorithms.
The capacitor voltages are shown in Figure 11. It can be observed that capacitor voltages V C1 , V C2 , V C3 and V C4 are balanced at 56.5, 57.1, 56.2 and 27.5 V, respectively. The voltage of capacitors is inherently self-balanced in the proposed HMLI. Capacitor ripples ΔV C1 , ΔV C2 , ΔV C3 and ΔV C4 across the four capacitors are 5.4, 5.1, 4.8 and 2.6 V, respectively.

Dynamic performance of the proposed HMLI
In order to verify the dynamic performance of the proposed HMLI, the load resistance is step changed from 45 to 90 Ω. The load current is step changed from 3.4 to 1.6 A for variation in resistance as depicted in Figure 12. It can be noticed that the output voltage does not have any significant effect for the change in load resistance. Therefore, the inherent capacitator voltage balance is confirmed in the 17-level proposed HMLI.

Efficiency calculation
In order to calculate the efficiency of HMLI, V in (input voltage), I in (input current), V 0 and I o for R load (R = 45 Ω) are measured experimentally from Figure 13. The calculated

CONCLUSION
A 17-level HMLI using a reduced number of circuit components is proposed in this paper. TBV of the proposed HMLI is low, thus enabling utilisation of lower-rated switches for higher power level applications. The proposed topology has reverse current carrying capability. Output voltage levels higher than 17 can also be obtained using the extended structure of the proposed HMLI. Capacitor voltages are inherently balanced in the proposed HMLI, thus it eliminates the requirement of any external capacitor balancing circuit. MGWO algorithm has been used to obtain optimal switching angles of HMLI by solving non-linear transcendental equations in this work. MGWO gives superior performance in terms of harmonic content, convergence speed and fitness value as compared to GA, PSO and GWO due to its improved local optima and ability to balance between exploration and exploitation. In order to verify the effectiveness of the proposed HMLI, a 550 W laboratory prototype has been developed and the obtained experimental results verify the precision of the proposed work.

APPENDIX
The mathematical voltage balance of capacitor C 4 is derived below. The output voltage and current are assumed to have half-wave symmetry. The average current through C 4 for load resistance as R is given as follows: where I + C and I − C are current flow through capacitor (C 4 ) in both the half cycle of output voltage. The total charge Q delivered/absorbed over a period T is calculated as follows: .T + I C , 5V dc 2 + .