Design and analysis of a novel AC-side power decoupling circuit

A large amount of second (2 ω ) ripple power are coupled on the DC bus of a single-phase inverter due to the output pulsating power. In this paper, a novel AC-side power decoupling circuit (APDC) based on buck-boost is proposed for a single-phase inverter. The circuit is connected in parallel with the AC side of the inverter to realise the local decoupling of the pulsating power on the AC side. The working principle of APDC is elaborated and the switching sequence of APDC is derived. The corresponding pulse energy modulation (PEM) control strategy is designed to precisely control the decoupled power. The feasibility and superiority of the proposed APDC together with the PEM control strategy are ﬁnally veriﬁed by both the simulation and experimental results obtained on a 200 W single-phase inverter. The results show that 2 ω -ripple power of the system can be effectively buffered and the capacitor capacity in the inverter system is greatly reduced.


INTRODUCTION
The two-stage single-phase inverter is composed of the frontend DC/DC converter and the backward DC/AC converter, which is widely used in photovoltaic (PV) system, fuel cell generator, marine power system, UPS and other distribution systems. A pulsating instantaneous power exits on the AC side of a single-phase AC load as produced by the sinusoidal voltage and current. The pulsating power creates a 2ω-ripple on DC voltage or current. In the fuel cell and DC microgrid system, the 2ω-ripple current will reduce their lifetime and efficiency. The traditional solution is to connect large electrolytic capacitors (E-caps) on the DC bus to absorb the 2ω-ripple power. In this way, the E-caps containing 2ω-ripple voltage will shorten the lifetime and reduce the reliability of the system. Therefore, it is significant to reduce the influence of the 2ω-ripple power in a single-phase inverter. Therefore, several research works have been carried out and some different solutions are put forward in recent years. In general, they can be divided into two categories. One is to optimise the decoupling control strategy in the present two-stage inverters. The other is to propose a novel inverter topology. With regard to control strategy, reference [1] proposes that increasing the voltage loop gain of the front-end DC-DC converter at 2f o could reduce 2ω-ripple current. To satisfy this requirement, proportion integration (PI) regulator plus inductor cur-This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology rent feedback is employed to achieve the high bandwidth of the voltage loop. In [2], a control strategy is presented based on the front-end load current feedforward. It intends to control the DC bus voltage to swing properly, making the DC bus capacitor supply all the pulsating power nearly. In [3], a basic approach is proposed from the perspective of the output impedance. It indicates that the output impedance of the front-end DC-DC converter should be designed relatively high at twice the output voltage frequency (2ω) while relatively low at other frequencies.
In [4], a closed-form solution is derived to calculate the amplitude of the ripple-caused harmonics. In [5], an observer-pattern modelling method is proposed to eliminate the time-variance effect from both fundamental components in the load-stage and 2ω-ripple in the source-stage. In [6], an adaptive sliding mode control strategy for a two-stage converter to reduce 2ω-ripple is proposed. Adopting the above control methods, 2ω-ripple current in the front-end DC/DC system can be properly suppressed. However, the 2ω-ripple power is introduced into large E-caps on DC bus, so the value of E-caps is still quite large. When the value of E-caps increases to a certain value, the ability to absorb 2ω-ripple power is limited. In addition, large Ecaps have some inherent disadvantages, such as short life, large volume [7][8][9][10], and so on. Using film capacitors to absorb 2ωripple power has become a hot topic.
The second scheme is to reform traditional two-stage inverters. The DC/DC converter adopts a high-frequency (HF) transformer, which has the advantages of input-side and output-side being electrical isolation. In [11], a three-port PV micro-inverter is proposed with the strategy of current decoupling instead of power decoupling. In this way, the current decoupling tank can buffer the current difference between the PV panel and the AC grid current. On the basis of a conventional flyback inverter, a modified micro-inverter [12] is derived by incorporating another transformer winding and a power decoupling circuit. This three-switch inverter can extract maximum power from PV, deliver a sinusoidal current to the grid, and compensate for the unbalanced power. In [13,14], a conventional four-switch flyback-based inverter is turned into an inverter equipped with a series power decoupling circuit. The modified inverter has an inherent snubber circuit, which can restore the energy of the transformer leakage inductance and improves its overall efficiency. These two-stage inverters can step up the voltage using a transformer. In this way, the system needs to use the transformer. However, it is more advantageous to eliminate the transformer because this would reduce the production cost and size and increase power efficiency. Therefore, two-stage transformerless inverters have become a typical object of study as a grid-connected inverter circuit configuration [15].
The DC/AC topology containing decoupling ability has always been a research hotspot. Single-phase differential mode boost inverter [16][17][18][19] and single-phase differential mode buck inverter [8,20] are new inverters developed in recent years. The decoupling method of differential mode power transfer is adopted. In this way, the secondary current harmonics on the DC side can be suppressed without additional switching devices. However, it imports the fourth current harmonics inevitably. Most fatally, the decoupling scheme is actually limited to low power applications.
In addition, some scholars propose active decoupling circuits to divert the pulsating power into decoupling capacitors by controlling the capacitor voltages. In [21][22][23][24][25][26], the decoupling circuit is connected in parallel with the bus capacitor, and the corresponding active damping method is proposed. Adopting these schemes, the decoupling capacitors are still large. In [27], a variety of DC-side decoupling circuits are compared, and an adaptive decoupling voltage control method is proposed to test the optimal DC-side decoupling circuit.
Based on present active power decoupling schemes, this paper studied the parallel decoupling circuit on the ac side of the inverter. By controlling the pulsating power on the AC side and realising the local decoupling of the 2ω-ripple power on AC side, the transmission loop of 2ω-ripple power in the system can be shortened and the energy loss on the DC side can be reduced. In addition, AC-side power decoupling circuit (APDC) and two-stage inverter are independent of each other, which reduces the complexity of the system and is conducive to the transformation of traditional inverter equipment.
In this paper, an APDC based on buck-boost mode is proposed. First, the output characteristics of the AC side of the inverter are analysed. The energy flow loop is designed when the two-stage inverter and APDC work together. The PEM control

POWER COUPLING RELATIONSHIP OF INVERTER
In a single-phase inverter, u g (t) and i g (t) are the AC voltage and current, which are given by where U g and I g are the rms values of u g (t) and i g (t), respectively, ω is the angular frequency, and φ is the phase factor angle. For pure resistive load R, φ = 0, the instantaneous AC-side power P ac (t) is given by P n is the nominal output power of the inverter, which is obtained as Let P d (t) = P n -P ac (t), whose expression is P d (t) is 2ω-ripple power of the system and also the power to be decoupled. Let T = 2π/ω, f = 1/T, T and f are the angular frequency period and frequency of u g (t). Let P d (t) =0, in (0, T), we get t = T/8, 3T/8, 5T/8, 7T/8. The polarity of u g (t) and P d (t) is combined. One working cycle of the inverter can be divided into four modes as shown inTable 2. The Interval distribution of modes is shown in Table 3. Figure 1 shows the distribution of modes I-IV in (0, T). The distribution of the four modes is I, II, I, III, IV and III in sequence, with the interval length ratio of 1:2:1:1:2:1. Modes I and III are divided into two sections in T, with the interval unit    Figure 2 shows the system structure of the two-stage inverter. Where U in and I b are the input voltage and current of DC/DC circuit, and U b is the voltage of bus capacitor C b . The inverter adopts a monopolar modulation strategy, whose switching period and switching frequency are T s and f s . U inv and I o are the output voltage and current before filtering. Based on modes I-IV of the inverter, the APDC is designed, which is composed of switch S 1 -S 6 , decoupling capacitance C d FIGURE 2 Two-stage inverter system and decoupling inductance L d as shown in the blue shadow of Figure 2. U Cd is the voltage of C d , and i Ld is the current flowing through L d . The switching period and frequency of APDC are T s and f s , respectively. In (0, T), APDC can also be divided into modes I-IV, corresponding to the inverter.

Topology of six-switch APDC
APDC is connected in parallel with the AC side of the inverter, which adopts U inv as the input voltage to realise the local compensation of 2ω-ripple power on the AC side. When the inverter works in modes I and III, P d (t) > 0, P ac (t) > P av, the DC side delivers energy to APDC and load; when the inverter works in modes II and IV, P d (t) < 0, P ac (t) > P av , the DC side and APDC deliver energy to load together. In the switching period of modes I and III, U inv transfers energy to L d , then L d transfers energy to C d ; in modes II and IV, C d transfers energy to L d , then L d transfers energy to U inv . Therefore, L d is the bridge of energy interaction between the AC side and APDC. Through the precise control of the buffer energy on L d in the switching period, the instantaneous 2ω-ripple power can be decoupled. The following will analyse modes I-IV of APDC.   increases linearly from zero. u Cd keeps constant and U Cd0 is the initial voltage of C d . i Ld (t) and u Cd (t) can be given as Equation S 4 state changes from ON to OFF once i Ld (t) reaches peak current I Ld1 . I Ld1 can be written as Equation (6) In stage two, S 4 is OFF state, i Ld flow path is shown by the black dashed line. In this stage, i Ld decreases from I Ld1 to zero based on the resonance of L d and C d . u Cd can be obtained by Laplace inverse transformation according to the dynamic response analysis of the second-order circuit. The equations of u Cd (t) and i Ld (t) in stage two are expressed by 12 T s is the time when i Ld (t) decreases from I Ld1 to zero. From Equation (6), D 12 T s can be obtained as

Mode II
Mode II of APDC is shown in Figure 4. In mode I, U inv > 0 and P d < 0, S 3 is ON, S 1 , S 2 , S 4 and S 5 is OFF, and S 6 is the master switch controlled by the HF PWM signal. Mode II can also be divided into two stages shown by the red solid line and black dashed line, respectively. At this time, C d releases energy to the AC side and u Cd decreases. Since the inductance of L d is small and u Cd is high, i Ld rises linearly from zero to the peak current I Ld2 with the slope of U inv /L d in stage one. D 21 T s is the turn-on time of S 6 and the D 22 T s is the time when i Ld decreases from I Ld2 to zero. The decreasing process of i Ld is LC resonance, which is the same as mode I as shown in Figure 3.

Modes III/IV
When U inv < 0 and P d > 0, the APDC works on mode III, which is shown in Figure 4. In this mode, S 2 is ON. S 1 , S 4 -S 6 are OFF, and S 3 is the master switch. C d absorbs energy and u Cd rises. When U inv < 0 and P d < 0, the APDC works in mode IV, which

Time sequence of APDC
It can be seen from the analysis of mode I-IV that the switching state is determined by the magnitude of P d , the polarity of U inv and P d . The switch state table of S 1 -S 6 can be obtained as shown in Table 4.
In Table 4, '0′ indicates the switch is OFF and '1′ indicates the switch is ON. '1/0′ indicates that the switch is the master switch driven by the HF PWM control signal. 'A' and 'B' indicates the polarity of u g and P d .
According to Table 4, the logic expression of the switch state can be deduced as follows: Therefore, the driving signals of S 1 -S 6 are obtained as shown in Figure 7. The time-domain distribution of S 1 -S 6 is based on the distribution of modes I-IV, which is divided into LF constant duty cycle signal and HF PWM signal. The LF signal is used as the auxiliary signal and the HF signal controls P d . In each working mode, the HF and LF signals work together to control the corresponding switches. With the switching of working mode, the HF and LF signals are switched to the other two switches, respectively.

PEM control strategy
APDC is in parallel with the two-stage inverter, so their control system design can be carried out independently. The inverter adopts a unipolar SPWM modulation strategy. This section mainly discusses the control strategy of APDC.
From Figure 6, it can be seen that P d is controlled by HF PWM signal. D(n) is the duty cycle of the PWM signal determined by the decoupled energy W(n) in the carrier period. This paper names it as pulse energy modulation (PEM) control strategy.
According to Equation (4), in the nth switching period [(n -1)T s ∼ nT s ], the energy needed to be buffered is where f s is switching frequency, f is the frequency of u g (t). According to Equation (10), the system needs to sample u g (t) and i g (t) to obtain instantaneous decoupling power P d (t). Also, W(n) is related to the output power P n of the inverter in the carrier period but not to the control of the previous DC/DC circuit. At the same time, W(n) satisfies the energy formula of L d : i dref is the given value of the peak current of i Ld . When i Ld rises to i dref , the transfer of decoupling energy to L d is completed. i dref can be Subsequently, the discrete distribution of i dref in [0, T] and its envelope i dv can be obtained as shown in Figure 8. According to the fitted curve i dv , the theoretical waveform of i Ld could be obtained, which is shown in Figure 9. i Ld flows in the positive direction in modes I and IV while flowing in negative direction in modes II and III. According to Table 2, P d decreases in [0∼T/8], so does i dv . In [T/8∼3T/8], i dv increases first and then decreases along with P d . The variable tendency of the peak value of i Ld in the rest time interval is the same as above. In the partial enlarged diagram of i Ld in modes II and I, it can be seen that i Ld rises linearly from zero to the peak current. After that, i Ld decreases to zero along the curve of slope reduction under the resonation of L d and C d .
When APDC absorbs energy from the two-stage inverter in stage one of modes I and III, U b is equal to the voltage of L d .
By substituting Equations (12) into (13), D(n) can be obtained as Since the working range of modes I and III are ( When APDC delivers energy to the two-stage inverter in stage one of modes II and IV, U b is equal to the voltage of L d . i dref (n) satisfies By substituting Equations (11) into (15), D(n) can be obtained: Since the working ranges of modes II and IV are (T/8,3T/8), (5T/8,7T/8), the value range of integer n is n ∈ Subsequently, the duty of the PEM signal is related to U b in charging and it is related to U Cd in discharging process. It is necessary to sample U b and U Cd in order to calculate the duty of PEM more accurately.
where U H and U L are the peak value and valley value of u Cd . ΔU is the peak-to-peak value of 2ω-ripple voltage coupled on u Cd . U av is the given value of DC bias on u Cd . With the inverter working in the frequency conversion situation, the relationship between ΔU and f can be obtained: Thus, △U is inversely proportional to f when nominal power P n and the given value U av are set as constant.

SIMULATION VERIFICATION
In order to verify the APDC and its control strategy in this paper, a simulation platform of the two-stage inverter with the APDC is built in Matlab. The inverter adopts unipolar sine pulse width modulation (SPWM) modulation, and the APDC adopts the PEM control strategy. The simulation parameters of the circuit are shown in Table 5. Figure 10 shows the simulation waveform of i Ld and u Cd when APDC puts into operation at 0.2 s. As can be seen From

FIGURE 10
Performance index of decoupling circuit Figure 10, the maximum peak value of i Ld is 25 A in the charging process and 22 A in the discharging process. The average value of u Cd is 650 V, and 100 Hz pulsation component is coupled on C d , and the pulsation range of u Cd is 582-714 V. Figure 11 shows the simulation waveform of U inv and u g . The HF pulse sequence of U inv shows a large swing, and the waveform of u g is distorted before 0.2 s. With APDC running, the HF pulse sequence of U inv is flat, and the waveform quality of u g is improved.
It can be seen from Figure 12 that u g is coupled with 150 Hz LF ripple components when APDC not running. At this time, the THD of u g is 5.49%, and the third harmonic content is 5.47%. The coupling of a large number of LF harmonic components makes u g seriously distorted. With the APDC running, the third harmonic is effectively suppressed. At this time, the third harmonic component is 0.93%, and the quality of u g is improved.

FIGURE 11
Influence of decoupled circuit on AC side  Figure 13 shows the simulation waveform of U b and I b . The average value of U b is 400 V and the variation range of U b is 314-480 V. The swing amplitude of twice frequency component is 166 V, which makes up a relatively significant share (30%) of U b when t < 0.2 s. When the APDC puts into operation, the average value of U b is about 400 V, and the variation range of U b is 394.8-405.2 V. The amplitude of the second harmonic component is 10.4 V, which is equal to 2.6% of U b . It can be seen that the average value of I b , which is DC-input current is 5.5 A. I b is also coupled with the second harmonic current component when t < 0.2 s. The current swing of I b is 2.8 A. When the APDC puts into operation, the second harmonic current swing is reduced to 0.7 A. Figure 14 shows the fast fourier transformation (FFT) analysis of input current. It can be seen that I b is coupled with 100 Hz LF ripple component when the APDC not running, and the second harmonic content is 24.05%. With the APDC running, the 100 Hz ripple component is effectively suppressed and the second harmonic content of U b decreases to 1.73%.   The simulation results prove that the proposed six-switch APDC can buffer the unbalance of instant power of DC/AC side and suppress twice the frequency component of U b and I b .

EXPERIMENTAL VERIFICATION
In order to verify the effectiveness of APDC and its PEM control strategy, an experimental platform is built as shown in Figure 15. The main hardware experiment parameters of the system are shown in Table 6.

Experiment with E-caps
Traditional micro-inverter uses large-capacity E-caps to suppress the second-order ripple power on the DC side. Then, the micro-inverter experiment is carried out with a 220 µF Ecap selected for C b . The experimental platform is shown in Figure 15. The experimental parameters are shown in Table 6.
The experimental results of 220 µF E-cap are shown in Figure 16. It can be seen that the ripple range of U b is about 8 V.

Experiment with APDC
The experiment of the novel inverter with APDC is carried out on the experimental platform of Figure 15 and the experimental parameters of Table 4. A 20 µF film capacitor is selected for C b . Figure 17 is the timing sequence of the driving signals for six switches in APDC. It can be seen that the relationship between the timing sequence of the driving signals is consistent with the theoretical analysis in Figure 7. Figure 18 shows the experimental waveforms of i Ld . It can be seen that the relationship between i Ld and U inv is consistent with the simulation results shown in Figure 10 and the principle analyses shown in Figure 9. In [0, T], the distribution of the four modes is I, II, I, III, IV, III in turn and the proportion of the interval length is 1:2:1:1:2:1. i Ld flows forward in modes I/IV and reverse in modes II/III. In the partial enlarged drawing of i Ld in modes I and II, it can be seen from the figure that in the carrier period T s, i Ld rises linearly from zero to peak value, and the charging speed of i Ld is constant. Once the peak current reached, i Ld drops to zero along the curve. The slope of the decline process decreases gradually and the discharge speed of i Ld slows down. The charging and discharging process of i Ld is controlled in the carrier period. The initial value of i Ld in each carrier interval is zero so as to control energy in the carrier unit. Figure 19 shows the experimental waveforms of i Ld and u Cd . As can be seen, the peak current of i Ld in starting process is greater than that in the stable process in modes I/III. The peak current of i Ld in starting process is less than that in stable process modes II/IV. Therefore, the energy absorbed by C d is greater than the energy released, so the average voltage of C d increases. After several working cycles of the inverter, the average value of u Cd is 150 V, and the voltage fluctuation amplitude is 130-178 V. The amplitude of the second ripple on C d is 48 V and the frequency is 100 Hz. Figure 20 shows the experimental waveforms of U b , i Ld , U inv and u g . It can be observed that the HF pulse sequence of U inv indicates large amplitude and u g is distorted when APDC not running. Meanwhile, the average value of U b is 108 V, the fluctuation range is 92-128 V, and the secondary ripple swing is 36 V and accounts for 33.3% of the DC component.
With APDC running, the HF pulse sequence of U inv is straight. The waveform quality of u g is improved, which is close to the sine wave. The average value of U b is 100 V, and the fluctuation range of U b is 96-104 V. The secondary ripple swing is 8 V and accounts for 8% of the DC component. Therefore, the swing of U b decreases by 77.8% (from 36 to 8 V). The waveform quality of the novel micro-inverter with 20 µF capacitor film is equivalent to the traditional micro-inverter with a 220 µF E-cap. Figure 21 shows the experimental results of the dynamic characteristics of APDC. The waveforms from top to bottom are i g and u g , u Cd , i Ld . When the load changes from 50 to 25 Ω, u g remains constant basically, i g increases from 0.8 to 1.6 A, and P ac is doubled. With the increase of P ac , the peak value of the i Ld in modes I-IV is higher than before. When the load is 50 Ω, the swing amplitude of the u Cd is 138-158 V; when the load is 25 Ω, the swing amplitude of u Cd is 115-155 V and the decoupling energy of C d increases. Therefore, the instantaneous decoupled power of APDC can track the output power of the inverter in time. Figure 22 shows the frequency characteristic of APDC. When the frequency of u g is smoothly changed from 50 to 25 Hz, the duration of the four working intervals of the inverter changes accordingly. The decoupling inductance current in APDC can compensate the instantaneous decoupling energy in the variable working interval, so the duration of the four working modes of i Ld also changes accordingly. In addition, with the decrease in f, the frequency of the secondary voltage ripple on C d decreases and the peak-to-peak value of the secondary voltage ripple △U increases gradually. It can be seen that APDC can track the output frequency of u g in time to achieve accurate power decoupling. So APDC can be used in variable frequency drive.
The efficiency curve of the proposed inverter versus the output power is drawn in Figure 23. The efficiency is calculated by dividing the inverter output power by its input power. Input and output powers are obtained by multiplying voltage and current values that are measured by a digital multimeter. The efficiency continuously increases as the output power increases. The inverter losses include switching, conduction, and core losses.
Based on the above experimental results, it can be seen that the low capacitance film capacitor connected to the two-stage inverter system as the bus capacitance will cause the distortion of the output voltage waveform at the ac side and increase the secondary ripple amplitude at the DC side. APDC can effectively suppress the secondary ripple component on the DC side and improve the distortion of the output voltage waveform caused by the low capacitance film capacitor.

CONCLUSION
In this paper, an APDC and corresponding PEM control strategy are proposed. The circuit is connected in parallel with the AC side of the inverter, which can effectively absorb the 2ωpower ripple in the system. Through the verification of simulation and experimental platform, the following conclusions are drawn. For a 200 W experimental prototype, only 20 µF bus capacitor and 10 µF decoupling capacitor are needed to control the secondary ripple amplitude of bus voltage at about 8 V, which is equivalent to 220 µF E-cap. In the new scheme, the required bus capacitor per unit power is 0.4 µF/W. The PEM control strategy is adopted in APDC, which makes the decoupling of 2ω-power more accurate, simple and easy to realise. When APDC is put into operation, the suppression of 2ω-ripple of the bus voltage in two-inverter no longer depends on large E-caps, which prolongs the life of the inverter and reduces the volume of the system and increases the reliability of the system. However, the existence of semiconductor devices in the decoupling circuit will inevitably increase the cost of the system, so the switching devices in APDC should be further reduced in future research.

ACKNOWLEDGEMENT
This work is supported by the National Natural Science Foundation of China (grant no. 51467006), 'Study on micro-inverter without electrolytic capacitor based on power decoupling in AC side and its pulse energy modulation technique'.