A new boost switched capacitor seven-level grid-tied inverter

In this paper, a new switched capacitor-based multilevel inverter structure is suggested. The proposed topology can generate seven-level output voltage waveform using ten power electronic switches and two ﬂoating capacitors. This structure has the ability to boost the input DC voltage, up to 1.5 times. Although this topology can generate an output waveform with large number of levels, it does not increase the voltage stress on the power electronic switches. There is no need for capacitor voltage balancing in this structure since the capacitors are balanced through charging and discharging modes of operation. In addition, the suggested switched capacitor inverter reduces the number of input dc power supplies and uses a single dc source such as a photovoltaic (PV) panel. Since the proposed inverter is an neutral point clamp based multilevel inverter topology, the leakage current is minimized and as a result the overall efﬁciency of the proposed system is increased. The operation modes and steady-state analysis of the proposed structure are explained in detail. In order to validate the feasibility of the proposed topology, some experimental results are presented in the grid connected mode of operation.


INTRODUCTION
Multilevel inverters have been a popular division of inverters for power conversion systems since it has been introduced in early 80s [1]. Basically, the multilevel inverters can be classified to three categories of, cascaded H-bridge inverters (CHB), flying capacitors (FC) and neutral point clamped inverters (NPC). Multilevel inverters are more efficacious than the conventional two-level inverters in generating high voltages output using lower rating elements. These inverters by the way, have some drawbacks such as, the need for a greater number of power electronic switches and supply sources and complex control methods. Multilevel inverters generate a staircase output voltage waveform, similar to a sinusoidal waveform and has a higher power quality compared with conventional inverters [2][3][4]. Multilevel inverters have several merits, one of which is minimizing total harmonic distortion (THD) of the output voltage waveform which is performed without increasing the switching frequency or decreasing overall efficiency of the system. In multilevel inverter topologies, as the number of output voltage levels increase, the total harmonic distortion decreases. As the loads are getting more sensitive and the customers are getting more concerned about the quality of power, the power electronic devices should be prepared for the new conditions [5][6][7][8]. In simple, compared with the conventional bipolar inverters, multilevel inverters have lower amount of harmonics at the output voltage waveform and is one of the best solutions to improve the power quality of the inverters. Meanwhile, these kind of multilevel inverters have not prevented the interest of improved structures [2,9], that seek higher efficiency, an enhanced number of generated output voltage levels, and optimized number of circuit components. It is worth mentioning that multilevel inverter structures mentioned above also have some disadvantages such as high voltage stress on power switches, capacitor voltage imbalance, absence of voltage boosting feature, and requirement of multiple power dc supplies. The CHB well visible in the literate, is a superior structure with increasing popularity for high and medium power applications because of its modular structure. On the other hand, new modules have been suggested to translocate only the H-bridge module to produce more output voltage levels with lower number of power electronic switches and derivers [10]. Recently, a symmetrical five-level sub module has been recommended in [11], which can produce several dc voltage levels with less number of power switches across H-bridge. Nevertheless, the same number of galvanically isolated sources was needed as in a conventional CHB. Accordingly, some presented papers support utilizing of asymmetrical structures in order to decrease the number of input dc sources. To address this issue, in [12] a new 15-level structure that uses four unequal dc power supplies is suggested. A module combining two Ttype converters connected through four extra power switches, generating seven-level output voltage waveform is presented in [13]. Recently, several switched capacitor multilevel inverter topologies have been presented and attracted the attention of researchers [14][15][16][17]. This is due to their ability of boosting voltage by switching the utilized capacitors in series and parallel states with the input voltage dc sources instead of using a dc-dc boost converter or a bulky transformer. To maximize the output voltage level number, with lower count of power electronic elements, structures based on hybrid inverter have been presented. In hybrid structures, different conventional multilevel inverters are connected in series and parallel or cascaded connections. In general, the switched capacitor multilevel inverters use fewer number of circuit elements in comparison to conventional multilevel inverters. These topologies do not have the issues of capacitors voltage balancing through the periodically charging the capacitor to a reference value. This makes it possible to generate the higher number of output voltage levels using only one dc voltage input source. A new seven-level inverter structure with two asymmetrical dc power supplies has been suggested in [18]. This topology cannot guarantee the stability of the clamped capacitor voltage in steady-state and dynamic situations. A new single dc source cascaded seven-level inverter has been presented in [19], which needs complex control loops to balance the capacitors voltage is presented in. Another new structure of seven-level active neutral point clamped inverter has been presented in [20]. The disadvantage of this structure is that, it requires a large number of dc sources, to generate a higher number of output levels. Several modulation techniques such as carrier phase shift modulation, carrier disposition modulation, space vector modulation pulse width modulation (PWM) have been presented for multilevel inverter topologies [21,22]. Although space vector PWM method enhances the output power quality by increasing the number of output voltage levels, it increases the number of basic vector. The increase in number of basic vectors, adds to the control complexity through introducing redundant switching states, which is not appropriate for seven-level inverters. The phase opposition disposition modulation technique is utilized in [23] to improve the operation of seven-level active neutral point clamped inverter. To have the modulation on mixed cascaded seven-level inverter, the SPWM technique with a single carrier is presented in [24]. In order to produce the gate pulse of the utilized power switches, two reference signals with opposite magnitude values are utilized in [25]. The total harmonic distortion (THD) of the output voltage waveform is lower and therefore the quality of output voltage waveform is higher, however the efficiency of the inverter is low. Recently, switched capacitor based multilevel inverters with ability to boost voltage and self-voltage balancing have been recommended in [26,27]. These structures have two stages, combining a switched capacitor dc-dc converter with an H-bridge. Having the H-bridge in the structure, it present an inherent impropriety of cascaded multilevel inverters, i.e. the need for multiple isolated power dc supplies [14]. To overcome the mentioned disadvantage of multilevel inverters to have high voltage stress on the power electronic switches, in this paper a new multilevel inverter based on switched-capacitor topology is presented. This topology generates a seven-level output voltage waveform with voltage boosting capability having lower voltage stress across the power switches. The capacitor's voltage can be balanced without any complex control loop (with capability to self-balance the voltage). In order to produce a seven-level output voltage waveform, a single dc source is used in this structure. Rest of this paper is organized as follows; the proposed boost switched capacitor seven-level inverter is fully described in Section 2, and its operation modes are presented in Section 3. Ripple of utilized capacitor voltage is determined in Section 4. Section 5 carries out a comprehensive comparison of proposed topology with other structures. To validate the accurate performance of the proposed switched capacitor inverter, some experimental results are obtained when it is tied to grid and these results will be presented in Section 6 of this paper, last but not the least is the conclusion drawn in final section.

PROPOSED BOOST SWITCHED CAPACITOR SEVEN LEVEL INVERTER
The proposed switched capacitor inverter is shown in Figure 1, in which ten power electronics switches are used to control two floating capacitors C 1 and C 2 . It should be mentioned that all of the power switches are unidirectional expect switches S 5 and S 8 . The proposed structure can be applied to the photovoltaic systems where the PV panel is assumed as the input dc source of the inverter. It should be noted that the proposed inverter is based on NPC topology, thus the common mode voltage is limited to half of dc-link voltage. Therefore, the common mode voltage is fixed which leads to reduced leakage current. Regarding the mid-point of dc-link capacitors, Ideal seven-level output waveform the suggested inverter administers to produce seven levels of output voltages with levels of 0.5V dc ,

OPERATION MODES OF PROPOSED SEVEN-LEVEL INVERTER
In this section, the operation modes of the proposed topology are described in detail. The states of the switches S 1 to S 8 are presented in Table 1 and the ideal seven-level output voltage waveform is shown in Figure 2.
Regarding Figure 2, it can be seen that the capacitor C dc1 , is in the output current path and transfers the power to the output, therefore capacitor C dc1 , is being discharged during and capacitor C dc2 , is being charged in this positive half-cycle. During the negative half cycle, capacitor C dc2 , is in the output current path and transfers the power to the grid while in the output current path and transfers the power, therefore capacitor C dc1 , is being charged in this half-cycle. Considering the mentioned facts, the charging time for capacitor C dc1 and capacitor C dc2 is the same which leads to natural balancing of capacitors. Similar to what is explained for capacitors C dc1 and C dc2, from Figure 2, it can be seen that capacitors C 1 and C 2 are in the output current path for the same period of time. In other words, capacitor C 1, supports the generation of output voltages +V PV and +1.5V PV, in the positive half-cycle while capacitor C 2 is being utilized in the same half cycle and is and is in the output current path while generating +1.5V PV . As in the positive half-cycle, in the negative half-cycle, capacitor C 1 is utilized when generating −1.5V PV voltage and capacitor C 2 is being utilized for generating −V PV and −1.5V PV. So it is clear that the capacitors C 1 and C 2 are in the output current path for the same amount of time which leads to natural balancing of these capacitors. As a general note, it could be said that, since the operation of the circuit is symmetrical in the negative and positive halfcycle, the capacitor charging will be done in a balanced way naturally.
The equivalent electrical circuit of each operation mode is separately shown in Figures 3 and 4. In these figures, the blue and red paths indicate charging direction of the capacitors and injected current to power grid respectively. In this topology each utilized capacitors is charged to half of V PV . The operation modes of this topology are classified as follow.

First operation mode 0V PV
The equivalent circuit of this mode is indicated in Figure 3(a). Considering this figure, it can be understood that the switches S 1 , S 3 , S 5 and S 8 are in ON-state. Therefore, the output voltage of the proposed inverter is equal to zero (V out = 0). It should be noted that during this mode, the capacitors C 1 and C 2 are in parallel with the input dc power supply. Each floating capacitor is charged to half of the input dc power supply(V C1 = V C2 = V PV ∕2). This guarantees the selfbalancing of capacitors voltages. In this mode the switches S 2 , S 4 , S 6 , and S 7 are in OFFstate. The standing voltage of these switches can be obtained as follows: Also, in this mode the generated output voltage of the proposed switched capacitor inverter is equal to zero.

Second operation mode 0.5V PV
The electrical circuit of this mode is shown in Figure 3(b). In this mode, as in the previous mode, the capacitors are in parallel with the input source and are being charged to half of the input dc voltage (V C1 = V C2 = V PV ∕2) Considering Figure 3(b), it can be seen that, the switches S 1 , S 3 , S 5 and S 6 are in ON-state and the amplitude of generated output voltage level of the inverter is equal to 0.5V PV . In this mode, the switches S 2 , S 4 , S 7 , and S 8 are in OFF-state. The standing voltage of these switches can be calculated as follows:  this mode. So that the capacitor C dc1 and capacitor C 2 are connected in series and then discharged to the output. Therefore, the amplitude of produced out voltage level is equal to the sum of these mentioned capacitors voltage.  The standing voltage of switches can be achieved as: Figure 3(d) depicts the equivalent circuit of the fourth operation mode with the capacitor charging path and the path of injected current to the grid. In this mode, the switches S 1 , S 4 , S 6 are in ON-state. Under this condition, the capacitors C dc1 , C 1 , and C 2 are in series connection and the total energy of all three capacitors is transmitted to the output of the proposed inverter. In this mode, amplitude of the generated output voltage level is equal to 1.5V PV .

Fourth operation mode 1.5V pv
The standing voltage of switches can be obtained as:

Fifth operation mode −0.5V PV
The electrical circuit of this mode is shown in Figure 4(a), in which switches S 1 , S 3 , S 5 , and S 7 are in ON-state in order to generate first output level of output voltage waveform in the negative half cycle. When the switch S 1 , S 3 , and S 5 are in ONstate, the capacitors C 1 and C 2 are connected in parallel with the input dc source. Therefore, each of mentioned capacitor are charged to half of the input dc source(V C1 = V C2 = V PV ∕2). By turning on the switch S 5 and S 7 the energy of capacitor C dc2 is discharged to the output of the inverter through the current path which is shown in red. In this mode the first level of the negative half cycle is generated. Also, the switches S 2 , S 4 , S 6 , and S 8 are in OFF-state. Therefore, the standing voltage of these switches can be calculated as: Figure 4(b) shows the electrical circuit of this mode, which is to generate second level of output voltage waveform in the negative half cycle. This is achieved through switching the power switches S 2 , S 3 , and S 8 to ON-state. By turning on of the S 2 and S 3 , the capacitors C 1 and C dc2 are in series connection. Meanwhile, the switches S 1 , S 4 , S 5 , S 6 , and S 7 are turned off. The standing voltage of these switches can be written as follows:

CALCULATION OF CAPACITOR VOLTAGE RIPPLE
The grid current in the proposed structure is divided into two dc-link capacitors with the same capacitance. This will lead to have the same average voltage on the capacitors. Voltage ripple of the capacitors of dc-link (V ripple ) can be calculated as: Here, V C,dc,P is the peak voltage of the dc-link capacitors. Considering a sinusoidal grid current, the voltage ripple can be rewritten as follows: (23) where I P is the peak fundamental grid current. The capacitance of both utilized capacitors are the same.
In the other words, in order to calculate the voltage ripple of utilized capacitors C 1 and C 2 , longest continues discharging period of the utilized capacitors are considered. With respect to Figure 5, the integration of grid current from 2 to − 2 , electric charge flowing out from capacitor C 1 can be calculated as: Since the capacitor electric charge has a linear relation with capacitor voltage (Q = CV ), the voltage ripple equation can be written as follows: where, cos( ) indicates the power factor (PF). It should be noted that, the capacitance value of floating capacitors C 1 and C 2 are the same.

COMPARISION RESULTS
The proposed switched capacitor boost inverter is compared with most recent topologies and the summary of this comparison is presented in Table 2. This comparison is made in terms of number of generated output voltage levels, utilized power switches, diodes, floating capacitors, voltage boosting capability, and standing voltage of power switches. Multilevel inverter structures ensures low voltage stress on power electronic switches [26,33], with lack of voltage boosting capability. Considering Table 2, in all of the presented topologies, voltage stress on power switches is equal to V dc expect topologies [26,31,32]. Consequently, the proposed topology in this paper can offer benefits not only in voltage boosting capability, it also mitigates the standing voltage on the switches, thus improving the lifetime of the devices.

SIMULATION RESULTS
In this section, simulation results of MATLAB/Simulink are presented for the seven-level inverter, in this simulation, the peak input voltage magnitude is assumed to be 266 volts. Sevenlevel output voltage with a peak magnitude of 400 volts with sinusoidal grid injected current with unity power factor is presented in Figure 6(a). The proposed topology can also support the grid reactive power, therefore, grid injected current with output inverter voltage with different power factors are presented in Figure 6(b-d).
Voltage waveforms of capacitors C dc,1 , C dc,2 , C 1 , C 2 , are shown in Figure 7(a-d). Regarding the presented waveforms, it could be seen that the capacitor voltage is adjusted to half of the input voltage and the capacitor voltage ripples are in an acceptable range.
In addition, the voltage stress of the utilized switches S 1 -S 4 are presented in Figure 8(a-d), respectively. Also, the voltage stress of power switches S 5 -S 8 are indicated in Figure 9(a-d), respectively. Regarding the simulation results of voltage stress for switches S 5 and S 8 , it could be understood that the voltage stress on the mentioned switches is bipolar, so for the accurate operating of the proposed topology, switches S 5 and S 8 , should be composed of two back to back IGBTs.

EXPERIMENTAL RESULTS
Experimental results are presented to validate the performance of the proposed switched capacitor inverter. A photograph of the proposed inverter prototype is depicted in Figure 10. Details of used elements and prototype specifications are presented in Table 3. Since 2200¯F is a standard commercial capacitor, the voltage ripple for capacitors C dc1 and C dc2 could be calculated based on following equation: It is worth mentioning that in this equation, I P is the peak grid injected current and is equal to 5 A, therefore,

FIGURE 10
Laboratory prototype of the single phase grid tied proposed inverter used in the experiment So the voltage ripple for capacitors C dc1 and C dc2 could be calculated as 7.24 V, which is a reasonable value for the voltage ripple and could also be confirmed by the experimental results. Therefore, it could be said that 2200 µF is an appropriate value for the capacitors C dc1 and C dc2 .
In order to calculate the C 1 and C 2 capacitors value: Since 2200 µF is a standard commercial capacitor, the voltage ripple for capacitors C 1 and C 2 could be calculated based on following equation: So the voltage ripple for capacitors C 1 and C 2 could be calculated as 12.53 V which is a reasonable value for the voltage ripple and could also be confirmed by the experimental results. Therefore, it could be said that 2200¯F is an appropriate value for the capacitors C 1 and C 2 .
To verify the feasibility of the proposed inverter for gridconnected applications, experimental results are obtained in grid-connected operating mode. It is worth mentioning that the current control technique in [9,34,35] is used to generate the gate pulses of switches. In single-phase grid-connected inverters which are connected to a grid with 220 V RMS voltage, it is recommended for inverter to have an output of 360-400 V. Since in this topology, the inverter output will be 1.5 times of input voltage, in order to have a 400 V output voltage, the input voltage should be 266 V. The input dc power supply used in the tests has an amplitude of 266 V. The seven-level output voltage waveform of the inverter with a peak value of 400 V and a sinusoidal output grid-injected current at the unity power factor (PF = 1) are shown in Figure 11(a). Regarding this figure, the grid injected power could be calculated from below equation, (31) in which, V g,max and I g,max represent the maximum voltage and current of the grid, respectively, which are 220 √ 2V and 5 A for the proposed topology. Replacing the mentioned values in Equation (31), the grid injected power is calculated to be 0.77 kW. In order to verify the balanced voltage waveform of the utilized capacitors, the voltage across the capacitors C dc1 , C dc2 and C 1 , C 2 are presented in Figure 11(b) and 11(c) respectively. Considering this figure, it is clear that the capacitors have been balanced to half of input dc power supply value (V dc1 = V dc2 = 113 V, V C1 = V C2 = 113 V). Also, the voltage ripple of the utilized capacitors has an acceptable value.
The proposed inverter will also provide the reactive power support to the grid. In other words, the current injected to the

FIGURE 11
Experimental results: (a) Seven-level output voltage waveform of proposed inverter (200 V/div) and grid-injected current (5 A/div), (b) voltage across capacitors C dc1 and C dc2 (100 V/div), (c) capacitors C 1 and C 2 (100 V/div) grid can be in phase with grid (PF = 1), or under conditions of leading PF and lagging PF. Figure 12 shows the results of grid voltage and injected current from proposed inverter. Injected current under different power factors from unity power factor (PF = 1), to leading PF and lagging PF, are indicated in Figure 12(a-c) respectively. Meanwhile, the standing voltage waveform of used power switches (S 1 -S 8 ) are presented in Figure 13, in which Figure 13(a) shows the standing voltage of switches S 1 and S 2 . It is clear that the peak voltage stress across switch S 1 and S 2 is limited to only V PV . The voltage stress on the power switches S 3 and S 6 are indicated in Figure 13(b). With respect to this figure, it is clear that the peak value of standing voltage of mentioned switches are equal to V PV .
Also, standing voltages of power switches S 4 and S 5 are presented in Figure 13(c). The peak voltage stress across the switches S 4 and S 5 was limited to V PV . Figure 13(d) shows the standing voltage of switches S 7 and S 8 where the peak standing voltage value for these switches are equal to 0.5V PV . With respect to this figure, the peak value of standing voltage of used power switches is about 266 V. Therefore, the utilized power switches withstand only friction of peak value of output voltage  Figure 13(c).
The peak voltage stress across the switches S 4 and S 5 was limited to V PV . Figure 13(d) shows the standing voltage of switches S 7 and S 8 where the peak standing voltage value for these switches are equal to 0.5V PV . With respect to this figure, the peak value of standing voltage of used power switches is about 266 V. Therefore, the utilized power switches withstand only friction of peak value of output voltage waveform in their OFF-state mode.

FIGURE 13
The standing voltage of utilized power switches (100 V/div); (a) V S1 and V S2 , (b) V S3 and V S6 , (c) V S4 and V S5 , (d) V S7 and V S8 Finally, regarding presented experimental results, the accurate performance and feasibility of the recommended boost switched capacitor seven-level inverter for grid-connected applications is validated, which is also in good agreement with the provided mathematical analysis for the proposed topology.
Also, comparing the results confirms the similarity between simulation and experimental results.

CONCLUSION
In this paper, a new switched capacitor seven-level inverter topology with voltage boosting and reactive power support capabilities is presented. This structure combines the benefits of different multilevel inverter structures. The suggested switched capacitor inverter produces seven-level output voltage waveform using only ten power switches and two floating capacitors. The presented topology is grid connected with a significant drop in the leakage current thanks to the NPC topology. The peak value of output voltage is 1.5 times the input dc voltage which validates the boosting capability of the converter. One of the interesting features of proposed switched capacitor multilevel inverter is self-voltage balancing of floating capacitors and single power supply requirement. Moreover, design consideration and standing voltage calculations of the involved power switches have been discussed in this paper. Last but not the least, the feasibility and superiorities of the proposed switched capacitor inverter are compared with most recently introduced switched capacitor structures. Also, to verify the performance of the proposed inverter, experimental results are presented for the grid-connected mode of operation.