Modelling of GaN high electron mobility transistor on diamond substrate

On modelling of GaN high electron mobility transistor on diamond substrate Abstract A reliable small‐signal modelling approach has been developed and applied on GaN‐on‐ diamond high electron mobility transistor. The extrinsic elements' extraction procedure was improved to provide an accurate characterization for the quasistatic behaviour of the intrinsic transistor. The frequency independence of the intrinsic elements at active multibias condition has been considered as another objective in addition to measurements' fitting. Physical relevant values for the model elements have been obtained. The model accuracy was also validated by means of S‐parameters simulation, which showed a very good fitting of the measured data.

The main contribution of this study with respect to other studies is considering the quasistatic behaviour of the intrinsic transistor as a target through the extraction process. Under this quasistatic, the intrinsic elements are modelled as a function of bias voltages [35]. This means the values of the elements should be almost constant over the entire frequency range of operation (frequency independent). This condition is necessary for accurate bottom-up large-signal modelling of the same device [36]. The idea of considering the frequency-dependency of the intrinsic element as a criterion for extrinsic parameters extraction has been presented in [37]. It has been developed for simple lumped model of 13 elements and applied on small-size GaAs device. This study is contributing by improving the idea to be applied on distributed model of 20 elements. The study also demonstrates the proposed approach by using it for small-signal modelling of the recently developed GaNHEMT on the Dia substrate. Figure 1 presents epitaxial structure of the considered GaNon-DiaHEMTs. The devices are fabricated on 500 μm Dia substrates. From bottom to top, the epitaxial layers are constituted by 1 nmAlN nucleation layer, 2 μm Fe-doped GaN buffer, 20 nm AlGaN barrier layer and 2 nm GaN cap layer. The Al-mole is 0.3 nm in AlGaN barrier layer. The gate is designed by E-beam lithography. Gate-drain spacing (L gd ) and gate-source spacing (L gs ) are 2 μm and 1 μm, respectively. The gate finger width W g is 100 μm with gate number N g = 2. The gate length L is 0.25 μm. The GaN-on-Dia device is first fabricated on the epitaxial substrate (SiC) before removing from the original substrate and is bonded onto a high thermal-conductivity CVD polycrystalline Dia substrate [32]. The epitaxial structure and layout of the second GaN-on-SiC device is presented in Figure 1. More details about the device physics and characterization are reported in [34].

| EQUIVALENT CIRCUIT MODEL
As mentioned earlier, the investigated device is fabricated using the substrate transfer technology. One of the main disadvantages of this technique is the induced mechanical stress/tensile and wafer bow, which have stronger impact on the electrical properties of piezoelectric materials such as GaN [38]. The extra process on both sides of GaN buffer will affect the quality of subsequently grown epitaxial layers. This could also result into generating surface states and deep-level buffer traps, which affect the RF characteristics of GaN device [4]. This is illustrated in Figure 2(a), which presents the measured pinchoff S-parameters of GaN-on-SiC and GaN-on-Dia of the same gate width and almost the same structure. As can be seen, there is a significant difference in the RF characteristics of both devices. The buffer traps and surface states could also enhance gate and buffer leakage currents, which degrade the power efficiency of the device at high voltage and high frequency operation [39]. Figure 2(b) shows significantly higher values for the real part of the pinch-off Y-parameters at the gate side for GaN-on-Dia with respect to GaN-on-SiC. This could be attributed to extra parasitic leakage currents, which must be considered by the model and presents more pressure on the implemented extraction procedure. Reliable extraction and de-embedding of the parasitic elements are crucially needed for accurate characterization of the bias-dependence (quasistatic) of the intrinsic of the transistor.
The small-signal characteristics of the device are simulated by the equivalent circuit model in Figure 3. As mentioned, the extra surface process on this device could stimulate higher defect or imperfection-induced leakage current. This has been taken into account in the model by the gate-forward and gate-breakdown conductance, G gdf and G gsf . It has been found that these additional elements improve the model simulation (especially in the low frequency range) with respect to the adopted model in [32]. In this model, C pga and C pda represent the pad capacitances, while C pgi and C pdi account for interconnection-induced capacitances. With respect to the reported model in [32] and [33], the additional C pdi and C pgi will improve the model accuracy for characterizing the parasitic distributed effect at mm-wave frequency of operation.

| MODEL PARAMETERS EXTRACTION
The lower frequency measurements of the devices (see Figure 2(a)) confirm the asymmetrical capacitive behaviour in the gate and drain sides, and this will be considered in the extraction procedure. As can be seen in Figure 2, the high frequency measurements (>25 GHz) show higher ripple (uncertainty), which strongly impacts the reliability of extraction [40]. For that reason, the frequency range for extrinsic parameters extraction was restricted to 25 GHz for both investigated GaN-on-DiaHEMTs. This range of frequencies is enough and has provided reliable extraction results as will be presented.  The extrinsic parameters extraction is mainly based on cold S-parameters at pinch-off and unbiased conditions. This could be an advantage with respect to the commonly used conventional techniques that require extra forward stress measurements. In addition to these, extra measurements at typical bias conditions of class AB and class B mode are added. The frequency independence of the intrinsic parameters of the device, represents an indicator for the reliability of the extracted and the de-embedded extrinsic elements. The standard deviation of the active intrinsic elements could be added as another objective function to be minimized. The extraction procedure is based on two phases, initial value generation, and then optimal value determination. The full extraction process is summarized by the flow chart in Figure 4. The followed extraction procedure is an improved version for the reported one in [41]. Initially, the total capacitances (C gst , C dst and C gdt ) are extracted from the low frequency range of the measured pinch-off Y-parameters (see Figure 5(b)) of the device that can be modelled by the simplified equivalent circuits shown in Figure 5(a). In this case, the Y-parameters can be expressed as: It is clear that the total capacitances can be estimated from the measured Y-parameters by linear regression.
Then, a systematic searching is followed by scanning the outer-and inter-electrode capacitances. In this step, C pga and C pgi are assigned to incrementally increased values within the estimated total capacitances. For each assigned value of C pga and C pgi , C gs is calculated as: C gs ¼ C gst − C pga − C pgi . For each assigned value of C pga , C pda is assumed to have the same value of C pga and thus C pdi is calculated as: Typically, C ds is small under pinch-off and initially it could be observed in C pdi [41]. For our case, C gd ¼ C gdt . These parasitic capacitances are then de-embedded from unbiased (at V GS = 0 V and V DS = 0 V) measured Z-parameters (converted from S-parameters) and the series resistances and inductances are extracted from the de-embedded Z-parameters. Under this condition, there are no drain and gate currents and thus G gds , G gdf , G M and τ can be excluded. After removing the extrinsic capacitances, the equivalent circuit model will be reduced to that presented in Figure 6(a). Under unbiased condition, the channel will be symmetrically depleted around the gate metallization. Thus, the assumption of C gs ¼ C gd ¼ C g and [42]. At high frequency range (>10 GHz for our case), the gate capacitance C g bypasses the diode differential resistances [43] and also the F I G U R E 4 Flow chart for the extraction procedure of the extrinsic elements F I G U R E 5 Low frequency equivalent circuit and measured Yparameters with their linear fitting at pinch-off (V GS = −4 V and V DS = 0 V) for a 2 � 100-μm GaN-on-Dia HEMT 664impact of channel capacitance could be ignored [44]. Thus, the intrinsic π-network in Figure 3 could be represented by the simplified T-network in Figure 6(b) [42]. It is easy to prove that this T-network is equivalent to the actual intrinsic π-network. The T-network could be converted to the π-network shown in Figure 6(b) using the following formulas: where After substituting Z g ; Z d and Z s ; Equations (4) and (5) simplify to: These represent the impedances of the gate-source and gate-drain branches of the π-network in Figure 6(b), which has the same topology of the intrinsic part of our model in Figure 6(a). By substituting Z g ; Z d and Z s in Equation (6), the drain-source impedance is: The term ω � is much less than R ch and thus Z ds ≈ R ch ; which characterizes the drain-source resistance or conductance (G ds ) in the model of Figure 3. By representing the intrinsic part by the simplified T-network in Figure 6(b), Z-parameters of the unbiased device could be characterized by: Thus, the extrinsic inductances could be extracted from the slope of ωIm[Z ij ] versus ω 2 as shown in Figure 7. Im[Z ij ] represents the imaginary part of Z-parameters characterised by Equations (11) to (13). As illustrated also in Figure 7, the extrinsic resistances could be estimated from the real part of ωRe[Z ij ] versus ω 2 . F I G U R E 6 (a) Equivalent circuit model for the unbiased device after de-embedding the extrinsic capacitances and (b) simplified T and π equivalent circuits for the intrinsic of unbiased transistor at high frequency The other intrinsic elements are then extracted from the pinch-off intrinsic Y-parameters after removing the effect of the extrinsic parasitic elements (resistances, inductances and capacitances). The extracted model elements are then used to synthesis the S-parameters, which are then compared to the measured results to find the error, where and N is the total number of data points. δS is the difference between the measured S-parameter coefficient and its simulated value. The weighting factor (W) de-emphasises the data region with higher reflection coefficients due to the involved higher measurement uncertainty [41]. The scalar error is then expressed as: where defined at each frequency point n.
The same extracted extrinsic elements are de-embedded from measured active S-parameters to find the values of C gs , C gd and G m . Variation of these elements with frequency is measured by root-mean-square of their standard deviation as follows: σ ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi 1 3 where σ gs ; σ gd and σ gm are the standard deviations of C gs , C gd and G m ; respectively. This has been applied on all considered active S-parameters measurements, and the corresponding σ at each active bias condition is calculated. In our case, this was applied on S-parameters at typical bias conditions of class AB and class B mode to find their standard deviation of σ 1 and σ 2 . The fitting error ϵ r , which also represents the objective function in the optimization phase is defined as: ϵ r ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi where k 1 and k 2 are scaling factors to insure proper weighted summation for the error and the standard deviation. These steps are illustrated by the flow chart in Figure 4. The extrinsic elements are then fine-tuned, using a modified simplex-based optimization method [41], to fit the pinch-off S-parameters.
This extraction method has been applied on cold-pinch-off (at V GS = −4 V and V DS = 0 V) and unbiased (at V GS = 0 V and V DS = 0 V) S-parameters measurements of 2 � 100-μm GaN-on-Dia, 4 � 125-μm GaN-on-Dia and 4 � 50-μm GaN-on-SiC HEMTs. Table 1 lists the optimized values for the model elements at the pinch-off bias condition. As can be seen, the extrinsic elements values are reliable (nonzero values) to reflect the physics of the device.
As expected, the comparable values of pad capacitances C pga and C pda reflect the symmetrical pad contacts [44]. The model also simulates the expected enhancement in the interelectrode capacitances (C pgi and C pdi ) for GaN-on-SiC, which has higher number of fingers (4 � 50-μm) with respect to GaN-on-Dia (2 � 100-μm). R d and R s include the contact and access resistances. For all devices R d is larger, which could be attributed to the nonsymmetric access path (L gd and L gs spacing) in the drain and source sides. The GaN-on-Dia is also undergoing additional carrier wafer processing with respect to GaN-on-SiC. This extra process could change the surface condition of device and there might be some residual carrier wafer material on AlGaN after removal of carrier wafer. This, accordingly, may affect the quality of the contact resistance [45]. The effect of additional carrier wafer processing on the parasitic resistance is captured well by the model, which shows higher values of R d and R s for 2�100-μm GaN-on-Dia device than 4�50-μm GaN-on-SiC HEMT. R g is related to the gate width and number of fingers by [46]: where W is the total gate width, N F is the number of fingers and new and orig subscripts indicate the new and original scaled device, respectively. Both devices of 2�100-μm and 4�50-μm have the same gate width but GaN-on-SiC has higher number of fingers and according to Equation (1) this could justify the lower value of its R g (see Table 1). As expected, 4�125-μm GaN-on-Dia shows a higher value of R g with respect to 4�50-μm GaN-on-SiC. The values of extrinsic resistances for 4�125-μm and 2�100-μm are consistent with the expected reduction with gate width. The intrinsic capacitances are directly proportional to the total gate width and this could be observed from the values of C gs and C gd of all  -667 devices. The extracted values provide an excellent fitting with the measured pinch-off S-parameters as can be seen in Figures 8-10 for the considered devices.

| SMALL-SIGNAL MODELLING
The equivalent circuit model in Figure 1 can simulate the smallsignal characteristics of both devices over wide range of bias conditions. Under any active bias condition, initially, the extrinsic bias-independent elements are de-embedded from the corresponding S-parameters. Then the intrinsic elements are extracted directly by means of curve regression [41]. Figures 11-13, show curves of intrinsic elements versus frequency after de-embedding the extrinsic part for all the devices considered. As can be seen, the intrinsic elements show almost constant and frequency-independent values, which also validate the model topology for characterizing the parasitic elements and the reliability and accuracy of the extraction method.  Table 2 lists the extracted intrinsic elements at active bias condition in saturation region. As expected, GaN-on-Dia devices show a higher value for the transconductance G m and this is related to its better thermal characteristics with respect to GaN-on-SiC. The higher thermal conductivity of Dia substrate allows it to transfer the internally generated heat and cool down the intrinsic transistor. This accordingly, enhances the electron mobility and saturation velocity and thus improves the channel transconductance and of course Pout and gain of the device. This is consistent with reported results in [47], which demonstrates an achievement of a more than three times reduction in thermal resistance for GaN-on-Dia device with respect to GaN-on-SiC device. It was reported also that the thermally induced negative differential G ds , in the saturation region at DC measurements, is lower for GaN-on-Dia HEMT with respect to GaN-on-Si transistor [48]. That is to say, the self-heating is also affecting the output conductance [46]. Compared with GaN-on-SiC, GaN-on-Dia shows higher buffer trapping effect [4]. Thus, the reduced self-heating and higher trapping could justify the higher value of G ds for GaNon-Dia with respect to GaN-on-SiC device. The trapped charge in the buffer area also raises the intrinsic drain-source capacitance C ds , which shows larger value for GaN-on-Dia. C gs and C gd are almost the same for the GaN-on-Dia and GaN-on-SiC devices for the same total gate width.
The model accuracy has been also validated by means of S-parameters simulation at different active bias conditions. values for Ga-on-Dia due to its lower self-heating. As mentioned earlier, the self-heating also affects the output conductance and could be observed from the higher values of this element in the case of GaN-on-Dia [49]. The higher trapping of GaN-on-Dia also contributes to the higher value of G ds [50]. In the case of GaN-on-SiC of four fingers, air bridge connection is used to interconnect the sources. The effect of extra cross capacitances due to these connections is clear from the higher value of C gd in the case of GaN-on-SiC. Both devices show almost similar values of C gs . In general, the results show the typical expected behaviour of the device including the higher values of C gd and G ds near the triode region (V DS = 10 V).

| CONCLUSION
The results of this research show that GaN-on-Dia could be simulated with same reported equivalent circuit model of GaN-on-SiC. The main thing to be considered is the additional gate leakage current due to the extra substrate transfer process. The extraction results also show higher output/transconductance dispersion for GaN-on-Dia due to its higher lattice mismatch-induced buffer traps. The proposed modelling approach provides accurate and reliable results.