High-performance full adder architecture in quantum-dot cellular automata

: Quantum-dot cellular automata (QCA) is a new and promising computation paradigm, which can be a viable replacement for the complementary metal – oxide – semiconductor technology at nano-scale level. This technology provides a possible solution for improving the computation in various computational applications. Two QCA full adder architectures are presented and evaluated: a new and ef ﬁ cient 1-bit QCA full adder architecture and a 4-bit QCA ripple carry adder (RCA) architecture. The proposed architectures are simulated using QCADesigner tool version 2.0.1. These architectures are implemented with the coplanar crossover approach. The simulation results show that the proposed 1-bit QCA full adder and 4-bit QCA RCA architectures utilise 33 and 175 QCA cells, respectively. Our simulation results show that the proposed architectures outperform most results so far in the literature.


Introduction
The complementary metal-oxide-semiconductor (CMOS) technology has followed Moore's law [1].Therefore, it is essential that the number of transistors within the chips should be increased.On the other hand, continuation of this process has been very difficult by reducing transistor size.Since many problems such as quantum effects, short channel effects, and power dissipation have occurred when scaling comes down to submicron level.Quantum-dot cellular automata (QCA) is one of the top technologies, which can be attractive alternatives for CMOS technology [2][3][4].
The QCA was introduced by Lent in 1993 [2,3].The QCA technology is a new and promising alternative technology for the CMOS technology.This technology is introduced as one of the top emerging technologies with several potential advantages such as low-power dissipation, high device density, high switching speed, and pipelining [2][3][4].The QCA technology is based on the encoding of binary information in the charge reconfiguration in quantum-dot cells.The prime contribution on the QCA-based logic circuits have been developed by optimisation of the parameters such as layout complexity (cell count), effective area, and clock delay (number of clock zones) to achieve high efficiency and quality of the designs.Recently, several promising designs have been presented such as efficient QCA full adder designs [3,, flip-flops, and memory structures [36,40,41], efficient QCA multiplier designs [42,43], encoder/ decoder circuits [44], and efficient QCA multiplexer designs [19,45,46].
Full adder has a key role in many computational circuits design such as implementation of multiplier [35], and arithmetic logic unit [46].Up to now, many efforts have been made to improve the performance of the full adder in the QCA technology [3,.
This paper presents and evaluates two novel and efficient QCA full adder architectures: a new and efficient 1-bit QCA full adder architecture and a 4-bit QCA ripple carry adder (RCA) architecture.The main distinctive characteristics of our contribution are as follows: The simulation results show that our proposed QCA full adder architectures have advantages compared with other modified QCA full adder architectures.
The remainder of this paper is organised as follows: Section 2 presents a brief review of the QCA technology.In Section 3, the related works have been reviewed.The proposed QCA full adder architectures are presented and simulated in Section 4. Section 5 provides the simulation results of the proposed QCA full adder architectures.Section 6 evaluates the proposed architectures.Finally, the conclusion is provided in Section 7.

Review of QCA
The following section explains the basic QCA units such as wire crossing, inverter, and majority voter gate (MVG).

QCA overview
Fig. 1 shows two kinds of QCA cells.The structures of 90°and 45°Q CA cells can be seen in Figs.1a and c, respectively.As illustrated in Fig. 1b, a quantum cell can involve a set of four charge containers or dots located in the corners of a square.The cell contains two mobile electrons, which are allowed to tunnel between neighbouring sites [3].Computational power is provided by the Columbic interaction between QCA cells.It should be noted that only two stable configurations of the electron pair exist.The two possible polarisation states are P = +1 and P = −1, which represent logic '1' and logic '0', respectively.If we label the four dots from 1 to 4 according to Fig. 1b, and assign P i as the electron density of the ith dot, P, which shows the polarisation of cell, is given as follows: Electrostatic interaction between dots in cell i and each dot in cell j is given as follows [47]: where ɛ 0 is the permittivity of free space and ɛ r is the substance relative permittivity, which is the dielectric constant, q i shows charge of a dot at the ith cell, and |r i -r j | shows the distance between the two dots.On the basis of (2), charge of a dot can be either negative or positive according to electron attendance or lack in that dot [26].

QCA wires crossing
Owing to Columbic interactions and tunnelling effect among the QCA cells, a wire of the QCA cells can be made.A QCA wire consists of a number of the QCA cells, which can transmit the information from input to output.There are two types of wires in the QCA technology: (i) coplanar crossing wire and (ii) multilayer crossing wire.The coplanar crossing wire is implemented in a one layer, and this type of the wire consists of the vertical wire and horizontal wire [16].The vertical wire has been made by rotated cells (45°Q CA cells), whereas for multilayer crossing wire, it uses three layers for designing crossovers.

QCA gates
Basic logic elements in the QCA circuits are MVGs and inverter gate (IG) [2].The MVGs have three inputs, and one output, which can be classified into two categories: (i) original MVG (OMVG) and (ii) rotate MVG (RMVG).Figs.2a and b show the QCA layout of MVGs.Assume that the inputs are A, B, and C, the MVG performs following function: The 2-input AND and 2-input OR gates can be implemented using 3-input MVG by setting one of the three input cells to '0' or '1' [45].
Another fundamental gate in the QCA circuits is the IG, which is shown in Fig. 2c.

QCA clock
Clock in the QCA technology is different from clock pulse in the conventional CMOS technology [19].The clocking not only controls the data flow in the QCA circuits but also it is employed to achieve the required power for restoring the signal and reduce power dissipation, whereas the clock pulse only provided the synchronisation in the conventional CMOS circuits.On the other hand, the QCA clock consists of four zones.As is illustrated in Fig. 3, there is a 90°phase shift from one clock zone to the nextclock zone.In each clock zone, the clock pulse has four phases.In other words, the clock scheme has multi-phase in the QCA technology.Phase changes are as potential change and the clock phases include four states: switch, release, hold, and relax [18,40].
QCA cells begin unpolarised and their inter-dot potential barriers are low during the first clock phase, switch phase.Then, the barriers are raised during this phase and the QCA cells become polarised according to the state of their driver.The actual computation has occurred in this clock phase.At the end of this clock phase, barriers are high enough to repress electrons tunnelling.The cell states are also fixed.
During the second clock phase, hold phase, barriers are held high.As a result, the outputs of the sub-array can be used as inputs to the next stage.In the third clock phase, release phase, barriers are lowered and cells are allowed to relax to an unpolarised state.Finally, during the fourth clock phase, relax phase, cell barriers have remained lower and cells have remained in an unpolarised state.
A QCA circuit is divided into sub-arrays.This clocking scheme in the QCA technology gives permission for computing a sub-array, which offers the advantage of multi-phases clocking and pipelining for each sub-array.The clocking are inherently attractive pipeline and systolic computation.The number of phases in the critical path of the QCA circuit determines the overall delay [19,48].
It should be noted that four clocking zones are used here as follows: green indicates clock zone 0, violet indicates clock zone 1, blue indicates clock zone 2, and white indicates clock zone 3.

Related works
A 1-bit QCA full adder architecture is a basic block for multi-bit QCA full adder architectures.So, previous 1-bit full adders are reviewed in this section.
Lent and Tougaw [3] presented the first 1-bit QCA full adder.They utilised five 3-input MVGs and three IGs in their design.This architecture consists of 192 QCA cells covering an area of 20 μm 2 and it is constructed in one layer.
This architecture is not a suitable component for implementing larger QCA circuits.After that, several QCA full adders are developed .Fig. 4 shows these 1-bit QCA full adders.Tougaw [5] has also used a signal distribution network for implementation of 1-bit QCA full adder.This model is employed to minimise the required number of gates.
Wang et al. [21] have proposed 1-bit QCA full adder architecture, which consists of three 3-input MVGs and two IGs.Their design requires 142 QCA cells.
Zhang et al. [8] have proposed a QCA full adder, which is implemented using three 3-input MVGs and two IGs.This design con-tains145 QCA cells and occupies 0.17 μm 2 area.Moreover, they [6] have designed a QCA full adder architecture, which is implemented in three layers.The layout of this design has been presented in [10].This architecture requires 86 QCA cells and 0.5 μm 2 area.
Azghadi et al. [9] have proposed a QCA full adder, which consists of 5-input MVGs to design the QCA full adder for the first time in a primitive work.This architecture is implemented using a 5-input MVG, a 3-input MVG, and an IG.
Navi et al. [11] have improved the performance of the 1-bit QCA full adder architecture of [9].The QCA layout of this design consists of 61 QCA cells and 0.03 μm 2 area.Moreover, they [12] have proposed a new 5-input MVG.Then, the authors have implemented a 1-bit QCA full adder using this 5-input MVG, which is simple in terms of implementing digital functions.This QCA full adder architecture consists of 73 QCA cells and area of 0.05 μm 2 .
Hanninen and Takala [17] have offered a 1-bit QCA full adder, which utilised eight clock zones (two clock cycles).It consists of 102 QCA cells and area of 0.097 μm 2 .This structure also used to design QCA RCA, carry flow adder, and carry look-ahead adder.
A design of 1-bit QCA full adder was proposed in [24], which is utilised as a noise rejecting building block for the large arithmetic units.This design includes three 3-input MVGs and two IGs.It consists of 102 QCA cells and 0.097 μm 2 area and consumes eight Bishnoi et al. [20] have presented and implemented an RCA using 5-input MVG, which has eight clock zones (four clock cycles), and used 95 QCA cells with 0.087 μm 2 area.
Pudi and Sridharan [22,39] have presented a 1-bit QCA full adder using three 3-input MVGs and one IG which takes four clock zones (one clock cycle) for generating the SUM and C out .Moreover, they have proposed a 1-bit QCA full adder in [22], which consists of 79 QCA cells and 0.064 μm 2 .In addition, they have designed a modified bit-serial QCA full adder in [23].A single-layer QCA RCA is also designed using this 1-bit QCA full adder.
Hashemi et al. proposed two layouts for 1-bit QCA full adder in [13,14], respectively.They [13] introduced 1-bit QCA full adder, which is constructed in three layer.In [14], they proposed a robust one layer QCA full adder, which consists of 71 QCA cells covering an area of 0.06 μm 2 .
Kianpour et al. have developed a 1-bit QCA full adder architecture in [25].The proposed full adder based on MVG is implemented only in one layer.The cellular layout of this QCA full adder contains 69 QCA cells and 0.07 μm 2 area.Clock delay of this layout includes four QCA clock zones (one clock cycle).
In [27], Suresh and Ghosh have proposed a 2-input XOR gate.A 1-bit QCA full adder has designed using this XOR gate.The logical structure of this design includes only two XOR gates.This design consists of 124 QCA cells, area of 0.12 μm 2 , and it has six clock zones (1.5 clock cycles).
Roohi et al [15,16] have offered two types of multilayer architectures for 1-bit QCA full adder, which has been designed using 5-input MVG to reduce the number of cells as well as occupied area in the layouts.
A fault-tolerant full adder for QCA is presented by Farazkish [26].Works presented in [28] have proposed a methodology for 1-bit QCA full adder, which has used a 5-input MVG.Their architecture is constructed in three layers.Layout of this design includes 31 QCA cells and 0.02 μm 2 area.Moreover, they [29] have designed two types of 1-bit QCA full adder, which is implemented using 3-input conventional MVGs and 3-input reliable MVGs.
Labrado and Thapliyal [18] have designed single-layer QCA full adder, which has made up one 5-input MVG, one 3-input MVG, and one IG.Their QCA full adder consists of 63 QCA cells and 0.05 μm 2 area.It has been used three QCA clock zones (0.75 clock cycle).
In [7], Sasamal et al. has proposed a 5-input MVG, then they are implemented 1-bit QCA full adder using it.Layout of this design uses 49 QCA cells and its occupied area is 0.04 μm 2 .It has been used four clock zones (1 clock cycle) to achieve valid carry output and sum.
Mohammadi et al. [31] have proposed two multilayer architectures for 1-bit QCA full adder, which are implemented in three layers and five layers.The three-layer architecture consists of 38 QCA cells and 0.02 μm 2 area, whereas five-layer architecture consists of 47 QCA cells and 0.03 μm 2 area.The logical architecture of the proposed 1-bit QCA full adder in [31] includes three 3-input MVGs and one IG.

Proposed QCA full adder architectures
In this section, a novel and efficient architecture is presented and simulated for 1-bit QCA full adder.Then, a 4-bit QCA RCA is designed and simulated using this 1-bit QCA full adder as a module.Fig. 5 shows the proposed 1-bit QCA full adder architecture.
As specified in Fig. 5a, A and B are the two inputs and C in is the carry input.Two outputs are SUM and C out .The layout of the proposed 1-bit QCA full adder architecture contains 33 cells, and it takes two clock zones (0.5 clock cycle) to create the SUM and C out .It is implemented in one layer.
A 3-input RMVG is used for establishing the carry output.The outputs C out and SUM can be represented using a logical expression and a majority voter logical expression shown in ( 4) and (5).We need to optimise (5) in terms of the MVG.Using the MVG, the SUM function can be computed as follows: Here, the Maj defines the MVG.By combining ( 5) and ( 6), ( 7) can be proved.
The truth table of the full adder is listed in Table 1

Proposed 4-bit QCA RCA architecture
As it is illustrated in Fig. 6, the proposed 4-bit QCA RCA is implemented using four 1-bit QCA full adder modules, which have a simple and efficient structure.As it is observed in Fig. 6b, the data inputs are labelled as A0, A1, A2, A3, B0, B1, B2, B3, and C in .C in shows the carry input value and A0 and B0 show the least significant bits of the inputs.The outputs are S0-S3 and the carry out is shown as C out .
As it is shown in Fig. 6a, the proposed 4-bit QCA RCA architecture utilises 175 cells and it is implemented in one layer.It also takes four clock zones (one clock cycle) to create outputs SUM and C out .
In the 4-bit QCA RCA architecture, the output is determined after the carry is produced.Therefore, the most significant bit of the sum is only available after the carry signal has rippled through the adder from the least significant stage to the most significant stage as shown in Fig. 6b.As a result, the final sum and carry bits will be valid after a considerable delay.Critical path in the RCA is usually C in -C out .
5 Simulation results

Proposed 1-bit QCA full adder architecture
The proposed 1-bit QCA full adder architecture has been simulated using the QCADesigner version 2.0.1 [48] that is a simulation tool

Performance comparison
This section compares the proposed 1-bit QCA full adder and 4-bit QCA RCA architectures with the previous single/multilayer designs in [3, 5-20, 22, 24, 25, 27-38] in terms of layout complexity (cell count), effective area, and clock delay (number of clock zones).
In this table, delay is expressed in terms of the number of required clock cycles (×10 −12 s), area is expressed in terms of μm 2 , complexity is expressed in terms of the number of required cells, the ratio denotes the ratio of each parameter of 1-bit QCA full adder architecture of each reference in comparison with this parameter in the proposed 1-bit QCA full adder architecture, cell size is expressed in terms of (nm), and cost is computed for each reference using the following equation [18]: Here, area is expressed in terms of μm 2 and latency represents the number of required clock cycles (×10 −12 s).
As it is shown in Table 2 and Fig. 5, the layout of the proposed 1-bit QCA full adder architecture has minimum number of cells in comparisons with the pervious designs in [3, 5-15, 17-28, 30-38].The area of the proposed 1-bit QCA full adder consists of 0.02 μm 2 , which has been reduced compared with [3, 5-15, 17-28, 30-38].It should be noted that the 1-bit QCA full adder presented in [16,29] consumes less area compared with the proposed 1-bit QCA full adder architecture, it is because these designs [16,29] use the multilayer technique for implementation of 1-bit QCA full adder architecture, whereas the proposed layout is implemented in only single layer.The superiority of the proposed architectures in comparison with the pervious designs [16,29] is that the input cells and output cells are implemented in only one layer.
A comparative performance analysis of the proposed QCA RCA architecture with existing designs in [10,13,14,17,18,22,30,31,35,38] in terms of layout complexity (cell count), effective area, and clock delay (number of clock zones), which are obtained using QCADesigner, are given in Table 3.It should be noted that the available parameters in Table 3 is same as parameters of Table 2.
The results that are shown in Table 3 demonstrate that the proposed QCA RCA architecture provides considerable improvements in comparison with previous designs in [10,13,14,17,18,22,30,31,35,38] from the point of view of the layout complexity (cell count), effective area, and clock delay (number of clock zones).
On the basis of simulation results that are shown in Tables 2  and 3, the cost value of the proposed QCA full adder architectures has been reduced compared with the existing designs.In addition, the proposed QCA full adder architectures provide improvements in comparison with the other modified QCA full adder architectures in [3, 5-20, 22, 24, 25, 27-38] in terms of the layout complexity, effective area, and delay.In this paper, a novel and efficient single-layer 1-bit QCA full adder architecture was presented.The proposed 1-bit QCA full adder architecture was suitable for designing larger QCA adder units such as the RCA.We have implemented a 4-bit QCA RCA architecture using 1-bit QCA full adder module as its structural unit.The proposed QCA full adder architectures have been simulated using the QCADesigner version 2.0.1.The simulation results showed that the proposed QCA full adder architectures provide improvements in comparison with other modified QCA full adder architectures in [3, 5-20, 22, 24, 25, 27-39] in terms of the layout complexity, effective area, and delay.
(i) It presents a new and efficient 1-bit QCA full adder architecture as a basic logic module.(ii) It presents a new and efficient 4-bit QCA RCA architecture based on the proposed basic logic module.(iii) It simulates the proposed QCA full adder architectures on the QCADesigner version 2.0.1.

Fig. 5
Fig. 5 Proposed 1-bit QCA full adder architecture a Schematic logic diagram and block diagram b Layout of the QCA full adder

Fig. 6
Fig. 6 Proposed 4-bit QCA RCA architecture a Layout of the adder b Schematic logic diagram and block diagram

Fig. 7
Fig. 7 Simulation results of the proposed 1-bit QCA full adder architecture

Table 1
Truth table of 1-bit QCA full adder

Table 2
Comparative table for the 1-bit RC QCA adder architectures

Table 3
Comparative table for the 4-bit RC QCA adder architectures