One current adaptive switching strategy for DC/DC converter with spike limitation

: In this study, a new current adaptive switching strategy with the spike limitation applied in DC/DC converter is proposed. With this switching strategy, the switching speed of the power switch can be regulated adaptively with the change of the load. The turn-on/turn-off current is inversely proportional to the load. So, at the light load, the switching speed of the power switch is faster and the switching losses are lower. In addition, all of the control should be based on one principle that the current/voltage spike across power switch under a smaller load cannot exceed that under a rated load. The switching characteristics of power switch with the proposed switching strategy and the relationship between current/voltage spike, turn-on/turn-off current and power loop stray inductance during the switching transition is discussed in this study. Moreover, the drive circuit is designed in detail. Finally, a boost converter prototype with 200 V DC input voltage/ 380 V output voltage/1 kW output power is established to verify the proposed method. The tested results show that the ef ﬁ ciency of the converter adopted the proposed method rises by 1.5% comparing with that used a conventional switching strategy at the light load.


Introduction
As it forms a crucial and integral part of a power converter, the gate-driver should be paid more attention to. It has a great influence on the switching speed, switching losses, current and voltage variations (di/dt and du/dt), the efficiency and electromagnetic interference (EMI) of the converter [1][2][3]. In recent years, a lot of work regarding the gate-drivers has been done and it mainly focuses on the drive capability, drive speed, isolated power supply and effective switching in [4][5][6][7][8], which most commonly utilises the conventional voltage source drivers (VSDs). However, VSDs have a defect that all the gate-drive energy dissipated through the drive resistance R g and the fixed-drive voltage could not optimise the power losses of the power switch.
As the frequency of power switch increases, the power losses of the drive circuit cannot be ignored, so different resonant gatedrivers (RGDs) [9,10] have been proposed to recycle gate energy losses in the VSDs. The review on the RGD techniques and its assessment in low-power DC/DC converters are presented in [11,12]. The design method and general circuit are proposed in [13,14]. The RGDs are especially impactful for the synchronous rectifier (SR) of buck converters, because the SR is designed with large gate charge to reduce the conduction losses. Nevertheless, it is noted that the RGDs emphasise to reduce the gate losses, while they can hardly reduce the dominant switching losses for highfrequency converter, so the efficiency improvement potentials of the RGDs converter is limited.
To improve the performance of RGDs, the current-SDs (CSDs) are reported in [15,16]. CSDs can reduce the dominant switching losses by generating the constant drive current to charge and discharge the gate capacitance of the power switch, which will accelerate the switching speed. The present CSDs usually use constant drive current and voltage. Thus, if the drive current is stronger, the switching losses will be lower. However, higher drive current normally leads to higher gate-drive circuit losses, so the switching losses reduction and gate-drive circuit losses are needed to be compromised in design of the CSDs. To optimise this issue, the 'adaptive drive current' concept is proposed to weigh the switching losses and drive circuit losses dynamically in [17,18], but they ignore the problem that the stronger drive current not only means the faster switching speed, but also means higher spike during the switching transition, which lead to the problem of EMI. In addition, though the current/voltage variations (di/dt and du/dt) can be controlled and adjusted in [19,20], they lose the merits of the CSD. Meanwhile, the sensing circuit and the drive logic are complex to realise. In [21,22], a real-time variable turn-off current strategy for a power factor correction (PFC) converter with voltage spike limitation and efficiency improvement, but it only discusses the turn-off transient. Infineon has launched the slew rate control insulated gate bipolar transistor driver integrated circuit (IC) EiceDRIVER™ [23], which behaves similar as a traditional driver at level 11 and controls the voltage drop across the sense resistor; however, the turn-off gate current is also controlled with the conventional VSD.
In view of the switching losses and spike during the switching process, this paper proposes one current adaptive switching strategy, where the turn-on/turn-off current for the power switch can be regulated adaptively with the load variation to reduce the dominant switching losses. In addition, the caused spike during the switching process can be limited to a decent value. This paper is organised as follows: the operating principle of the proposed switching strategy is given in Section 2. The switching characteristics of power switch with a constant CSD are fully presented in Section 3. Section 4 shows the design consideration and the drive circuit. Then, the proposed switching strategy is compared with the VSD and tested by means of several experiments in Section 5. Finally, the conclusion is drawn in Section 6.
2 Current adaptive switching strategy

Proposed switching strategy
Taking a boost converter controlled by average current mode, for example, the proposed switching strategy is shown in Fig. 1a. The main circuit is marked in the dotted-line area, which consists of input voltage U in , inductance L, power loop stray inductance L s , diode D and power switch Q. C gs , C gd and C ds are the parasitic capacitances of Q. C D is the parasitic capacitance of diode D. The drive resistance R g represents the inner parasitic resistance and the external series resistance. Moreover, the controller with doubleloop control (voltage loop Gv and current loop Gi) and the proposed gate-driver strategy are presented at the outside of dotted-line area. As shown in Fig. 1a, the current reference signal i Lref through a reverse regulator G, forming the control current signal i ref , which determines the turn-on current i on and turn-off current i off by the current controlled current source (CCCS). Since i Lref is determined by the inductor current, also determined by the load, the drive current i on and i off can change adaptively with the variation of the load. Moreover, the controller outputs signal u g determines the working state of switch Q.

Working principle
In the conventional VSDs, the switching speed keeps constant once the drive circuits are designed and the peak value of current/voltage spikes exist at the switch passing through the maximum current, correspondingly, the converter operates at full load. However, the spikes will fall down with the decrease of switch current due to the same slew rate. In that case, it implies the slew rate during switching transient can be adjusted with the variation of switch current while ensuring the spikes lower than the peak values (i peak , v peak ), as shown in Fig. 1b.
Concretely, the relationship between the duty cycle α and the inductor current i L in a high-frequency DC/DC converter as shown in Fig. 1c. In case the converter is working at boundary conduction mode in point A, the current of this operation point is i L(A) and duty cycle is α (A) . The left region of A can be defined as the discontinuous conduction mode (DCM) area and the right area of that is the continuous conduction mode (CCM) area. It can easily get that the duty cycle α increases rapidly with the increase of i L in the DCM area, while rises slowly in the CCM area. Assuming that the converter works at the light load in point B and operates at the rated load in point C, then, i L(B) < i L(C ) , which means i Lref(B) < i Lref(C ) . The regulator G adjusts the signal i Lref reversely and outputs i ref , as a result, i ref(B) > i ref (C ) . Therefore, the drive current i on(B) > i on(C ) and i off(B) > i off(C ) , which implies the switching speed of the power switch in point B is faster than that in point C. The faster switching speed is, the less switching losses will be. As a result, the efficiency of the converter in the point B could be higher than that in point C. So, with this proposed switching strategy, the switching speed of switch can be regulated adaptively with the inductor current changing and the efficiency can be improved relatively.

Analysis of the switching characteristics of switch
The switching losses and current/voltage spike resulted from switching transient are two key factors in the design of the drive circuit. Although the analytical modelling of switching transition with CSD has been discussed in detail in [24], they neglect the parasitic capacitor of the diode, which has an influence on the switching transient in real circuit. In this paper, the switching modelling of switch [metal-oxide-semiconductor field-effect transistor (MOSFET)] considering the parasitic capacitor of freewheeling diode will be studied stage by stage. A typical boost converter is employed to clarify the switching characteristics. The equivalent turn-on/turn-off transition circuits and the qualitative waveforms of the switching transient are shown in Fig. 2.
To simplify the analysis of the operation stage, the following conditions are assumed: (i) C iss = C gd + C gs and C oss = C gd + C ds are denoted as the input and output capacitances of the MOSFET, respectively. (ii) In all the analytical calculations, the MOSFET has no reverse recovery and it is considered to be a resistance, an open circuit or a dependent current source whose behaviour is described by

Turn-on switching transient
The turn-on transient can be divided into four different substages described in the following sections. Substage 1 [t 1 -t 2 ] turn-on delay time: During t 0 -t 1 , the power switch Q is off and the inductor current I L flows through the diode D.A tt 1 , the PWM signal u g is turned into high level. C iss is charged by the drive current i on . The MOSFET works in the cut-off region until the gate-source voltage u gs reaches to the threshold voltage V TH . I L still circulates through the diode D while the channel current i ch equals to 0. Thus, only the gate circuit should be considered and the equivalent circuit is shown in Fig. 3a. The gate-source voltage u gs is given by

Substage 2 [t 2 -t 3 ] current rise time:
In this stage, when u gs reaches V TH , the MOSFET channel starts conducting and i ch starts to increase from zero, the drain-source voltage u ds simultaneously decreases due to the voltage drop induced by the rising drain current across the stray inductor L s . This voltage drop u Ls determines whether u ds will drop to zero before or after i Ls reaches to I L , which will further determine the operating mode of the MOSFET in this stage and the following stages. Both of them are described as follows.

Case (I):
The MOSFET works in saturation region, the channel current i ch is governed by (1). Fig. 3b shows this stage equivalent circuit and equations can be obtained from this figure, which are as follows: By solving (3), there are two possible cases.
(i) Overdamped condition: The stray inductor L s is relatively large and satisfies (4). Then, the voltage u ds and the drain current slew rate di Ls /dt could be calculated as (5)

Fig. 3 Equivalent circuit during turn-on (a-d)/turn-off (e-h) transition
where (see (6)) (ii) Underdamped condition: L s is small and satisfies (7). Similarly, the u ds and di Ls /dt can be expressed by (8) Case (II): The MOSFET works in ohmic region, in case the drainsource voltage u ds is very small and the drain current i Ls will rise at a rate determined by the stray inductor instead of u gs . If the voltage drop of u ds is neglected, then with U o entirely dropping on L s and i Ls will increase at a constant rate, i.e. U o /L s . In fact, since case II appears when the stray inductance L s is extremely large and is not likely to occur in a well-designed converter, so it will not be discussed in the following sections.
Substage 3 [t 3 -t 4 ] Current ringing time (diode reverse recovery time):A tt 3 , i Ls reaches I L , the diode D will change its polarity and start the reverse recovery process. The current ringing begins and the stray inductor will resonate with parasitic capacitors C D and C ds . Thus, i Ls continues rising and u ds decreases simultaneously. The equivalent circuit of this stage is shown in Fig. 3c. The equations can be established as By simplifying (10), the di Ls /dt can be gotten (see (11)) However, the solution of (11) is very complicated and the results are not convenient to analyse. It is necessary to scrutinise on the other hand. Here, analysis can be deduced from the principle of the reverse recovery characteristic of the diode. According to the Kirchhoff's current law, the drain current i Ls is given by where i CD is the reverse recovery current. The dotted-line area of Fig. 3c shows the characteristics of the diode reverse recovery. The reverse time t rr is divided into two parts t a and t b , when i CD rises from 0 to I rr_max and then returns to 0, respectively. The reverse recovery charge Q rr is also divided into Q rr.1 and Q rr.2 .
According to the reverse time, di Ls /dt obtained from (5) or (8) is the current slew rate of i Ls at i Ls = I L , which are dependent on the case MOSFET works. Accordingly, the equations can be founded I rr_max is calculated by (13) Therefore, the maximum current i peak flows through the drain of MOSFET is given by At t 4 , the drain-source voltage u ds decreases to U ds(on) , the MOSFET will go into the ohmic region. Substage 4 [t 4 -t 5 ] current damping oscillation time: In this stage, the MOSFET works in ohmic region and u ds remains at U ds(on) . The channel current i ch is no longer controlled by u gs , which keeps constant at I L . C gs continues to charge and u gs goes on to charge up and will reach V cc . However, the loop stray inductance L s and parasitic capacitances C D will keep on resonating together until the current i CD arrives 0 at t 5 . The equivalent circuit illustrates in Fig. 3d.

Turn-off switching transient
Similar to the turn-on switching process, the turn-off transient can be also divided into four substages.
Substage 5 [t 6 -t 7 ] turn-off delay time:Att 6 , the PWM signal u g is set as 0 and the turn-off current i off starts to discharge the input capacitance C iss . The MOSFET operates in the ohmic region and i ch , u ds remain unchanged in this stage. The equivalent circuit is a = g fs C gd 2(C ds C iss + C gs C gd ) , v 2 0 = C iss L s (C ds C iss + C gs C gd ) , shown in Fig. 3e. The u gs can be expressed as When u gs = V TH + I L /g fs , this stage ends. Substage 6 [t 7 -t 8 ] voltage rise time: Fig. 3f shows the equivalent circuit during this period. The MOSFET operates in saturation region and the channel current i ch drops suddenly. The excess current I L -i ch -i CD charges the parasitic capacitances C gd and C ds . Therefore, the voltage u ds starts to rise until it reaches U o and the i Ls begins to decrease from I L . In this stage, the circuit equations can be expressed as follows: However, due to the Miller effect, there is a plateau region in u gs which keeps constant, so the current i gs approximates to 0 in this interval. Thus, u ds and i Ls are obtained from (17) i This period ends when the u ds arrives at U o at t 8 . In addition, if the i ch reaches 0 before u ds goes to U o , which is likely to happen if I L is relatively small. In that case, the following stage has access to Substage 8 directly. Substage 7 [t 8 -t 10 ] current falling time:Att 8 , the diode D ceases to block the voltage and the I L starts to divert from the MOSFET to D. Since the stray inductance L s impedes a sudden change in the drain current, the drain-source voltage u ds continues increasing. The equivalent circuit is shown in Fig. 3g. Similarly, the equations can be founded as Similar to the expression (11), the solution of (19) is difficult to analyse. So, the analytical method in [25] is adopted here. This period can be divided into two stages and the specific demonstration is as follows.
(i) Current falling period (I) [t 8 -t 9 ]: In this short stage, assume the gate voltage keeps constant and as well as the channel current. At t 8 , the circuit conditions can be simplified by independent current and voltage source in the circuit and a rearrangement of the sources. Then, the final equivalent circuit can be achieved, as shown in the dotted-line area (1) of Fig. 3g. It is clear that the L s and C ds will resonate with each other and the u ds can be easily expressed from Fig. 3g u where the current I ch∞ is the initial value of the channel current, which is obtained based on the approximation, the detailed derivation is given in the Appendix. This stage ends when the current i Ls arrives at the channel current I ch∞ at t 9 , the u ds has reached its peak value u peak , which can be easily calculated u peak = u ds (t 9 ) (ii) Current falling period (II) [t 9 -t 10 ]: During this period, the voltage u peak -U o effects on the stray inductor. The drain current will be forced to continue falling to 0. As the current difference i Ls -i ch charges the capacitance C ds , these two values are very close during this period, so there will not be a large current charging C ds . Hence, the voltage u ds can be considered equal to u peak approximately. To simplify this stage, the channel current i ch is assumed to be controlled by the voltage U o . The equivalent circuit of this stage is shown in the dotted-line area (2) of Fig. 3g, i ch can be approximated as At t 10 , the channel current i ch decreases to 0 and this stage ends. Substage 8 [t 10 -t 11 ] voltage damping oscillation time: After the channel current i ch decreases entirely to 0, u gs reduces from V TH to 0 and the MOSFET works in the cut-off region. At this moment, a resonate circuit formed by L s and C oss begins to oscillate; however, the stray resistance R s will damp the oscillation until the voltage u ds reaches its steady-state value U o . The equivalent circuit is shown in Fig. 3h. The voltage u ds and drain current i Ls can be deducted as where This stage ends when the u ds keeps a steady-state value U o .

Power losses during turn-on transition
According to the analysis of turn-on process, the power losses during [t 1 -t 2 ] and [t 2 -t 3 ] can be easily calculated. While the power losses derivation during [t 3 -t 5 ] could be sophisticated because the circuit is ringing. To calculate the power losses during this interval, the perspective of energy change extensively analysed in [26] is utilised. First, the energy losses during the period of the current i Ls changing from I L to its peak value i peak are approximated to where Q rr.1 is the part of the reverse recovery charge Q rr that is removed from the diode as shown in Fig. 3c. At t 5 , the circuit reaches steady state when the ringing is fully clamped. The only energy in the loop is stored in C D , thus the energy losses in this part is With Q rr.2 as the other part of Q rr that is needed to charge the parasitic capacitance C D . Therefore, the total energy losses in this interval can be expressed as Hence, it is easy to obtain the power losses during [t 3 -t 5 ] The power losses under different substages of turn-on process are illustrated in Table 1.

Power losses during turn-off transition
Similarly, the power losses derivation in the periods of [t 6 -t 7 ], [t 7 -t 8 ], [t 8 -t 9 ] and [t 9-t 10 ] can be gotten easily from the equivalent circuits, which are given in Table 2. Similarly, the power losses during [t 10 -t 11 ] can be calculated by the energy stored at the beginning and the end of this stage. At t 10 , the energy stored in the loop circuit is At the end of the stage, the energy stored is Besides, the energy recovered to the source during [t 10 -t 11 ]i s given by The energy dissipated in the loop circuit can be obtained Therefore, the power losses can be gotten during [t 10 -t 11 ] As depicted in Tables 1 and 2, the power losses during the turn-on and turn-off transitions are closely related to the turn-on current i on and turn-off current i off , respectively. It is necessary to design i on and i off reasonably to improve the performance of the converter.

Design of turn-on /turn-off current with spike limitation
According to the analysis of switching transient in Section 3, the faster the switching speed is, the lower the switching losses will be. However, as displayed in (15) and (21), larger turn-on/ turn-off current may lead to a higher current/voltage spike. If the spike value is extremely large, the switch will be possible to break down. Therefore, in the design of the turn-on/turn-off current, the current/voltage spike should be treated as the most important reference. It is easy to find that the spike value is dependent on the inductance current I L , turn-on/turn-off current, power loop stray inductance L s , the inherent parameters of MOSFET along with freewheeling diode (g fs , C iss , C oss , C rss and Q rr ). On the basis of the aforesaid analysis with the proposed switching strategy, the design principle is that the current/voltage spike under a smaller inductor current is not greater than that under a rated inductor current; meanwhile, the switching speed changes adaptively.
A typical boost converter is used to demonstrate the design procedure of the turn-on/turn-off current. The setup is as follows: the switch MOSFET is IRFP460A and the diode is RHRG1560_F085. Their relational parameters found in the datasheet are listed in Table 3 t 9 -t 10 P 8 Loss = f s u peak relationship between the current/voltage spike (i.e. i peak /u peak ) inductor current and the turn-on/turn-off current (i.e. i on /i off )i s shown in Fig. 4. It can be intuitively gotten that the turn-on/ turn-off current will increase with the decreasing of inductor current I L if the spike value is fixed constant. From the relation curve in Fig. 4, the turn-on/turn-off current (i.e. i on /i off ) can be approximately designed as where N 1 , N 2 being two constants, which are different under turn-on and turn-off conditions.

Drive circuit
Fig . 5 shows the turn-on/turn-off drive circuit which is not limited to this kind of method. Here, the UC3854A is employed to control the boost converter. The CCCS shown in Fig. 1a that consists of the CAOUT pin signal and voltage control current source (VCCS) shown in Fig. 5b are used to adjust the turn-on/turn-off current, adaptively. The turn-on adaptive drive circuit includes VCCS-1, R 1 -R 3 , T 1 -T 2 , D 1 -D 4 and a comparator IC1, while the turn-off circuit is composed of Q 1 , T 3 and T 4 . If the u pwm is high level, the i on will charge the C iss to turn-on MOSFET, while if the u pwm is low level, the i off will discharge the C iss to turn-off the MOSFET by the mirror current source. The VCCS consists of the LT3086 produced by linear company and its peripheral circuit, which is explained at length in the datasheet [27], as shown in Fig. 5b. In addition, the CAOUT and V REF are two pins of the UC3854A. If the signal in CAOUT is u c , the inductor current I L is similar proportional to Hu c according to the analysis in Section 2.2. Moreover, the VCCS could be expressed by i on (i off )=Ku r , where u r is the adjustable signal in the TRACK pin. Therefore, if R 5 = R 6 = R 7 , and D 5 is IN4733, the drive signal current is given by where K and H are two constants, but R 8 and R 9 are different in VCCS-1 and VCCS-2, obviously (35) matches with (34).

Experimental verification
To verify the proposed adaptive drive strategy, one boost converter with 200 V input, 380 V/1 kW output and 150 kHz was built and other specifications are listed in Table 3. The control IC is UC3854A and the adaptive drive circuit is shown in Fig. 5.I ti s noted that the smaller the loop stray inductance (is), the better the performance of converter will be. However, in this prototype, to reflect the principle of the proposed adaptive drive strategy, the loop stray inductance is set about 1 μH. From Fig. 4, if the current/ voltage spikes are limited to 10 A and 500 V, respectively, during the switching process, the turn-on current i on can be set within 0.3-2 A modulating adaptively, while the turn-off current within 0.5-2 A, which can be realised by (35). In circuit application, in order to achieve the better control effect, the turn-on or turn-off current can be adjusted within certain realms by regulating R 8 and R 9 in Fig. 5b.
By contrast, the prototype was tested with the proposed drive strategy and the conventional VSD strategy. Figs. 6 and 7 show the key experimental waveforms during turn-on transition and turn-off transition under different loads, respectively. Figs. 6a and b give the waveforms of the drain current i Ls , drain-source voltage u ds and gate-source voltage u gs at full load with the conventional VSD and the proposed method, respectively. It is obviously seen that they show a similar transient process because they are designed as the same turn-on speed at full load. The current spike is limited at 10 A and the duration of t 1 -t 5 shown in Fig. 2 is near 800 ns. As seen in Figs. 6d and f, the turn-on duration of t 1 -t 5 is about 320 ns at the half-full load and is near 200 ns at 20% full load with the proposed drive method. The current spike does not exceed the set value 10 A. However, since the parameters of the drive circuit remain unchangeable in the conventional VSD, the time of turn-on process is fixed, which are illustrated in Figs. 6c and e. Accordingly, by the proposed drive strategy, the turn-on speed is adaptively adjusted and the current spike is limited to the reference value with the change of the load. The overlap area of the drain current and the drainsource voltage is narrowed, so the power losses can be reduced in turn-on transient. Fig. 7 illustrates the comparison of the typical waveforms during turn-off transient with the conventional VSD and the proposed strategy. From Figs. 7a and b, both the voltage spikes are limited to about 500 V and the turn-off duration of t 6 -t 10 shown in Fig. 2 is ∼320 ns. With the load decreasing, the turn-off speed can be adjusted by the proposed strategy, while it remains unchanged by the conventional driving method, which can be seen in Figs. 7c-f. As shown in Figs. 7d and f, the duration of t 6 -t 10 decreases from 240 ns at half-load to 120 ns at 20% full load by the proposed drive strategy; meanwhile, the voltage spike would not exceed 500 V. However, the turn-off duration maintains constant, which can be reflected in Figs. 7a, c and e. Hence, the turn-off power losses can be reduced with the proposed driving strategy. In addition, from Fig. 7a-f, it can be seen one duration that u gs is reduced and hold as constant, i Ls is still high and u ds is still low. This is caused by the reverse recovery of the power MOSFET, but it has no influence on the spikes and switching losses, so this stage has not been marked in Fig. 2. Fig. 8 shows the efficiency comparison of the proposed drive strategy and the conventional drive method. It is shown that the converter efficiency using the proposed switching strategy under light load rises by more than 1.5% that in the conventional drive method.

Conclusion
This paper presents a new current adaptive switching strategy applied in DC/DC converter, which can limit the current/voltage spike as the switching speed is regulated with the change of load. First, the working principle of the proposed switching strategy is analysed. Then, a circuit-level model, in consideration of MOSFET capacitances, the circuit loop stray inductance and the The expressions of the current/voltage spike can be obtained from the analysis of the switching transition. The relationship between the drain current, the inductor current and turn-on/turn-off current is discussed in detail to design the drive circuit. Finally, the prototype with a boost converter has been established to verify the proposed switching strategy. Besides, the conventional drive method (VSD) has also been tested to be compared with the proposed method. The experimental results show that theoretical analysis is correct and the converter with the proposed switching strategy has a higher efficiency than that with the conventional drive method under a light load.

Acknowledgments
This work was supported by Funding of Jiangsu Innovation Program for Graduate Education KYLX15_0275 and the Fundamental Research Funds for the Central Universities.