MMC with parallel-connected MOSFETs as an alternative to wide bandgap converters for LVDC distribution networks

Low-voltage direct-current (LVDC) networks offer improved conductor utilisation on existing infrastructure and reduced conversion stages, which can lead to a simpler and more efficient distribution network. However, LVDC networks must continue to support AC loads, requiring efficient, low-distortion DC–AC converters. Additionally, increasing numbers of DC loads on the LVAC network require controlled, low-distortion, unity power factor AC-DC converters with large capacity, and bi-directional capability. An AC–DC/DC–AC converter design is therefore proposed in this study to minimise conversion loss and maximise power quality. Comparative analysis is performed for a conventional IGBT two-level converter, a SiC MOSFET two-level converter, a Si MOSFET modular multi-level converter (MMC) and a GaN HEMT MMC, in terms of power loss, reliability, fault tolerance, converter cost and heatsink size. The analysis indicates that the five-level MMC with parallel-connected Si MOSFETs is an efficient, cost-effective converter for low-voltage converter applications. MMC converters suffer negligible switching loss, which enables reduced device switching without loss penalty from increased harmonics and filtering. Optimal extent of parallel-connection for MOSFETs in an MMC is investigated. Experimental results are presented to show the reduction in device stress and electromagnetic interference generating transients through the use of reduced switching and device parallel-connection.


Introduction
There have been reported cases of distribution networks operating close to their capacity limits [1].DC networks are being suggested as a means of addressing the issue of converter rich AC networks and improving conductor utilisation, thus increasing network capacity using existing infrastructure.Reports state that low-voltage direct-current (LVDC) technology could provide large power capacities without replacing the existing cables [2][3][4].Furthermore, LVDC networks present the additional benefit of no reactive power flow and allow reduction in the number of conversion stages [5][6][7].However, these systems will retain the need to supply local AC loads which must be provided by DC-AC converters meeting the same stringent performance criteria outlined above for AC-DC converters supplying DC loads such as electric vehicles (EVs).Issues of power quality also affect LVDC networks and are complicated by the need to supress DC harmonics associated with single-phase loads and to have resilience to DC network faults.
Meanwhile, increasing load demands, distributed generation, and the growing use of electricity for heating and vehicle transport contribute significant strains on existing LVAC distribution networks [1].These increasing numbers of DC loads require controlled low distortion, unity power factor AC-DC converters with increasing capacities as well as bi-directional capacity.In the UK, statistics show that full penetration of EVs is predicted to increase total electricity consumption by ∼50% [8].EV chargers present much high power loads operating at higher frequency and higher voltage than the existing numerous lighter power electronic loads (such as PC's, phone chargers etc.), driving a need to facilitate the adoption of high performance converters capable of handling high power, frequency and voltage.These loads must be supplied whilst meeting strict harmonic limits and avoiding issues of circulating currents and control band oscillations associated with power electronic rich networks.This growth drives a critical need for improved converter performance in terms of efficiency, power quality and control.
The consequent number of converters required, when LVDC networks are combined with high numbers of EVs, further increases the pressure to improve converter efficiency as losses from thousands of converters accumulate, and underlines the imperative to meet strict harmonic standards to ensure continued grid stability [9][10][11].To date, higher power applications have been met using two-level insulated-gate bipolar transistor (IGBT) inverters, however IGBT devices are now at the limit of performance.Two solutions can be proposed for this.Wide bandgap (WBG) devices are now available with appropriate voltage and power ratings.The exploitation of WBG fast switching behaviour can be used to increase modulating frequency while simultaneously increasing efficiency compared with IGBT.Higher modulating frequency in turn allows smaller, lower loss filters.Basic circuit topology remains unchanged but the devices are expensive and their high speed can introduce electromagnetic interference (EMI) issues [12].Gate drivers for very fast switching devices can also be challenging to implement [13].Alternatively, improved control and power quality can be facilitated at lower switching frequency by improvements in the converter output waveform, by using a stepped waveform such as that generated the modular multi-level converter (MMC) topology.A stepped waveform reduces the harmonic content of the output current and voltage, which allows a reduction in filter size and complexity and leads to reduced VAR consumption, simplified control, reduced circulating harmonic/ reactive current, greater stability and less filter damping loss.
Multi-level converters allow the decoupling of power quality and device switching frequency.They offer the potential to drive down conversion loss but have received little attention at low voltage due to the apparent increase in complexity.This paper will investigate the potential benefits and limitations of multi-level techniques in comparison to the extension of two-level converters through the use of WBG devices.
In this study, a DC voltage of 600 V is selected with 10 kW, single-phase power transfer.There are many suitable converter topologies at this voltage, each with different advantages, and hence this research aims to provide a comparison of converter topologies, comparing efficiency, volume and reliability, for converters capable of meeting strict harmonic standards.Generally, the complexity of the circuit topology and the large number of capacitors required are the main limits of using flying capacitor converters [14].For neutral point clamped (NPC) converters, additional inverter control may be required to balance the neutral point.The losses are not equally distributed in NPC converters, thus limiting current rating by the most stressed semiconductor devices [15,16].
Three principal converters stand out as being the most suitable, innovative solutions for this application: Si metal-oxide-semiconductor field-effect transistor (MOSFET) MMC, GaN highelectron-mobility transistor (HEMT) MMC and SiC two-level [17].Selecting which of these converters brings the best performance is non-trivial as efficiency is affected not only by semiconductor losses but also by the filtering required to meet harmonic standards.This research optimises the design of the three converters including filtering, and validates the outcome of the comparisons using experimental results for SiC and Si MOSFET.Discussion on reliability and fault tolerance differences between the three converters is also included, as well as a comparison of required heatsink volume.
Expected benefits of the low-voltage (LV) MMC as an alternative to two-level converters are summarised as: (i) continuous arm currents, (ii) negligible switching loss, allowing slowed switching, leading to reduced dv/dt, (iii) modular construction, (iv) no need of a DC-side filter, (v) better output waveform quality leading to smaller AC filters, (vi) negligible switching losses and (vii) the ability to prevent capacitor discharging current.The modular structure of the MMC allows the use of lower voltage rated Si MOSFETs in place of IGBTs, allowing further loss reduction through parallel connection and synchronous rectification.
The two-level Si MOSFET converter is excluded because a Si MOSFET (≥600 V) has a larger power dissipation than an IGBT [18,19].
2 Design optimisation for low-voltage converters: Si MOSFET MMC, GaN HEMT MMC and SiC two-level 2.1 Operating principle and component sizing of LV MMC type converter 2.1.1Operating principle: The topology of a five-level MMC, where four submodules and one arm inductor form one arm, is shown in Fig. 1a.Fig. 1b illustrates the average model of a singlephase MMC.In each arm, R represents the semiconductors ohmic loss [20,21].
This paper assumes that current suppression control eliminates all harmonics and the remaining circulating current (i diff ) has only a DC component I dc .According to [22], arm currents can be expressed as ( 1) and (2), where I dc is the DC component of i diff and i ao is the sinusoidal output current 2.1.2Design of passive components (sizing capacitors and inductors): To reduce MMC bulk, capacitance is set to the minimum required to stay within ±10% voltage fluctuation [23].The submodule capacitance, C sub , is sized based on maximum energy deviation [24] (adapted for a two-phase-leg topology), so that submodule capacitance is given by (3) [25], where n is the number of submodules in one arm, ΔV max is maximum voltage difference in p.u., M is the modulation index and S is apparent power While current suppression control effectively reduces second harmonic distortion, circulating currents at switching frequency can only be suppressed by arm inductance, since switching frequency exceeds controller bandwidth [24].The difference between phase leg voltage and V dc results in circulating current.If arm currents are dominated by DC and fundamental components (1) and ( 2), the voltage difference u diff is given by the following equation [20] Peak-to-peak circulating current at the switching frequency is given by the following equation ΔT is the time between switching, with its largest value equal to the inverse of switching frequency 1/f S , and the maximum value of I pp Minimum arm inductance is given by the following equation [25]

Si MOSFET five-level MMC
According to [25], 18 mF capacitors are chosen for the two-level converter, which is calculated from the peak-to-peak energy deviation.By using (3), the required C sub for different levels of MMC at M = 0.57 (240 V rms output) can be obtained and the calculated losses are compared in Fig. 2. Interestingly, with increasing number of MMC levels, capacitor losses are almost constant, while semiconductor losses decrease gradually.Parallel-connection of ≥2 MOSFETs reduces conduction loss dramatically.Converter power loss calculation will be presented in Section 3.
Fig. 2 shows how converter cost increases significantly with higher converter levels, dominated by capacitor costs.Significant capacitor loss means that simply increasing the number of levels is counterproductive for efficiency, while also adding complexity, volume and cost.The five-level MMC with parallel-connected Si MOSFETs provides the optimum balance between control complexity, losses and costs.

GaN HEMT three-level MMC
Comparing available GaN HEMT devices showed that a GaN threelevel MMC using 650 V GS66516T devices promises highest efficiency, as illustrated in Table 1.

SiC two-level converter
With higher breakdown voltage [14], lower R on and very low diode recovery loss, SiC MOSFETs are increasingly adopted for high efficiency.For LVDC at 600 V dc a two-level converter is the most efficient SiC MOSFET topology.The 1.7 kV Cree CAS300M17BM2 device provides low R on , as shown in Table 1.
3 Converter power loss estimation

Semiconductor losses
MOSFET and GaN transistor conduction loss is given by ( 8), assuming synchronous rectification [26,27] where i DS is the drain-source current.R on is the on-state resistance, given by the following equation [28] where R on_25 gives R on at 25°C and k R on is a coefficient obtained from the datasheet.Interpolation of SiC datasheet switching loss predicted far lower loss than experimental SiC switching loss measured by the authors.Measured SiC switching loss at 600 V dc is presented in Section 5.1, and is used for all loss comparisons.
Si MOSFET and GaN transistor switching loss is given by the following equation [29,30] where t on and t off are the turn-on and turn-off times, respectively, and are obtained from switching gate charge Q SW and average gate current I GS [31] I GS can be approximated by the Miller plateau gate current where V P is the Miller plateau voltage, and R g denotes total gate resistance.
Diode switching loss is

Capacitor loss calculation
At ≤400 V, electrolytic capacitors achieve small volume, but bulkier film capacitors provide low equivalent series resistance (ESR).A comparison between electrolytic and film capacitors in Table 2 reveals that with film capacitors, capacitor loss is almost eliminated at a cost of increased weight and volume.Currently, lower voltage film capacitors are unavailable so parameters in the second row of Table 2 are estimates provided by API capacitors.For the MMC, submodule capacitor losses in upper and lower arms are given by ( 14) and ( 15), respectively For the SiC two-level converter, loss occurs in the DC-side capacitor.Using peak energy deviation [24,25] it can be shown that the required capacitance is given by the following equation DC-side capacitor current, i cap (t), is assumed to contain all of the AC components of the upper switch current DC-side capacitor loss is then found from the following equation 3.3 Inductor loss 3.3.1 MMC arm inductor loss: Using ( 10) and ( 14), the minimum arm inductance for a 10 kW, M = 0.57, f s = 10 kHz, V dc = 600 V, ΔV max = 0.1 MMC operating at unity power factor is 1.5 mH.Air-gapped Blinzinger ferrite E160/56/36 cores [33] were used to minimise inductor loss.Inductor loss is calculated using ( 21) and ( 22) Harmonic analysis calculations show that ferrite core loss may be neglected.With four arm inductors in total, MMC inductor loss is 192 W regardless of the number of levels.
3.3.2Two-level converter inductor loss: Analysis of single-phase two-level converter harmonic performance showed that 1.7 mH of AC-side inductance is required to maintain harmonics below 5% of fundamental current.Blinzinger E160/56/36 cores [33] were used again.Harmonic analysis of the two-level converter with 1.7 mH of converter-side inductance showed significant harmonics at the switching frequency of 10 kHz, and hence with skin effect, total loss in the AC-side inductor is 268 W.
In addition, to keep DC-side currents below 5% of DC input current, a DC-side inductance of 6.5 mH is required.Using the Blinzinger E160/56/36 cores again total DC-side inductor loss is estimated to be 88.5 W.
Total inductor loss for the two-level converter is therefore 356.5 W.

Comparative study of converters
Three converter topologies based on Si MOSFET, SiC and GaN devices are proposed.Parallel connection of switching devices is explored to reduce conduction losses and heatsink sizes are compared.
4.1 Power lossoptimal number of parallel-connected devices As shown in Fig. 2, parallel connection can significantly reduce converter losses.With many parallel-connected devices, the effect of track resistance becomes more significant [30], imposing a limit on parallel connection.In addition, this section discusses the current unbalance limits for parallel connection.
Power losses for different numbers of parallel-connected devices are plotted in Fig. 3. Track resistance is seen to roughly limit the benefit of parallel connection, with respect to efficiency, to four devices.With four IRFP4668 devices in parallel, total current rating is now 800 A, bringing strong potential reliability benefits to the Si MOSFET MMC in terms of device stress compared with the SiC module current limit of 300 A, and a current limit of 240 A for GaN three-level MMC with four parallel devices.
For the MMC, low switching loss permits slower turn-on/off without undue impact on loss, enabling a lower EMI solution [27], in contrast to the SiC two-level converter where high switching loss prohibits slow turn-on/off.
In Fig. 3a, the Si and GaN MMC offer lowest loss.Device packaging and footprint area impact parasitic resistance and inductance incurred by parallel connection.For an LVDC MMC converter using Si MOSFETs all devices are available in TO-247 packaging.Laying out four TO-247 devices in the most efficient manner leads to a volume of around 16 cm 3 which is around 21% of the predicted heatsink volume.Hence, for around four devices in parallel, device packaging and size are a lesser concern compared with gate-drive complexity and efficiency when establishing optimal parallel connection.For four TO-247 devices laid out efficiently and using slowed switching, gate threshold tolerances have far more impact on switching synchronisation than different gate track lengths imposed by layout, hence efficiency dictates optimal parallel connection for Si MOSFETs.Switch timing is experimentally investigated below.
Parallel connection of many surface mount GaN devices may be more practical.However, currently GaN devices are expensive, and the diminishing improvement in efficiency with increased parallel connection beyond four to six must be considered alongside the expense of more devices.

Reliability
The luxury of being able to reduce switching speed in both Si and GaN MMC also improves reliability by allowing switching transients to be reduced and hence minimising voltage stress due to overshoot, as will be demonstrated in Section 5.In addition, the availability of low-cost, high current rating Si MOSFETs minimises current related device stress.Since device stress is a significant cause of converter failure, converter reliability seems likely to noticeably improve with the use of Si or GaN MMC, thus mitigating any reduction in reliability that can be attributed to increased complexity.In [34], for photovoltaic applications, it is concluded that SiC offers a superior solution to Si IGBT due to a combination of lower life-cycle costs, lower part count, higher efficiency and power density.In [35], gate reliability of SiC power devices is found to be problematic, however, [36] suggests that up to date SiC devices suffer reduced gate reliability issues.
GaN brings the advantage of very fast switching, but this comes at the cost of increased gate-drive complexity, and increased risk of oscillation [13], both of which are likely to impact reliability.Mean time to failure for the Si MOSFET is around 1.5 × 10 8 h [37], while with GaN it is around 1.9 × 10 6 h [38], suggesting that the GaN power devices are less reliable.
The SiC converter contains eight times fewer power switches than the Si MOSFET five-level MMC, and if the reliability of both semiconductor switch types were equal, and if we ignore the reduced stresses on the devices in the MMC topology, would equate to an improvement in reliability of eight times.Hence, there is a complex balance required to compare the reliability of the converters.At this time, quantifying the potential reliability improvements offered by reduced voltage stress in MMC topologies and the relative impact of SiC gate reliability in twolevel converters is an area of interest which longer term industrial studies will demonstrate in time.

Fault tolerance
The choice of converter topology will have implications for the fault response of LVDC networks, in particular severe pole-pole short circuits.The use of conventional two-level converters results in rapid rise in fault current associated with the discharge of converter DC side capacitance accompanied by AC fault contribution which builds through the converter body diodes as the DC voltage collapses below the envelope of the AC network [39].Once the DC rail fully collapses both current components are transferred to the diode path placing significant stress on the converter power modules.Fast acting DC protection is therefore required to prevent both de-energisation of the network and damage to converters.
The impact of converter topology has seen significant research in high-voltage DC applications.The adoption of the MMC topology can prevent the capacitive discharge component of the DC fault current, however the basic topology is still subject to fault current through the module diodes.The use of reverse blocking converters such as the full-bridge and half-bridge MMC has the ability to block both capacitor discharge and AC contribution to the DC fault [40].Improved fault behaviour is achieved at the expense of additional devices and conduction loss.
MMC-based converters can bring the same functionality to LVDC systems.In these cases, the lower operating voltage provides greater degrees of freedom in the design.For instance, mixed device ratings may allow the use of fewer reverse blocking cells giving fault tolerance while minimising impact on overall converter loss.An additional interesting point is that parallel connection in MMC leads to high transient overload capacity allowing faults to trip conventional protection whilst at the same time reducing operational losses.

Cost
Fig. 2 demonstrates the impact of increasing number of levels on Si MOSFET MMC cost, giving a cost of around £1000 for the parallel-connected five-level case.For comparison, GaN three-level MMC costs around £1150, and SiC two-level converter around £1500.Si MOSFET MMC currently offers the lowest cost solution out of the three compared converters.
4.5 Thermal design and heatsink sizing 4.5.1 Deriving thermal resistance: Thermal design is carried out for 10 kW SiC MOSFET two-level, GaN HEMT three-level MMC and Si MOSFET five-level MMC converters with four parallel-connected devices ('three converters'), and compared with a 10 kW IGBT two-level converter.To follow the approach in [26] most thermal resistances can be obtained from the datasheet.Only the Si MOSFET datasheet provides the case-to-heatsink thermal resistance, R θ(C-S) , which is affected by the contact quality [41].SiC MOSFET/GaN HEMT R θ(C-S) is estimated by the following equation where A Si and A SiC are the contact areas for the Si and SiC devices, and R θ(C-S)Si is the datasheet Si MOSFET R θ(C-S) [42].
To mount the optimal top-side cooled GaN HEMT device, a pedestal copper block is required [43], but the copper block has negligible thermal resistance.

Heatsink sizing:
IGBT two-level converter losses in one arm with M = 0.57, T J = 125°C are listed in Table 3, along with required heatsink volume.
Power loss and required heatsink volume are listed in Table 4 for the 'three converters'.Despite similar loss in the GaN three-level MMC compared with the Si five-level converter, the small GaN transistor package leads to larger R θ(C-S) , and hence double the heatsink volume.Even when compared with GaN three-level MMC, the heatsink volume required for a conventional IGBT two-level converter is over ten times larger.
5 Experimental results and analysis 5.1 Thermal measurement for the validation of power loss calculation 5.1.1Experimental validation of Si MOSFET loss calculation: Measurement of loss in the complete MMC is not practical, so loss in a single MMC module operating at fixed 50% duty cycle was measured instead.Loss was measured by first calibrating heat rise on the heatsink as a function of dissipated power by passing DC power through the Si MOSFET switches to calibrate temperature rise as a function of power loss in the switches.The experimental test rig is shown in Fig. 4, containing a single Si MOSFET MMC module with an R-L load, at 100 V dc and 1-20 A AC-side load current range, using IRFB4127PbF MOSFETs.
Fig. 5 shows the estimated and measured power dissipation for synchronous and non-synchronous rectification cases, highlighting the benefit that synchronous rectification brings for MOSFETs.Track resistance power losses are included since device on-resistance is now so low that track resistance becomes relevant in a prototype such as was available during this study [27].Fig. 5 shows that measured and calculated losses agree closely, validating the power loss calculation in Section 3.
5.1.2Experimental measurement of SiC MOSFET loss: SiC losses were compared with losses calculated using interpolation from datasheet switching loss.Heat rise for this large SiC module was found to be too small to measure accurately, however, smooth and relatively slow switching (compared with Si MOSFETs) allowed accurate determination of losses using conventional voltage and current measurements.Switching loss as a function of current is presented in Fig. 6, showing little variation in switching loss with load current at these low load currents.This is due to the dominance of capacitance effects in SiC switching loss [44].For accurate loss comparison with Si MOSFET devices measured switching loss was used to calculate SiC two-level converter efficiency.Conduction loss was found to agree with calculation.

Current sharing in parallel-connected MOSFETs
Parallel-connected devices are very desirable in MMC to reduce on-resistance since low device switching frequency of MMC means conduction loss dominates over switching loss.However, parallel connection of MOSFETs risks increased damage to devices during switching transitions if oscillations exist between parallel-connected devices.It is therefore important to investigate the behaviour of parallel-connected MOSFETs, and explore options to mitigate the risks caused by transient behaviour.
As increasing gate resistance slows down, switching speed EMI is reduced [27], and gate oscillations will be damped.However, increased gate resistance also exaggerates the spread in component tolerances leading to greater discrepancies in turn-on/off times.To explore the effects of increased gate resistance, current in individual devices in one submodule with four parallel-connected MOSFETs at 3 kHz switching frequency and 16 A load current, was measured.Non-symmetrical layouts lead to dynamic current imbalance, resulting in unbalanced switching losses [45], however with such low switching losses this effect is of no concern.
The dominant cause of static current unbalance is R on mismatch.Experimental results in Fig. 7 show good static current balance.
Different individual device threshold voltages and transconductances lead to varying switching rates as seen in Fig. 7 where MOSFET4 turns on first.The Miller effect then slows down the rise in V GS in the other three devices.The large current overshoot of MOSFET4 is caused by larger reverse recovery of its body diode resulting from its rapid turn-on transition.This dynamic current unbalance and the parasitic oscillations are exacerbated by the combined effects of the inductances, the gate and drain resistances, the gate-source capacitance and the drainsource capacitance [45,46].Considering so many factors affecting the switching performance, it is practically impossible to match the MOSFET switching transients [45].
However, Fig. 7 shows that the current overshoot is safe for all devices even at a gate resistance of 1 Ω, while with 100 Ω the current overshoot with four devices parallel connected is smaller than that for a single device switching with small gate resistance.As increased gate resistance slows down switching, oscillation and di/dt are attenuated significantly, reducing EMI.Fig. 7 clearly demonstrates that the MMC topology with increased gate resistance has significantly reduced device stress, while reduced ringing and slower transients will dramatically improve EMI, compared with a two-level converter.

Conclusions
The complex factors which must be considered when determining an optimal converter design for LVDC distribution networks have been thoroughly investigated.Power loss including semiconductor conduction, switching, capacitor and inductor losses was calculated for three different competing converter topologies.MMC topologies offer 200 W lower loss than the SiC two-level converter, while offering the possibility of fault tolerance with minimal impact on loss.Slowed switching with no loss penalty in MMC converters also offers improved reliability as switching waveforms presented here show reduced device stress, while EMI will also be significantly reduced.With by far the smallest heatsink volume Si MOSFET MMC offers a surprisingly competitively compact solution despite the requirement for a larger number of cell capacitors.GaN appears to offer highest efficiency by a small margin, but it remains to be seen how the high-speed, sensitive GaN gate drivers perform in terms of reliability, while reliability of the GaN power devices appears to be lower than that of the Si MOSFET.However, since GaN is a new technology this reliability gap may close in time.In addition, counter-intuitively, the very small packaged GaN HEMT requires double the heatsink volume compared with Si MOSFET.The main advantage offered by the SiC two-level converter is simplicity, but the reliability history of SiC devices offsets this advantage, and with lower SiC two-level efficiency, the MMC topologies are more attractive.At this time, Si MOSFET MMC offers the lowest cost converter for this application, although the authors note that relative costs are likely to be subject to much change.
Therefore, for low-voltage, single-phase converters at 10 kW, Si MOSFET MMC offers the highest performance converter, with lowest cost, and small size.
Parallel connection of devices offers lower MMC loss and further reduction in devices stress, bringing reliability improvement, hence has been analysed during this research.Power loss calculations indicate that four devices in parallel is optimal for the MMC topologies, while parallel-connection was unhelpful for the SiC two-level converter due to the dominance of output capacitance related switching loss.Power loss was found to be the dominating factor dictating optimum extent of parallel connection.Experimental results for four devices in parallel showed good static current sharing, and with slowed switching demonstrated lower device stress and order of magnitude slower and smaller transients to generate EMI.Further work is required to fully quantify EMI reduction.
Calculated loss was successfully validated through experimental measurement for a single MMC module, and for a SiC half-bridge converter.

Fig. 1
Fig. 1 Topology of a five-level MMC and average model of an MMC a Topology of a Si MOSFET five-level MMC b Average model of an MMC

Fig. 3
Fig. 3 Losses in converters with parallel-connected devices for an SiC MOSFET two-level converter, a GaN HEMT three-level and a Si MOSFET five-level MMC at 10 kW, 10 kHz, 600 V dc , M = 0.57 and unity power factor a Converter loss as a function of the number of parallel-connected devices b Converter loss distribution as a function of the number of parallel-connected devices

Fig. 4
Fig. 4 Experimental test rig for power loss measurement

Fig. 5
Fig. 5 Heat dissipation for one MMC submodule with and without synchronous rectification, allowing for track resistance This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)

Table 2
Comparison between electrolytic and film capacitors This product is not available for sale.Parameters are estimated by API Capacitors [32].

Table 1
Parameter comparison between different types of devices a Devices selected in this study.

Table 3
Heatsink sizing for the IGBT two-level converter

Table 4
Heatsink comparison between three converters with four parallel-connected devices (calculated for one-phase leg).