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Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters

Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters

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Recurrence relations and fully pipelined novel cell-level systolic architectures are suggested for massively parallel implementation of two-dimensional FIR and linear phase FIR filters. Owing to the higher level of parallelism, the proposed structures would yield more throughput over the existing structures. Besides, it can be flexibly configured according to the throughput requirement of the application for the chosen processor technology for cost-effective implementation.

Inspec keywords: digital signal processing chips; systolic arrays; performance evaluation; FIR filters; filtering theory; pipeline processing

Other keywords: high throughput implementation; two dimensional FIR filters; pipelined architectures; massively parallel implementation; 2D FIR filters; flexible cell-level systolic architecture; recurrence relations; cost-effective; throughput requirement; linear phase FIR filters

Subjects: Parallel architecture; Digital filters; Signal processing and detection; Digital signal processing; Digital filters

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