Dc‐link current computational methods for three‐phase inverter with low‐order harmonic output current

Both the spectral analysis and the closed-form root-mean-square (RMS) equations are widely used to determine the three-phase inverter dc-link current for capacitor rating proposed. However, the analytical models of the dc-link currents have rarely been reported for applications like the active power filter, where ac currents are mostly low-order harmonics (LOHs). This paper first derived expressions for each dc-link LOH current, in order to compute the capacitor losses for each LOH frequencies. Then, it is shown that the derivation of the dc-link switching harmonic current (SHC) RMS equation is very much complicated when LOHs are present in the ac currents. Hence, new set of generalised RMS equations were successfully derived and simplified into one equation to facilitate the worst case design. The design case of the dc-link current is demonstrated with the proposed equations. A flexible grid-tied inverter lab prototype is developed to inject arbitrary combinations of LOH currents of different orders, sequences, amplitudes and angles into the grid. Good match between the computational and experimental results validates the proposed methods.


Introduction
A key design factor of the three-phase voltage source inverters (VSIs) system is the dc capacitors rating. The dc-link current of VSIs with three-phase sinusoidal ac currents has a dc component, switching harmonics (f sw , 2f sw , …) and its sideband components [1][2][3][4]. The harmonic currents absorbed by the dc capacitors produce the power losses over the capacitor Equivalent Series Resistance (ESR), and the resulting heat could exceed the capacitor thermal limits and shorten its life expectation.
The dc-link current is in high frequency pulsed forms as the superposition of currents in the three upper phase legs of VSI [5,6]. Among the analytical methods proposed [1][2][3][4][7][8][9][10][11], double Fourier series analysis is widely used to generate the full spectrum of all the harmonics in the dc-link current and a general method to analyse the dc-link current spectra for most types of inverters was proposed in [2], where each frequency component needs to be individually obtained to compute the capacitor losses. In practical design cases, the capacitors ESR (electrolytic or film) at the pulse width modulated (PWM) switching frequencies almost remains constant [12][13][14]. Therefore, only one root-mean-square (RMS) equation for the dc-link switching harmonic currents (SHC) is needed [1,[7][8][9][10][11], where the dc-link current RMS value is expressed in terms of the modulation index, power factor and the amplitude of the output current. As the inverter output voltage is a PWM voltage, the output current also contains SHC ripples, whose impacts to the dc-link current RMS value are also investigated. In [7], the dc-link current RMS value is derived by Fourier analysis for the three-phase inverter. Herein, it is discovered that the SHC ripples impacts can be neglected when they are <0.3 times of the rated output ac current. Paper [8] demonstrates that the SHC ripples have very limited influence on dc-link current by numerous simulations. In [9,10], the dc-link current RMS closed-form expression is directly derived and it is also shown that there is only about 10% error by neglecting the large SHC ripples in the output ac current. In [15], the dc-link voltage ripple is analysed for threephase VSIs. In [11], the dc-link current and voltage ripple are analysed considering the antiparallel diode reverse recovery spikes. It is concluded that the error caused by this practical complication is only 2%.
So far, almost all attempts to derive the spectra or RMS value of the dc-link current assume sinusoidal three-phase ac currents. However, for many applications like the active power filter (APF), multiple low-order harmonics (LOHs) are present in ac currents and the dc-link current envelopes and patterns are totally different and more complicated to analyse. Very few studies are reported [16,17] so far. Pei et al. [16] dealt with the unbalanced ac currents at the fundamental frequency. Therein, overall RMS values are obtained by integrating the dc-link current expression within each switching cycle over one sector, and the dc-link LOH current is obtained in the same process. Initial investigation into the dc-link current under non-linear (including unbalanced) loads was made in [17] using spectral analysis, where it was stated that if each spectral component in ac output voltages and currents including switching components are enumerated, each dc-link SHC and LOH current could be obtained. However, to enumerate spectral components of the PWM voltages, double Fourier series analysis has to be performed for each different modulation strategy being used, as it alters the spectral distribution of the voltage and the dclink current. Meanwhile, as aforementioned, for many practical design cases, the SHC RMS value is sufficient and this value actually stays constant with different modulation strategies. This paper proposes quantitative equations set to compute the dc-link current for the capacitors rating design in three-phase VSIs applications with LOHs in the ac currents. In Section 2, the basic circuit operation and the dc-link current models are introduced together with the capacitor design aspects and power losses model. In Section 3, the LOH currents in the dc-link are formulated with an instant power based method in synchronous reference frames. Then, the LOH voltages and its maximum value are also formulated. The method simplifies the lengthy trigonometric derivation as in the power computation with three-phase quantities. With a given set of LOH ac currents, the individual dc-link LOH currents are obtained to compute the capacitor power loss for each LOH frequencies with their different capacitor ESR. In Section 4, it is shown that the derivation of the dc-link SHC RMS equation is very much complicated when LOHs are present in the ac currents. Then, the new generalised SHCs RMS equations are successfully formulated, which are also compatible with the equations in prior art when dealing with sinusoidal ac currents. For worst case rating design, the full range of the phase angles of the given LOHs in ac currents must be considered, since they bring up infinite amount of dc-link current patterns and corresponding RMS values. Therefore, the proposed equations are successfully simplified to facilitate the worst case rating design and then demonstrated with quantitative examples. Finally, Section 5 shows a flexible grid-tied inverter prototype developed to inject arbitrary combinations of LOH currents of different orders, sequences, amplitudes and angles into the grid. The dc-link current is measured in specially designed laminated busbars. Thorough experiments are performed and validate the results from the proposed computational methods, and the differences between the experiment and computation results are formulated and explained definitely.

Circuit description and basic operations
The typical circuit diagram of the three-phase VSI applications is as shown in Fig. 1. Therein, the inverter is connected to the grid through an LCL filter. Without a neutral line, the sum of the threephase currents is zero. The inverter is supplied by either a stable dc source or simply a capacitor bank for APF applications. C dc is the dc-link capacitor. T a1 -T c2 are six switches with antiparallel diodes.
Slight differences between the fundamental frequency component of the inverter PWM output and the grid voltages are applied over the LCL filter inductance to control the ac currents into or from the grid, where the SHC are absorbed by the LCL capacitors, and the desired fundamental frequency (ω 1 ) currents or LOH currents (5ω 1 , 7ω 1 ,...as in an APF) flow to or from the grid.
Other three-phase VSI applications such as UPS and motor drives use LC types of output filters. As long as ac current ripples are much smaller than the fundamental component, the analytical methods for the dc-link current are the same.

Dc-link current models
As illustrated in Fig. 1, the dc-link current is the sum of the products of each phase current and its switching state as expressed by where the switching state S i (i = a, b, c) equals to 1 or 0, respectively, when switch T i1 is on or off; and the phase currents can be obtained by inverter transfer function and filter impedance [18]. Modulation techniques, such as Sinusoidal Pulse Width Modulation (SPWM), Space Vector Pulse Width Modulation (SVPWM), Discontinuous Pulse Width Modulation (DPWM), Nearest Adjacent Vector Pulse Width Modulation (NSPWM), and so on, have different zero vector placement and different patterns of the piecewise dc-link current over one switching period, so it alters both the SHCs spectrum and the dc-link voltage ripple amplitudes. As discussed in [19], the dc-link SHCs RMS values are the same for different modulation strategies. In this paper, the SVPWM is used in all the subsequent derivation process.

Dc-link impedance impacts
The dc-link impedance has effects on the harmonic current distribution between the dc capacitors and front end. The typical three-phase VSI with the LOHs in ac currents considered in this paper is the APF system. As the APF system has only capacitors in the dc-link, the dc-link currents are the same as the capacitor currents, no matter what impedances the dc-link and the capacitors might have.
As for the dc-link harmonic current distribution in between multiple power stages, for example, in energy storage applications, the inverter is fed by the battery pack. Herein, it is to be verified that the capacitor bank impedance is much lower than that of the battery pack at high frequencies to absorb most of the dc-link harmonic currents as [3].
Moreover, the dc-link impedance effects on the dc-link current distribution were usually not considered or discussed in the literature. Nearly all the reference papers [1,2,[7][8][9][10]16] discussing dc-link currents or voltage ripples do NOT have dc-link impedance discussion. They all use the simple assumption that the capacitor currents are equal to the dc-link harmonic currents. As stated in [16], a well-designed dc-link capacitors bank needs to absorb most of the harmonic components.
The dc-link LOH currents distribution mechanism is a much more complicated issue. In some applications with multi-stages power conversion [20,21], the dc-link and capacitors impedances are to be considered to quantify the dc-link LOH currents distribution. However, the LOH currents distribution are dominated by multiple layers of control loops, which effectively alters the output impedance of the front end of the dc-link. However, these discussions are beyond the scope of the paper.

Capacitor design goals and power losses
In a typical dc voltage source design with strict voltage output tolerances, the voltage ripple would obviously be the primary design goal. However, in the industrial design practice of the inverter applications, the dc capacitor voltage ripple is usually the secondary design goal. Given the dc-link harmonic currents, the primary design goal is usually the thermal margin, which has to be satisfied with the proper capacitor losses, current ratings and the corresponding capacitance. Then the secondary goal is to verify that the capacitance selected in the first round of design is sufficient to keep the voltage ripple within certain limits. This is particularly relevant when the output currents have LOHs. Note that the inverter modulator has the dc voltage feedbacks, so that the output ac voltage can be accurately synthesised even with certain voltage fluctuation. Therefore, the dc voltage tolerance here is much looser than in a dc voltage source. Still, the voltage ripple limit should at least maintain the least sufficient dc voltage to synthesise the ac output voltage.
As for the primary design goal, the power losses are to be limited to get sufficient thermal margin. The power losses P C,rms are directly related to the dc currents in steady state [1][2][3][4][7][8][9][10] where R ESR represents the capacitor ESR resistance, and I C,rms is the capacitor current RMS value. A typical ESR versus frequency curve [12][13][14] is shown in Fig. 2. It is clear that the capacitor ESR stays almost constant with the frequencies >1 kHz and varies greatly at the frequencies below 1 kHz. Therefore, the capacitor power dissipation in (2) can be rewritten as where the first term and second term in (3) represent the power losses caused by the individual LOH currents and overall SHC RMS value in the dc-link, respectively.

Dc-link low-order harmonic currents
As the capacitor ESR varies significantly with the frequencies <1 kHz, the individual dc-link LOH current should be obtained to compute the power losses per harmonic order. A straightforward derivation process is proposed here to formulate the dc-link LOH currents induced by LOH or negative sequence currents on the ac side.
The ac side instantaneous power is expressed with the d-q quantities in the synchronous reference frame as The full expressions of three-phase voltages contain the LOH voltages and the full spectra of the switching harmonic voltages v isw_harm (i = a, b, c). The voltage equations after the d-q transformation are expressed as where M k + and M n − are the M-indexes of the harmonic of different sequence and order as defined by In (5) and all the subsequent equations, the superscript ' + ' and '−' represent the positive and negative sequence, and their respective harmonic orders are defined by the subscripts 'k' and 'n'. e as + is the first positive sequence voltages on the grid side and ω 1 t is its phase angle. φ vi (i = n or k) is the phase angle between the kth or nth harmonic and e as + . As the inverter output voltage and e as + are not exactly in phase, φ v1 represents this tiny phase difference.
When the grid voltages have LOHs distortion, a properly designed closed-loop controller of a grid-tied inverter outputs same amount of voltage harmonics in order to keep sinusoidal grid side currents. In APF applications, the current regulators add small amount of additional LOHs into the modulation signals to produce the required harmonic ac currents. As for the inverter filter inductance voltage drops, there are design rules such as in [22,23], where it is defined that a regular grid-tied inverter allows the inductance voltage drop at fundamental frequency <10%. The same rule is also applicable in an APF system. Therefore, compared to the fundamental frequency voltages output of a grid-tied inverter or APF, which are close to the grid voltages, the LOH voltages needed to cancel out the grid side low-order voltage harmonics or induce the LOH currents over the filter inductances are negligible.
By neglecting the LOHs in (5) and φ v1 , which is close to zero, the d-q voltages could be simplified as Unlike the voltages, the LOHs in ac currents could not be neglected as they are the dominant components in applications like the APF. Instead, current ripples (or SHC) are negligible in the ac currents expressions as defined by By substituting (7) into (4), the complete expression of instantaneous power on inverter ac side is obtained as The dc side instantaneous power could be seen as equal to (10) without considering power losses of the inverter. Hence, by dividing v c from (10), the dc-link current is expressed as The first term in (11) represents the dc-link LOH currents, which is the projection of three-phase currents onto the d-axis with a coefficient of 3M 1 + /4. So if ac currents are unbalanced and/or have LOHs, i d and i q are no longer constant and have a series of sinusoids at various frequencies as in (9).
The v dsw_harm and v qsw_harm in the second term of (11) represent the full spectra of the switching harmonic voltages in d-q reference frame. As spectra details of the dc-link SHC are not needed for capacitor loss computation, they will not be expanded for further derivation. By substituting (9) into the first term of (11), the LOH currents in the dc-link become The reason for the power expression derivation in the d-q reference frame is that it needs no trigonometric derivation. Only (4) and (7) are needed to express (11), into which (9) is to be substituted. Note that if (9) was derived from (8) by the normal d-q transform, it would have gone through the same lengthy process as in the stationery reference frame. However, by easy visualisation of the rotating vectors of the harmonics being projected onto the synchronous reference frame as in [24], (9) could be directly rewritten from (8). The three-phase APF design requirements include a group of the LOH currents to be injected into the grid. According to (12), the ac side kth positive and nth negative sequence currents induce the (k − 1)th and (n + 1)th currents in the dc-link. Instructively, if kn = 2, the vectors of the (k − 1)th and (n + 1)th dc-link LOH currents add up, which could either cancel out (φ k For example, when ac currents have the −1st, −5th, + 7th, −11th harmonics, the 2nd, 6th, 12th harmonic currents show up in the dc-link. For verification of (12), k is set as 1 and the average dc-link current expression could be written as which matches (6) in [1]. Due to the frequency-dependent ESR characteristics, the overall RMS expression of the dc-link LOH currents (including the average dc value) is not suitable for calculating the capacitor losses. However, it is needed to derive the dc-link SHC RMS value as in Section 6. So, it is obtained from (12) as where the fourth term under the square root sign represents the vector sum of the (k − 1)th and (n + 1)th dc-link LOH currents, when k-n = 2.

Dc-link low-order harmonic voltages
According to the Kirchhoff's Current Law (KCL) law and Fig. 1, the capacitor current can be written as As the impedance of the capacitor is infinity for the dc frequency, the average component of i dc is totally provided by the dc front-end current i DC . Also as discussed previously, the dc-link capacitor absorbs almost all the harmonic components (including LOHs and SHCs) in the dc-link. Then, the dc capacitor current can be rewritten as The resulting dc-link voltage ripple is calculated as Obviously, the dc-link voltage ripples have both the LOH Δv c_LOH and switching harmonic components Δv c_SHC . As the integral time of switching harmonic voltage is far less than the LOH voltage, the LOHs are the dominating component in the dc-link voltage and the switching harmonic voltage can be safely neglected.
As the i dc_LOH represent LOH currents in the dc capacitors current, it does not have the dc average component as in (12). The i dc_LOH is expressed as Then the LOH voltage in dc-link can be obtained by the integral of (18) as Obviously, the LOH voltage is independent of the modulation strategies. As the φ k + and φ n − are independent variables, the maximum value of the LOH voltage ripple {Δv c_LOH } max is

Dc-link current envelopes under low-order harmonics in ac currents
As illustrated in Fig. 3a, when the ac currents are sinusoidal and balanced, the dc-link current switching pulses has a cyclic pattern with a period of π/3. The way to derive the SHCs RMS value [1,7,8] is to express the RMS value of a switching cycle, and integrate it over a period of π/3 as The RMS values from (21) include the contributions from both the dc average value and PWM switching harmonics. However, (21) is no longer valid, as the LOHs in the ac currents reshape the dc-link current patterns significantly. Figs. 3b-d show the various patterns of the dc-link currents, when ac currents contain the −1st component, the combination of the +1st and −4th harmonics, and the combination of the −5th and + 7th harmonics, respectively. Their repetitive periods are π, 2π and π/3. Considering all possible LOHs combinations in ac currents, the RMS expression of the dclink current per switching cycle should be integrated over a fundamental cycle of 2π.  Fig. 4 shows the vector space of a three-phase VSI, and Table 1 gives the relationship between the dc and ac currents for each vector. Noted that in the grid-tied applications, the vector of the grid voltages is usually aligned with the d-axis and the phase angle ω 1 t of the reference vector V s is defined in Fig. 4.

RMS value of the dc-link switching harmonic currents
The dc-link current RMS expression per switching cycle varies in six sectors, so that the dc-link current RMS expression of a fundamental cycle is written as (see (22)) , where d i_j represents the duty ratio of the active vector V j when the reference vector V s is inside the sector i By substituting (8) and (23) into (22), after complicated trigonometric derivation, the generalised dc-link current RMS expression is formulated by (24)-(29). The RMS result as in (24) has five parts, which is further defined by (25) The first part of (24) stems from the kth positive sequence harmonic in ac currents as defined by Equation (25) could be further simplified by eliminating the second term, when k ≠ 3m-2 (m = 1, 2,…). The second part of (24) stems from the nth negative sequence harmonic in ac currents as defined by Equation (26) could be further simplified by eliminating the second term, when n = 3m-1 (m = 1, 2…). The third part of (24) stems from any two positive sequence LOHs (k 1 th and k 2 th) in ac currents as defined by (see (27)) . Only when k 1 + k 2 = 6m + 2 (m = 1, 2, 3,…) or k 1 -k 2 = 6m (m = 1, 2, 3, …), (27) has non-zero values.
It should be noted that (24)-(29) represent the overall RMS values including dc average, LOHs and switching harmonics in the dc-link current. To obtain only the RMS value of SHC, (14) needs to be eliminated from (24) as Equations (24)-(30) are a complete set of generalised tools to analytically obtain the RMS value of the dc-link SHC.

Equations compatibility with special cases
Equations (24)-(29) could be very much simplified when applied to special cases, such as grid-tied inverter applications, where only the first-order positive sequence component exists in ac currents. By setting k = 1 in (25), the resulting dc-link current RMS value expression as in (31) exactly matches (7) Table 1 Relationship of the dc-link current and line current Vector

Equations simplification for practical design
In an APF design, a set of ac side LOHs amplitudes are usually given as requirements. However, it is impractical trying to obtain the worst case RMS value of the dc-link SHC and LOH currents by traversing the full range of phase angles of each individual LOH. Therefore, simplifications are made here to facilitate the design practice.

SHC RMS simplification for the worst case:
It is discovered that most of the phase angle dependent terms in (25)-(29) are negligible due to their overwhelmingly large denominators, except for the cases when k = 1 in (25) or k-n = 2 in (29). Therefore, the overall dc-link current RMS expressions (24) where the second term under the square root symbol is obtained by setting k = 1 in the second term of (25), and the third term is obtained by setting k-n = 2 in the first term inside the curly brackets in (29).
By removing the RMS values of the LOHs and the dc average as defined by (14), the simplified RMS expression of the dc-link SHC could be obtained from (34) where the third term only exist when the LOHs in ac currents come in pairs and satisfy k-n = 2. When this does occur, I dc_switchRMS would vary noticeably with the phase angles. For practical design, only its maximum value is actually needed. Herein, once the Mindex or dc voltage is given, the maximum I dc_switchRMS is obtained if the third term in (34) satisfies φ k + = φ n − (0.98 < M 1 + < 1.15) or |φ k + -φ n − | = π (0 < M 1 + < 0.98). Hence, the maximum I dc_switchRMS is derived from (34) as Apparently, (35) is very easy to use even for the design cases with a large group of LOHs on the ac side such as the 5th, 7th, 11th, 13th and so on. Obviously, it would be impractical for the conventional methods such as the double Fourier series analysis or numeric simulations to obtain the worst case rating results out of numerous dc-link current patterns varying with the infinite combinations of the LOHs phases angles.

LOH currents RMS for the worst case:
Besides the dclink SHC RMS, the individual dc-link LOH currents also need to be considered in the rating of dc-link capacitors. It is clear to see from (12) that the kth positive and nth negative sequence current on the ac side would induce the LOH current at the same frequency in the dc-link when k-n = 2. The RMS value of their vector sum varies with the LOH phase angles and the worst case is expressed in Table 2. When k-n≠2, the overall RMS values of the (k − 1)th and (n + 1)th LOH currents in the dc-link are fixed despite their phase angles combinations.

Overall worst case for capacitor power losses with both SHCs and LOH currents RMS:
To obtain the overall worst case of capacitor power losses, the RMS values of both the SHCs and LOH currents are to be considered. In (36), the two terms I SHC_Vary and I LOH_Vary are extracted from (34) and from Table 2, respectively. Only when the kth positive and nth negative sequence harmonics (k-n = 2) in the ac currents co-exist, the two terms I SHC_Vary and I LOH_Vary are non-zero. Moreover, both terms vary with the LOHs phase angles combinations and determine the worst cases of the SHC RMS and LOH currents RMS. For the full Mindex range, the worst cases phase angles combinations are listed in Table 3 I SHC_Vary = M 1 From Table 3, it is clear that the RMS values of the SHCs and LOH currents could reach their respective maximum at the same time (when |φ k + -φ n − | = π) for the M-index range of [0, 0.98]. However, as for the M-index between 0.98 and 1.15, if one reaches its maximum, the other is at its minimum. So to obtain the worst case for capacitor power losses, the maximum values of I SHC_Vary and I LOH_Vary are symbolically expressed from (36) and Table 3, and then plotted and compared in Fig. 5. It is clear that the maximum value of I LOH_Vary (when |φ k + -φ n − | = π) is larger than that of I SHC_Vary (when φ k + = φ n − ). Moreover, the ESR values for LOH frequencies are greater than the ESR value at the switching frequencies. Therefore, the maximum of I LOH_Vary (when |φ k + -φ n − | = π) corresponds to the worst case capacitor power losses when the M-index is between 0.98 and 1.15.
It is then concluded that, for the full M-index range, the worst case for capacitor power losses is always when |φ k + -φ n − | = π. Fig. 6 shows the flow chart of the worst case design process for the capacitor power losses.

Practical design case study
In the following two quantitative design case studies of an APF dclink, the grid line-to-line voltage is 400 V and their requirements of the maximum LOHs in ac currents are shown in Tables 4 and 5, respectively. It should be noted that the phase angle of each LOH in ac currents varies within [0-2π], while the phase angle of the current of the fundamental frequency and positive sequence is fixed as π/2 in the APF system. In both design case studies, the same electrolytic capacitor B43504A5397M000 (TDK EPCOS) is used, and 60°C is assumed as the ambient temperature inside the cabinet. The capacitor ESRs are based on the normalised characteristic curves as in Fig. 7.  Figs. 8a and b, it is obvious that the plot contours and peaks from (34) well match those from the complete equations set and the error percentage is below 5%. So that the simplified (34) and its variant (35) is very efficient in obtaining the maximum RMS value of the dc-link SHC out of all possible phase angles of the ac currents LOHs with given amplitudes.
Then, the worst case LOH currents (when |φ 7 + -φ 5 − | = π) are computed and listed in According to the dc-link LOHs and SHCs in the worst case as in Table 6, the dc-link capacitor bank is designed with 900 V peak rating with two 450 V-rated B43504A5397M000 in series and eight branches in parallel. The normalised capacitor losses at 100, 600 Hz and the switching frequencies for individual capacitors and the capacitor bank are computed and listed in Table 6.
The normalised losses of the capacitor bank and the individual capacitor are computed as 100.83 and 6.30 (M 1 + = 1.15), respectively. While with the maximal permissible current of 4.86 A (peak) at 60°C as given by the datasheet, the allowable normalised individual capacitor loss is 11.81. Hence, there is sufficient design margin under the worst case operation point.

Comparative design case study:
In order to better clarify the benefits of the proposed method, two APF dc capacitor design cases are compared. As defined in Table 5, the base case only considers the fundamental frequency component in the ac currents (reactive power compensation), while the comparative case also considers the fifth negative sequence component. In both cases, the maximum values of LOHs and SHCs RMS can be computed according to the design flow path 1 in Fig. 6. The computed results are listed in Table 7.
In case 1, the APF dc-link capacitor rating is only determined by the SHC RMS values. To have sufficient thermal margin, the dc-link capacitors are designed with 900 V peak rating with two 450 V-rated B43504A5397M000 in series and two branches in parallel. From Table 7, it is clear that the normalised losses of the capacitor bank and the individual capacitor are computed as 17.1 and 4.3 in case 1, respectively. While with the maximal permissible current of 4.86 A (peak) at 60°C as given by the datasheet, the allowable normalised individual capacitor loss is 11.81. Hence, there is sufficient design margin under the worst case operation point for case 1. Then the capacitor voltage ripple is verified. The maximum dc-link switching harmonic voltage ripple is only 0.52 V.   However, if the same capacitors are used in case 2, the LOHs in the ac currents not only increase the capacitor power losses significantly, the SHC RMS values are increased as well. The normalised losses of the capacitor bank and the individual capacitor are 52.5 and 13.1, respectively. Therefore, the capacitors designed without considering LOHs would be over-heated and have premature failure. Moreover, it is computed with (18) that, the peak dc voltage ripple is increased from 0.52 to 14.2. Obviously, the proposed method provides more accurate capacitor losses estimation and ratings design, when the output ac currents contain LOHs.

Experimental validation
To validate the proposed analytical models under any harmonic currents conditions, a flexible three-phase grid-tied inverter prototype is developed in order to freely inject combinations of harmonic currents of different harmonic orders, sequences, phase angles and amplitudes into the ac grid, so that the dc-link current could be conveniently evaluated under any LOH currents, such as an APF compensating a required set of harmonic currents. The experimental setup is as shown in Fig. 9. Therein, three-phase high power density 15 kVA inverter assembly was constructed using multi-layer packaging design. The dc-link current is measured in specially fabricated laminated busbars as in Fig. 9. An easy to use graphic user interface is programmed to control the grid-tied inverter outputs via CAN data-link and monitor its status as in Fig. 10. The dc voltage is set at 570 V. The three-phase grid side voltage after the transformer is set at 240 V. The LCL filter and dclink capacitor parameters are listed in Table 8.
High-performance closed-loop control based on PI controller paralleled with multiple PR controllers in d-q reference frame was implemented and well-tuned to inject the sinusoidal LOH currents into the grid, particularly at the higher harmonic orders. So the accuracy of the dc-link current measurements is not affected by unexpected harmonics. Moreover, the PLL algorithm based on multiple reference frames guarantees the accuracy of the real-time phase angle extraction despite the grid voltage harmonics. The  closed-loop control is implemented on a digital signal processor (TMS320F28335). The PWM switching and control loop frequency was set to 10 kHz. As the simulation results match the experimental waveforms very well, only experimental results are provided to validate the analytical methods. Meanwhile, the oscilloscope data were exported for FFT analysis to compare with the computational results of the LOHs by (12) and SHC RMS values by (24)-(30).
Interesting discoveries were made in Fig. 11. From Fig. 11b, although multiple LOHs were present in the ac currents, there is nearly no dc-link LOH current. This is because the 6th harmonics induced by −5th and +7th LOHs in the ac currents cancelled out. In Fig. 11c, the 6th harmonics induced by −5th and +7th LOHs in the ac currents actually added up.

Error analysis
Although the experimental results of the dc-link LOH currents and SHC RMS values well matched the computational results, there are still slight differences among them. Tables 9 and 10 list the error percentages between the experimental and computation results for the LOH currents and SHC RMS values, respectively. Note that the total RMS value of all the LOH currents computed with (14) as listed in Table 9 is just used to verify the overall accuracy, instead of being used for capacitor losses computation. It should also be noted that two special cases are labelled as 'not relevant' in Table 9. In these two special cases, the LOHs in the dc-link should nearly cancel each other. However, in practical tests, small amount of LOHs exist, due to the non-ideal grid voltages as analysed later in this subsection. Therefore, the LOHs error percentages for the two special cases are not relevant, as the comparison base is too small. Even though the error percentage is well within the design margin, it is very instructive to explain these differences in detail.
The LOHs in the inverter output voltage, SHC ripples in the ac current and power module losses are the three main reasons for these differences. For simplicity, they are safely neglected when establishing the computation models for the dc-link LOH currents and the SHC RMS value.
Suppose that the LOH voltages and SHC ripples in the ac current are considered during the derivation, the inverter output voltage as in (7) and (9) is redefined as where the i dsw_harm and i qsw_harm represent the SHC ripples in the ac currents. Then the instantaneous power on the inverter ac side is obtained by substituting (37) and (38) into (4) as By dividing the dc voltage v c from (39), the dc-link current can be expressed as in (40). Compared with the dc-link current expression in (11), the detailed dc-link current expression as in (40) has five extra components. The first extra component is the second term in (40), which indicates that the switching ripple voltages together with SHC ripples introduce extra SHCs in the dc-link. The second and third extra components are the third and fourth terms in (40), which indicates that the LOH voltages together with SHC ripples in the ac currents introduce extra SHCs in the dc-link. Therefore, the LOH voltages and SHC ripples in the actual ac current would lead to additional SHC RMS values in the dc-link in reality. Moreover, by neglecting the power module losses, the computational results will be even smaller than the reality. From Tables 9 and 10, the deductions above are verified that the computation results are always lees than experimental results. However, the computation results error percentage is reasonably low and within 9%, which can be safely absorbed by the design margin. Therefore, the LOH voltages, SHC ripples in the ac current and the power module losses can be safely neglected in deriving all the computation models in this paper The fourth and fifth extra components are the fifth and sixth terms in (40), which indicates that LOH voltages introduce additional dclink LOH currents. The interaction between the kth positive harmonic voltage and nth negative harmonic current or nth negative harmonic voltage and kth positive harmonic current would induce (k + n)th LOH current in the dc-link. k 1 th positive harmonic voltage and k 2 th positive harmonic current would induce (k 1 -k 2 )th LOH current in the dc-link. n 1 th negative harmonic voltage and n 2 th negative harmonic current would induce (n 1 -n 2 )th LOH current in the dc-link. For example, when the ac currents consist of 1st, −1st and +7th harmonics, besides the dominating positive sequence fundamental frequency component, the inverter output voltage also has small amount of the −1st and +7th harmonics. Therefore, besides the 2nd and 6th harmonic currents in the dclink, it is deduced from (34) that the 8th harmonic current is also present in small quantities in the dc-link. This interesting phenomenon can also be observed from the experimental results as shown in Fig. 11f. More interestingly, the experimental results in Fig. 11 have small amount of the dc-link LOH current that are not present as deduced from (40). This is obviously due to the miscellaneous grid voltage harmonics in the practical tests.