Operation and control design of an input-series-input-parallel-output-series conversion scheme for offshore DC wind systems

— Irreversible electroporation for disinfection applications involve exposing the specimen cell-membrane to a pulsed electric field in order to kill harmful microorganisms. High voltage (HV) pulses, of relatively short durations in range of few micro-seconds, are generated across the sample chamber. The HV pulse specifications such as: voltage magnitude, waveform, repetition rate, and duration differ according to the conditions of the sample being processed. This paper proposes a new step-up power electronic converter topology for generating the required HV pulses from a relatively low input voltage. The converter consists of two main stages; the first stage is responsible for boosting the input voltage to the desired level using input-parallel/output-series connected dc/dc modules while the second stage forms the required HV pulses with the proper magnitude, duration and repetition rate using modular multilevel converter sub-modules. The proposed topology is able to produce the HV pulses with controlled voltage and current stresses across the employed semiconductor switches and diodes, hence, it can be implemented with the market-available semiconductor technology. Mathematical analysis of the proposed topology is developed and MATLAB/Simulink simulation results explore operational conditions. Experimental results from a scaled-down prototype validate the functionality of the proposed system.

It is a good candidate for chlorination in water disinfection applications [3]. For a successful IRE process, the strength of the applied electric field, typically ranges between 2.5 kV/cm to 12 kV/cm, according to the type of the harmful microorganism and the application [4]. Applying HV pulses in kV range and microsecond range should deactivate the harmful microorganisms in the water under treatment [5]. Therefore, HV pulse generators (PGs) are the pillar of IRE application, and should meet several challenging aspects such as modularity, scalability and flexibility [6]. Power electronics based PGs superseded classical PGs such as Blumlein lines, pulse forming networks and Marx generator aiming to meet these aspects [7].
The existing modularity with modular multilevel converter (MMC) sub-modules (SMs) has been harnessed to generate HV pulses for IRE [8]- [14]. Not only conventional rectangular pulse-waveforms can be generated by MMC based PGs, but a wide range of pulse-waveforms is also possible [5] and [10]. The majority of these topologies require an HVDC input supply and the obtained pulse peak-voltage is that of the input HVDC level. They require balancing of the individual SM capacitor voltages, ramping the HVDC input at start-up/shutdown, and protection against HVDC side faults. An exception for obtaining stepped-up voltage pulse from low voltage (LV) DC input are [13] and [14], where several series connected MMC SM capacitors are charged sequentially, then connected in series across the load to discharge. However, the voltage step-up and the pulse repetition frequency are dependent on the number of SMs and the charging process is achieved via resistors in [13] and via resistive-inductive branch in [14].
Solid-state Marx generators are introduced in the literature to provide flexibility compared with the classical Marx generator [15]. However, the ratings of the utilized switches are not identical in order to cope with their respective voltage stresses [13]. In [16], several stages of capacitor-diode voltage multipliers are incorporated to generate HV pulses from a LVDC input, but a HV switch is required to chop the pulse across the load, hence, series connection of switches is not avoided. In [17], an isolated forward converter with a step-up transformer is proposed, however, extending the topology to more than 5 kV requires series-connected semiconductors. Also, the core reset of the transformers is problematic and increasing the number of transformers increases the leakage inductance which limits the generated pulse-duration. In [18] A In this paper, a unipolar step-up PG (SUPG) fed from a LVDC supply is proposed based on isolated inputparallel/output-series (IPOS) voltage-boosting modules (VBMs) and MMC-SMs. The VBMs are isolated via nanocrystalline core based transformers which have low leakage and magnetizing inductance and are suitable for highfrequency operation [19]- [20]. The high voltage step-up is obtained from three mechanisms: the number of utilized VBMs, the voltage conversion ratio of the individual VBM, and the turns ratios of the step-up isolation transformers. The generated HVDC from connecting the output of the individual VBMs in series is chopped by employing two arms of series connected MMC-SMs across the load, hence, the SMcapacitors actively clamp the voltage across the semiconductor switches [21]. High repetition pulse rates are possible, independent of the employed number of VBMs or MMC-SMs. Mathematical modeling of the proposed PG is introduced while the methodology of selecting parameters is detailed. SUPG performance is assessed via Matlab/Simulink simulations and scaled-down experimentation.

II. BASIC VOLTAGE BOOSTING MODULE OF THE SUPG
The basic VBM of the proposed SUPG is shown in Fig. 1. Unlike conventional DC-DC converters [22], the secondary side switches Sx1 and Sx2 are not necessarily working in a complementary manner. The switching pattern for the VBM devices and the developed circuit configurations are illustrated in Fig. 2. The VBM operation can be explained as follows, i) During period t1, (Fig. 2b) the input current Iin increases and Lin charges, the load is connected to an open circuit, and the voltage of capacitors Cc1 and Cc2 are constant. The differential equations that describe the circuit in this period can be expressed as ii) During t2, (Fig. 2c) the input current Iin continues to increase while the load is connected to capacitor Cc2 in series with Sx1. This leads to a sudden voltage pulse across the load. Capacitors Cc1 and Cc2 discharge and their voltages decrease.
The differential equations that describe the circuit in this period are: iii) The same operation is repeated as in period t1. iv) Iin decreases and Lin discharges into the capacitors while the voltages Vc1 and Vc2 increase. No voltage is impressed across the load R, see Fig. 2d. The differential equations that describe the circuit in this period are in in c1 c 2 in in in The voltage and current waveforms of the basic VBM during one complete cycle of pulse generation are depicted in Fig. 3. Fig. 3a shows the current through the input inductor. The current through Cc1 and Cc2 are shown in Fig. 3b, while the voltage waveforms across Cc1 and Cc2 are shown in Fig. 3c along with the resultant VBM terminal voltage . The isolation transformer's primary and secondary voltages are shown in Fig. 3d. Finally, the generated voltage pulse is shown in Fig. 3e.
Assuming the pulse duty ratio is small with respect to the main duty ratio D and solving equations (1) to (3), the values of the circuit currents and voltages are    Arm1 is formed of m1 conventional half-bridge SMs, while each of the m2 SMs of Arm2 are formed with two diodes, a switch, and a capacitor.

III. STRUCTURE AND OPERATION OF THE PROPOSED SUPG TOPOLOGY
The basic operation of the proposed SUPG can be described as follows: with the operation sequence shown in Fig. 2a, switches S1, S2…SN are turned ON during t1, t2, and t3 and OFF otherwise, allowing the input inductors to energise. During t2, the lower switches of the SMs in Arm1 (SA1jy where, ) are turned ON, that is bypassed while the lower diodes in Arm2 (DA2ky where ) are reverse biased, thus, a voltage difference VAB is impressed across the load. During t4, the lower diodes of the SMs in Arm1 (DA1jy where ) and Arm2 conduct a charging current of Iin/n/N through the N charging capacitors Cc2.
Diodes (D1, D2,…DN) are installed to prevent unintended series connection of secondary sides of the isolation transformers due to any delay in primary side switches gate signals. Thus based on the VBM in section II and assuming that the component values of the N VBMs are identical, the average voltages of the voltage boosting stage can be calculated as where . The input inductor current of the individual VBMs are: The primary and secondary transformer voltages are: During t2, the midpoint 'm' is connected to the upper point 'A' through the semiconductor switches SA1jy. Consequently, a voltage pulse with duty ratio and magnitude Vp is impressed across the output load R. The voltage peak is: As concluded from (8), the output voltage is amplified by three mechanisms: (i) the N utilized VBMs basic cell converters, (ii) transformer turns ratio n, and (iii) the individual VBMs duty ratio D. The average capacitor voltages of the Arm1 and Arm2 SM-capacitors are: In the next section, a design process is presented for SUPG system parameter selection.

IV. PROPOSED SUPG PARAMETERS SELECTION
The main merits of the proposed SUPG are that of obtaining high voltage output pulses with the readily available semiconductor technology and a relatively low input voltage; thus modularity, scalability and flexibility features arise. Starting from the load side, the voltage and current stresses of the Arm1 SMs are: The current stresses of the clamping switches and diodes (SA1jx and DA1jx) are relatively small and hence, switches with lower current ratings can be used. Similarly, the voltage and current stresses of the Arm2 SMs are: Assuming a modular design and ' ' and ' ' are the voltages and current derating factors of the Arm SMs devices, the number of Arm1 SMs (m1) is: where, VrA1 and IrA1 are the rated voltage and current of Arm1 devices respectively. The number of Arm2 SMs (m2) is: where, VrA2 is the rated voltage of Arm 2 devices. As they conduct the charging currents of the clamping capacitors, the current ratings of Arm2 SM devices can be small compared to Arm1 device ratings. Similarly, assume that ' ' and ' ' are the voltages and current derating factors of the devices in the VBMs, the number of the boosting modules (N) is: The maximum duty ratio Dmax is related to the voltage stresses across the module's devices,viz.: 'VrM'and 'IrM'are the rated voltage and current of the VBM devices.
The passive element values are selected in order to keep the ripple current and voltage within certain ranges. The ripples across the different elements can be calculated from [23], [24] as: Defining the ripple factors as: Accordingly, the passive element values should be kept as: Because the energy transfer is conducted through the boosting modules capacitors Cc1 and Cc2, the SMs capacitance values of Arm1 and Arm2 can be relatively small. The upper switches in SM cells (SA1jx and SA2kx) are responsible for discharging the capacitors when their terminal voltages increase above the desired range for any unexpected reason in order to ensure balanced voltages across the cells. Based on the previous analysis, the parameters of the proposed system are as in Table I for generating a HV pulses of 10 kV peak. For modular design, all the transformers are wound for isolation and clearance voltage higher than the peak value of the pulses as this stress voltage is experienced by the cell at the highest potential. In addition, if the ground point is moved to the point m, the required insulation voltage will drop to half the output voltage, without affecting the main operation of the converter. Fig. 4, with the values in Table I, illustrate the operation of the proposed HV topology.   100V/div; 25µs/div 100V/div; 5µs/div 250mA/div; 50µs/div 250mA/div; 50µs/div 50V/div; 25µs/div 1A/div; 25µs/div 1A/div; 25µs/div 70V/div; 25µs/div   5 shows the load voltage pulses with = 0.05 (that is the generated pulse time is 5µs) and when the repetition rate of the output train pulses is equal to the switching frequency of the boosting modules (fs= 10 kHz). Nevertheless, the generated pulses repetition rate is independent of fs and can be varied according to the application.

MATLAB/SIMULINK simulations of the SUPG in
The key performance current and voltage waveforms at different parts of the SUPG are depicted in Fig. 6. Fig. 6a shows the total input current drawn from the input supply, while the first VBM current is shown in Fig. 6b with one-fifth the total input current as expected. The capacitor voltages of the primary, Vc11, and secondary, Vc12, sides of the first VBM are shown in Figs. 6c and 6e, respectively. The currents through Cc1 and Cc2 are shown in Fig. 6d and 6f. The terminal voltage VAB is shown in Fig. 6i.
The voltages across the primary (VT11) and secondary (VT12) of the first VBM are shown in Figs. 6g and 6h, respectively, which confirm the voltage second balance for the transformer. The individual SM voltages in Arm1 and Arm2 are explored in Figs. 7a and 7c, respectively. As aforementioned, the generated output pulse train repetition rate not necessarily the same as the VBMs switching frequency. Therefore, Fig. 7f shows the output voltage pulses with repetition rate of 5kHz and pulse duration of 20µs when the boosting modules switching frequency is fs = 10 kHz.
During the starting of the proposed converter, the duty ratio D can be increased gradually following a first-order capacitive circuit manner until it reaches the final steady-state value in order to ease the charging process of the SM capacitors and avoid exceeding the acceptable limits.

VI. EXPERIMENTAL RESULTS
To show operation of the proposed system and validate the mathematical analyses and simulation results, a scaled-down hardware prototype with the parameters in Table II and  controlled with Texas Instruments TMS320F28335 DSP is constructed. Fig. 8a shows a train of the experimentally generated output voltage pulses with 500V pulse-peak, 10 kHz repetition rate and 2.5 s pulse duration. A zoomed view for a single pulse is depicted in Fig. 8b. Figs. 8c and 8d show the total input current drawn from the input supply and the first VBM drawn current, it is clear that since two VBMs are utilized, the first VBM draw one-half the total input current. The first SM-capacitor voltage in Arm1 and Arm2 are explored in Fig. 8e. The current through the first SMcapacitors (Cc1 and Cc2) are shown in Figs. 8f and 8g, respectively. Moreover, the voltages across the primary (VT11) and secondary (VT12) of the first VBM are shown in Fig. 8h. To show the dynamic performance of the proposed pulse generator, Fig. 8i shows the input current drawn from the LVDC supply as well as the created output voltage pulses across the load from the starting moment.
Finally, the flexibility of generating wide range of different pulse repetition rates and pulse durations are explored in Fig.  9. With pulse duration of 10 s and repetition rate of 10 kHz,  Fig. 10.

VII. CONCLUSION
This paper proposed a new HV pulse generator topology for electroporation applications. The topology employs inputparallel/output-series boosting modules in order to permit the use of a low voltage dc input supply. The amplified HV voltage is chopped with two MMC arms incorporating small clamping capacitors. Unlike many step-up HV generators in the literature, the boosting module capacitors of the proposed topology are charged simultaneously, allowing operation with a wide range of pulse widths and repetition rates. The simultaneous charging and discharging of VBMs implies that their switch gate signals are common to controller, consequently the control burden is low. The carried out simulation results showed the operation of the proposed topology, where the input LVDC is amplified by one hundred times using only five VBMs. Scaled-down experiment confirmed the feasibility of the proposed topology when the LVDC input is amplified by ten times using only two VBMs. Despite the obtained high amplification gains, the stresses on the utilised components are equal and acceptable. Thus, the proposed modular configuration allows the use of the marketavailable voltage and current ratings semiconductors. Moreover, the proposed topology can be extended to generate bipolar voltage pulses, which may be required for some irreversible electroporation applications, with two additional MMC arms across the treatment chamber.
Finally, the main contribution of the proposed SUPG topology can be summarized as:  It achieves an HV pulse voltage by employing a three-folded stepping-up technique (VBMs duty ratio, step-up transformers turns ratio and series connection of the VBMs) from the LVDC input supply.  It avoids using HV switches and series connection of switches to chop the generated HVDC voltage.  It has the ability of generating unipolar/bipolar rectangular pulses with flexible voltage peak, repetition rate and pulse duration.  It does not require voltage sensors.