Soft-Switching Operation of the Dual-Interleaved Boost Converter over all Duty Ratios

: To extend the operating range of the snubber assisted zero-voltage and zero-current transition (SAZZ) dual-interleaved boost converter beyond its inherent soft-switching limit of D=0.5, a resonant pulse transformer is proposed instead of the resonant inductor. The 1:2 turns ratio of the transformer ensures full discharge of the snubber capacitor at all duty ratio values to facilitate zero-voltage zero-current switching (ZVZCS) at turn on of the main switching devices. The effectiveness of the topology has been confirmed by SPICE simulation and demonstrated by a 20 kW SiC MOSFET converter. The prototype operated at 20 kW, 112 kHz, 320-600V achieving 98.7% efficiency and achieved 98.2% efficiency at 6 kW. Taking the additional losses in the auxiliary circuit into account, the switching losses at 20 kW are reduced by 74% compared with hard-switching operation, representing a 54% reduction in overall losses. of the conventional SAZZ topology so that the converter’s soft-switching region can be extended. The modified topology ensures soft-switching operation for the whole duty ratio range. The turn on losses of the main devices are eliminated and the turn off losses are significantly reduced as the energy stored in the device output capacitances and other parasitic capacitances is recovered. The experimental results show the superiority of the proposed topology over the previously published SAZZ circuits as zero-voltage-zero-current-switching turn on can be achieved for the full range of duty ratios without additional control complexity. Finally, the loss breakdown of the converter confirms the superiority of soft-switching over hard-switching operation.


Introduction
To achieve high power-density in multi-kW DC-DC converters, wide band gap devices such as SiC MOSFETs are being considered. SiC devices enable high-frequency operation, which potentially reduces the size of bulky passive components, however, switching losses and EMI issues can still limit the achievable operating frequency [1]. Soft-switching techniques can remove most of the switching losses, and also have the potential to reduce EMI [1]. A soft-switched SiC converter was proposed in [2] which combined the benefits of the dual-interleaved boost converter and interphase transformer (IPT) with those of the snubber assisted, zero-voltage and zero-current transition (SAZZ) converter. The prototype demonstrated a 50% reduction in switching losses compared with hard-switched operation, and achieved 98% efficiency when operating at 12.5 kW, 112 kHz and 400 V.
Soft-switching circuits including different SAZZ topologies for multi-kW DC-DC converters have been widely discussed in literature recently [3][4][5][6][7][8][9][10][11][12][13]. Furthermore, series resonant converter (SRC) topologies have been reported in [3][4][5][6] for multi-kW level transport applications with isolation requirements. Although all the prototypes showed above 97% efficiency at their rated conditions, the major drawbacks of these topologies are bulky high frequency isolation transformers and the limited softswitching operating range. A zero-voltage switching (ZVS) boost converter was proposed in front of the SRC converter in a two-stage system [7] to increase the range of soft-switching operation. Although the fixed input voltage improved the soft-switching load range of the SRC converter, the limited ZVS range of the front-end boost converter reduced the overall soft-switching range of the whole converter. Also the converter had a modest efficiency of 84% at the rated condition of 2.4 kW due to the two-stage conversion.
Another modified SRC topology was proposed in [8] using more than twice the number of devices in a conventional full bridge SRC to reduce the size and loss in the isolation transformer. However, the circuit complexity and increased conduction losses are significant drawbacks [8].
The SAZZ converter has been studied by several authors for applications where isolation is not required. Single and multiphase versions have been reported in [9][10][11][12][13] utilizing both Si and SiC devices, with the SiC prototypes providing higher efficiencies. Previous research also illustrated how interleaved versions of the circuit can achieve higher power density [11,13].
A limitation of the SAZZ converter is that soft-switching is only possible if the duty ratio (D) is greater than 0.5 as when D<0.5 the snubber capacitor cannot be fully discharged due to insufficient voltage difference between the output and input. One way to resolve the issue is to replace the main diodes with MOSFETs operating as synchronous rectifiers, thereby allowing sufficient current to be established in the resonant inductor to facilitate soft-switching when D<0.5 [14]. Apart from the additional transistors, this solution requires complex switching control and may result in increased conduction losses compared to hard-switching due to the extended conduction of the additional transistors. Another approach is to use the reverse recovery of the upper diode to develop sufficient current in the resonant inductor [15].
However this solution requires a slow diode which restricts the choice of snubber capacitor. The design was also optimised only for low-power (250W), D<0.5 operation. Some other techniques exist to extend the soft-switching region such as using a capacitive voltage divider in the auxiliary circuit [11,16], or using an additional capacitor to store and recycle the resonant energy [17]; in both cases balancing the capacitor voltages is a challenge, and the control becomes more complex.
In this paper a small pulse transformer with a 1:2 turns ratio is used to replace the resonant inductor of the conventional SAZZ topology so that the converter's soft-switching region can be extended. The modified topology ensures soft-switching operation for the whole duty ratio range. The turn on losses of the main devices are eliminated and the turn off losses are significantly reduced as the energy stored in the device output capacitances and other parasitic capacitances is recovered. The experimental results show the superiority of the proposed topology over the previously published SAZZ circuits as zero-voltage-zerocurrent-switching turn on can be achieved for the full range of duty ratios without additional control complexity. Finally, the loss breakdown of the converter confirms the superiority of soft-switching over hard-switching operation.

Circuit description and operation
The converter topology is a modification of the SAZZ dual-interleaved boost converter with interphase transformer (IPT) [2] as shown in Fig. 1. The resonant inductor is replaced by a pulse transformer, X a with 1:2 turns ratio. One additional diode (D aux3 ) and a RC snubber circuit are also added to the new configuration to ensure orderly operation.

Fig. 1. SAZZ dual-interleaved boost converter with resonant pulse transformer (grey section replaces the resonant inductor [2])
The soft-switching operation relies on the resonance between the leakage inductance, L leak of the pulse transformer and the snubber capacitors, C S1 and C S2 , which may be formed by the main device output capacitances. The auxiliary switching devices Q aux1 and Q aux2 are turned on just before the turn on of Q 1 and Q 2 , allowing the snubber capacitors to be discharged by resonating with the leakage inductance In the conventional SAZZ topology the snubber capacitor and the auxiliary inductor resonate with the full input voltage, which prevents the snubber capacitors from being fully discharged for D<0.5. In the proposed circuit only half of the input voltage is present in the resonant loop, so the snubber capacitor can be fully discharged at all duty ratios. Therefore, by halving the voltage in the auxiliary circuit, the pulse transformer extends the soft-switching operating range. Finally, the additional RC snubber in the auxiliary circuit damps the parasitic ringing induced by the turn off of D aux3 .

Analysis of the topology and operating waveforms
Ideal steady-state waveforms for the converter are shown in Fig. 2 for both D<0.5 and D>0.5 conditions, which are exactly same as the waveforms in a conventional dual-interleaved boost converter.
To ensure interleaved operation of the circuit, the gate pulses for Q 1 and Q 2 are mutually delayed by half a cycle, T/2. To illustrate the soft-switching operation the converter, equivalent circuits and ideal waveforms considering a perfectly coupled IPT are shown in Fig. 3 and Fig. 4, respectively for D<0.5. Fig. 3 identifies the main eight sub-periods, T0-T8 during one half of the switching period and Fig. 4 shows the corresponding main current and voltage waveforms. The RC snubber circuit is neglected in both figures to simplify the analysis. The converter operation is symmetrical as the main switching devices, Q 1 and Q 2 operate with a half-cycle delay. Fig. 4(a) shows the waveforms for the converter over a half switching cycle and Fig. 4(b) shows an expanded view of the ZVZCS turn on transient. Although Fig. 3 and 4 correspond to the D<0.5 condition, the soft-switching process is similar for the D>0.5 conditions. Here, V gsQ1 , V gsQ2 , V gsQaux1 and V gsQaux2 are the gate voltages of the main and auxiliary switches, V com is the IPT midpoint voltage, V L1 is the voltage across the main inductor, V dsQ1 and V dsQ2 are the drain to source voltages of the main switching devices; I in and I L1 are the input and main inductor currents respectively, I La and I Lb are the IPT winding currents, I dsQ1 and I dsQ2 are the main switch currents, I CS1 , I CS2 , I aux1 and I aux2 are the snubber capacitor and auxiliary switch currents, and finally, I D1 and I D2 are the diode currents. The input and IPT winding inductances are considered to be sufficiently high that they do not influence the resonant process. T

Sub-period T0
During this sub-period the converter works in a conventional dual-interleaved boost mode, the diodes D 1 and D 2 conduct, V com is equal to the output voltage, and I L1 has a falling gradient.

Sub-period T1
At time t1, the auxiliary switch, Q aux2 is turned on to facilitate soft-switching. The current I D2 commutates from D 2 to Q aux2 . As I aux2 starts to flow in the pulse transformer, D aux3 becomes forward biased and the transformer secondary voltage, V sec equals the input voltage. The leakage inductance, L leak of the pulse transformer ensures ZCS turn on for the auxiliary switches. However, it also creates an additional voltage across the transformer primary (V pri ) which depends on the gradient of I aux2 . This voltage increases the reverse voltage across D aux1 in the other auxiliary branch.

Sub-period T2 & T3
At time t2, the current commutation finishes, D 2 stops conducting and C S2 starts to discharge by resonating with L leak . The resonant circuit comprising C S2 , Q aux2 , D aux2 , L leak and the pulse transformer primary has an input of V in /2 because of the 1:2 turns ratio of the transformer. Therefore, at t3, when both the snubber capacitor and the auxiliary currents reach their peaks, the snubber capacitor voltage falls to V in /2. Because in a boost converter V out ̶ V in /2 is always greater than V in /2, over all duty ratios the snubber capacitor can be fully discharged. In the conventional SAZZ topology at t3 the snubber capacitor voltage falls to V in , so when V out ̶ V in becomes less than V in (D<0.5 conditions), the snubber capacitor cannot be fully discharged and partial hard-switching occurs. After t3, the currents start to decrease and at t4, the capacitor voltage falls to zero, the capacitor current I CS2 transfers to the anti-parallel diode of Q 2 , creating a ZVS condition for Q 2 . Depending on the value of D, I L1 reaches a minimum, I L1_LOW at some point during these two subperiods and then starts increasing.

Sub-period T3b
The auxiliary current, I aux2 flows through the anti-parallel diode of Q 2 after t4 if the gate pulse for Q 2 does not start exactly at t4. This sub-period provides a window for the ZVS turn on of the main switches as the snubber capacitor voltage is clamped to zero until the auxiliary current falls to half the input inductor current.

Sub-period T4
In this sub-period the current in Q 2 rises to be equal to I L1 /2 and the auxiliary currents in D aux2 and D aux3 fall to zero. At t5, I aux2 becomes almost zero as only a small magnetizing current flows in the pulse transformer allowing Q aux2 to be turned off safely. The turn off of Q aux2 initiates a resonance between the parasitic capacitance of D aux3 and the magnetizing inductance of the pulse transformer. An RC snubber circuit is required across D aux3 to control the associated transient.

Sub-period T5
The converter works in conventional dual-interleaved boost mode, the diode D 1 and the transistor Q 2 conduct, V com is half of the output voltage and I L1 continues to increase until the next sub-period starts.

Sub-period T6
Q 2 is turned off at t6, snubber capacitor C S2 is charged ensuring ZVS turn off for Q 2 . The sub-period ends when both voltages across Q 2 and Q aux2 become V out , and current starts flowing in D 2 . 8 3.8 Sub-period T7 D 1 and D 2 conduct in this sub-period similar to T0. Inductor current, I L1 decreases from the peak value, I L1_HIGH .
Because of the symmetrical operation of the converter, similar sub-periods will occur for Q 1 from t8 onwards. The ZVS transients for D>0.5 are identical to the D<0.5 condition in Fig. 4. However, the steady-state voltage and current waveforms in the circuit are changed as shown in Fig. 2 (b).

Circuit analysis and prototype design
The converter works as a dual-interleaved boost converter during most of the switching cycle except during the resonant period. Therefore, the calculation of the voltage conversion ratio, input inductor and IPT ripple currents and the output voltage ripple will be the same as for the conventional hard-switching dual-interleaved boost converter. However, precise timing calculations are required to generate gate pulses for the auxiliary switches.

Timing calculations for auxiliary switches
The total time of sub-periods T 1 , T 2 , T 3 and T 3b is the maximum timing advance for the auxiliary pulse to ensure ZVS. For orderly operation, the minimum width of the auxiliary pulse has to be the sum of intervals T 1 to T 4 to ensure the auxiliary current reaches virtually zero before the auxiliary switch turns off.
Each auxiliary switch has to be turned off before the turn on of the other auxiliary switch to ensure proper operation. T 1 , T 2 and T 3 can be calculated using (1)-(2) which are derived from Fig. 3 and Fig. 4.
where, ω o is the natural frequency of the resonant circuit given by: Here, C s = C S1 = C S2 and L leak is the leakage inductance of the pulse transformer. T 3b and T 4 can be calculated by solving their respective sub-circuit equations from Fig. 3 as shown in (4)- (5).
I L1 (t1) and I L1 (t2) can both be approximated as the minimum of the input inductor current, I L1_LOW . So, where, Z o is the characteristic impedance of the resonant circuit given by: Equations (1)- (2) and (4)- (5) can be used to calculate the timings for the auxiliary switches. The maximum allowable advance time (T max ) for the auxiliary switch is the sum of T 1 to T 3b and the minimum (T min ) is the sum of T 1 to T 3 . T 3b in this topology is double that of the conventional SAZZ-DIBC topology of [2]. As T 3b provides a window for the turn on of the main devices, a greater T 3b will reduce the control complexity to generate the auxiliary gate pulses. The above equations can also be used to choose the appropriate auxiliary components which will be discussed in the next sub-section.

Design considerations
A 20 kW, 320 V to 600 V boost converter was designed to validate the topology operation and circuit analysis. The switching frequency (f sw ) was fixed at 112 kHz to compare the performance with the conventional SAZZ topology of [2]. The circuit parameters and their selection criteria are shown Table 1. 60.6 A L 1 13.1 μH L 1 =V in D(1-2D)/(2f sw I ripple (1-D)) L diff (IPT) 358 μH Assuming differential current ripple, ΔI diff is 25% higher than the I ripple ; L diff = V out (1-D)/(f sw ΔI diff ) C out 4 μF Considering 1% ripple in the V out when V in = 250 V C s1 , C s2 2 nF Only device capacitances L leak 1.5 μH Optimized based on (1)-(4) to ensure minimum delay and T 1 > t on of D aux & Q aux L secondary 300 μH To ensure 1:2 turns ratio and around 0.5 A magnetizing current in the primary winding L primary 75 μH Here, L diff(IPT) is the total differential inductance of the IPT windings and L primary and L secondary are the selfinductances of the pulse transformer windings.

Prototype description
A demonstrator using SiC switching devices was built. Two first-generation Cree half-bridge modules, CAS100H12AM1 (117 A rated) were used as the main switching devices. The anti-parallel diodes of the upper two devices were used for D 1 and D 2 . Two C2M0080120D MOSFETs (Q aux1,2 ), two C4D40120D diodes (D aux1,2 ) and one C4D10120E diode (D aux3 ) were used in the auxiliary circuits. The 2 nF module capacitance was used for the main snubber operation (C S1,2 ). A 1 nF additional MLCC capacitor and a 50 Ω resistor were used across D aux3 as an RC snubber for the auxiliary circuit.
All the magnetic components used ferrite cores. The main inductor, L 1 was designed with a PQ40 core and the measured inductance was 13.1 μH. The interphase transformer, IPT was built with a PQ50 core and the measured differential inductance was 271 μH at the operating frequency. The self-inductance of each phase was found to be 68 μH. The pulse transformer was built with an ETD29 core and the leakage inductance from the primary side was found to be 0.

Control flexibility with the proposed topology
The proposed circuit provides a wider window for the ZVS turn on of the main switching devices than the original SAZZ converter as shown in Fig. 5, which increases its control flexibility. Maximum and minimum advance times were calculated using (1)-(9) for different output voltages for a fixed input voltage and load. The parameter values are given in Table 1. The results are only shown for D>0.5 for fair comparison with the original SAZZ circuit. It is evident that the width of the advance time window in the proposed circuit is almost double that in the original circuit for the whole specified region which provides greater flexibility in the controller design.

Soft-switching validation
Both the modified and original SAZZ circuits in Fig. 1 were simulated in LTspice using CREEprovided SPICE models of the SiC MOSFETs and SiC Schottky diodes for D<0.5. The turn on transient results in Fig. 7 for D=0.3 show soft-switching of the proposed SAZZ circuit (Fig. 7(a)) and partial hardswitching in the conventional SAZZ circuit (Fig. 7(b)) for the same operating condition. Advance times were calculated using (1)-(5) for both the modified and original SAZZ circuits. Here, V dsQ2 is the drain to source voltage across Q 2 , I dsQ2 is the drain current and I aux2 is the corresponding resonant current. Fig. 7(a) also shows reduced oscillations in both the resonant current and switch current due to the RC snubber. The experimental verification was done for a very similar condition to the simulations and the modified SAZZ prototype showed ZVS turn on transients in both phases, Fig. 8. Fig. 8(a) and 8(b) show the drain to source voltages and drain currents of Q 1 and Q 2 and the auxiliary currents of the respective phases.
Similarly, Fig. 9 shows the ZVZCS transients for both phases at the rated power condition. The experimental results show a good match with the theory and simulation results (not shown for clarity). The inductance in the auxiliary branch also ensures ZCS turn on of all auxiliary switches as evident from Fig. 8 and 9. The auxiliary current falls to zero after the resonant period but before the respective auxiliary switch is turned off, and so this enables ZCS turn off for all auxiliary switches. The RC snubber damped most of the oscillation in the auxiliary circuit ( Fig. 8 and 9). The oscillation in the main switch currents is likely to be induced by the high dv/dt and the Rogowski coil used to measure the drain currents of the modules. Fig. 10(a) and 10(b) show the turn-off drain to source voltages and drain currents of Q 1 and Q 2 at the rated operating point. As no additional snubber capacitor was used across the main switching devices the turn off losses were reduced in Q 1 and Q 2 but not zero. The losses were estimated to be 50% of the hard-switching turn off loss for the rated power condition. The soft-switching operation was also validated experimentally at the D>0.5 condition as shown in Fig. 11

Loss breakdown of the converter
A loss breakdown of the converter was done at the rated power condition to analyse the effectiveness of soft-switching over hard-switching. For the experimental condition shown in Fig. 9 at rated power, Table 2 shows the losses in the different components of the converter. The calculation was based on the experimental results and some datasheet parameters such as MOSFETs' on state resistances (R ds(on) ), gate charges (Q g ), MOSFET anti-parallel diode on-state voltages (V sd ), Schottky diode on-state voltages (V f ) and magnetic core losses. The estimated hard-switching circuit losses are included in Table 2.
It is evident from Table 2 that about a quarter of the total loss during soft-switching operation was in the auxiliary circuit. Also, the conduction losses of the main and auxiliary circuit diodes dominate the respective circuit losses. The loss breakdown shows an efficiency of 98.8% and the experimental efficiency was 98.7% based on input-output power measurements using circuit voltages and currents.  Table 2 while the conduction losses remain the same. Considering the 57.9 W additional auxiliary circuit loss, the proposed converter reduced the switching losses by 74% compared with hardswitching operation.

Efficiency comparison between hard and soft-switching
To investigate the performance of the soft-switching across a range of conditions it was tested at the rated output voltage (600V) at three different input voltages, 260V, 300V and 320V for a range of loads.
The efficiencies for hard and soft-switching operation are shown in Fig. 12   Although near the rated input and output voltage conditions the soft-switching efficiencies are always higher than the hard-switching efficiencies, if the input and output voltages are halved, V in =150 V and V out = 300 V, at low power conditions (below 6.3 kW) hard-switching efficiencies becomes higher as shown in Fig. 13. At these conditions the auxiliary loss exceeds the reduction of switching loss by around 2 to 4 W. However, even at this low voltage, if the output power is increased above 8.4 kW the switching loss reduction exceeds the auxiliary circuit losses.

Conclusion
The converter presented in this paper is demonstrated to be superior to the previously published SAZZ topologies. The ZVZCS turn on can be achieved for a wide range of duty ratios. The resonant inductor of the SAZZ-DIBC topology was replaced by a pulse transformer of the same size and weight.
The greater flexibility in the choice of advance time for the auxiliary gate pulses also eases the control complexity, potentially allowing fixed advance times to be used across the full operating range of the converter, as was the case in the prototype system. The simulation and experimental results confirm the feasibility of this topology and suggest its potential for high frequency multi-kW DC-DC converters.
The soft-switching prototype is shown to be superior to the hard-switching circuit in terms of losses and efficiency; the switching loss for the main semiconductor devices was reduced from 367 W to 38 W in the proposed converter, increasing the efficiency from 97.5% to 98.7%. The improvement in efficiency was demonstrated across a wide range of load powers and a range of input voltages. With higher switching frequencies (>112 kHz) and higher converter output voltages (>600V) the improvement in efficiency compared with hard switching is likely to be greater due to the overall increase in switching loss under these conditions, whereas at lower switching frequencies or designs where conduction losses dominate the total loss the benefit of the circuit will be reduced. The efficiency improvement could allow down-sizing of the heatsink, thereby increasing power density, or may enable an increased operating frequency, which could result in smaller passive components. Furthermore the use of additional snubber capacitors in parallel with the main devices could provide a greater reduction in main transistor turn off loss and also limit the dv/dt in the switching waveforms which is likely to improve the EMI performance. These findings highlight the potential of soft-switching techniques to assist in maximizing the performance benefit of SiC technology. The complexity of soft-switching circuits in terms of optimization, manufacture and control create additional design challenges, but it is thought that these could be overcome using integrated switching module assemblies, FPGA control platforms and modern simulation tools.