Push–pull mode digital control for LLC series resonant dc-to-dc converters

This study presents the design and performance evaluation of the digital control adapted to an LLC series resonant dc-to-dc converter operating with wide input and load variations. The proposed control design correctly incorporates the wide-varying power stage dynamics and variable small-signal gain of a digitally controlled oscillator, thereby offering satisfactory converter performance for all the operational conditions. The proposed digital controller adopts the push–pull mode control scheme, which executes the control action two times in one switching period, to minimise the time delay and enhance the performance. Using a 150 W experimental converter, the performance of the proposed push–pull mode digital control is demonstrated in comparison with that of the conventional complementary mode digital control, which performs the control action only once in one switching period.


Introduction
Digital control has emerged as a viable alternative to the conventional analog control for pulsewidth modulated (PWM) converters and resonant converters. The digital control of PWM converters has been extensively studied in past researches, yielding many useful results [1][2][3][4][5][6][7]. The digital control of resonant converters also acquired an ever-increasing attention because of the rapid development of the digital signal processor (DSP). The digital control of resonant converters can be divided into two groups. The first group is the non-linear control schemes, such as geometric boundary control [8,9], observer-based control [10], sliding mode control [11] and optimal trajectory control [12][13][14]. These control schemes directly monitor and control the resonant tank waveforms using high-performance DSPs or field-programmable gate array. These non-linear controls do not rely on the small-signal models or small-signal dynamics of converters for the execution of their control functions.
The second group is the digital controls based on the emulation method [15][16][17], which transforms an s-domain linear compensation into the z-domain counterpart. The emulation-based digital controls are entirely based on the small-signal dynamics of the resonant converters. Although these control schemes presume relatively small variations in the operating point, some protective measures are embedded into the controller for safe operations of the converter during large transitional periods. This paper presents a new emulation-based digital control for LLC resonant converters, which can be implemented with a cost-effective 16-bit DSP while offering considerable improvements over earlier emulation-based digital controls.
There exist several challenges for the implementation of the emulation-based digital control for resonant converters. One challenge would be the variations in both the power stage dynamics of the converter and small-signal gain of a counter-based digitally controlled oscillator (DCO). The power stage dynamics are sensitively affected by operational conditions [18][19][20][21][22]. The small-signal DCO gain varies as a quadratic function of the switching frequency. The digital control should be designed in consideration of these wide-varying power stage dynamics and DCO gain.
Another important issue of the emulation-based digital control is the time delay between the analog-to-digital converter (ADC) sampling and the switching period updating. The time delay is converted into the phase delay in the frequency responses, which could lower the phase margin of the loop gain and induce an unexpected oscillation in the output voltage.
In the conventional digital control for resonant converters, the ADC sampling is performed once in one switching period and the period updating is delayed at least half the switching period. This control scheme has been known as the complementary mode control [16]. This paper proposes a digital control scheme which employs two ADC samplings in one switching period: one ADC sampling during the first half of the switching period and another ADC sampling during the remaining half of the switching period. This control scheme is referred to as the push-pull mode control. In this control scheme, the two ADC samplings are individually used to immediately update the duration of the ensuing half of the switching period. The proposed control scheme substantially reduces the time delay and enhances the performance, compared with the case of the conventional complementary mode control. This paper will show that the push-pull mode digital control outperforms the analog control, implemented with a fixed-gain voltage controlled oscillator (VCO) [18][19][20][21]. Initially, the analog control might be designed for a large loop gain magnitude, sufficient stability margins and wide control bandwidth. However, when the operating point moves into the region where the power stage transfer functions vary into an undesirable direction, the converter performance will be degraded. In contrast, the DCO-based digital control exploits the non-linear DCO gain to compensate for unwanted variations in power stage transfer functions. This paper will demonstrate that the digital control could offer the superior loop gain characteristics and transient responses, compared with VCO-based analog controls. The proposed push-pull mode control also possesses the general merits of the digital control, such as design flexibility, cost-effectiveness, enhanced noise immunity and higher power density [15,[23][24][25].
This paper addresses the design and performance evaluation of the push-pull mode digital control for LLC series resonant dc-to-dc converters. The current paper adopts the standard emulation method for the digital compensation design, nonetheless, the compensation design incorporates the variations in the power stage dynamics and DCO gain. Design procedures and performance evaluation of the proposed digital control are illustrated using a 150 W experimental LLC converter. The performance of the push-pull mode digital control is compared with that of the complementary mode digital control. This paper reveals that the push-pull mode control outperforms the complementary mode control, because of a reduced time delay and enhanced feedback gain. This paper also shows that the push-pull mode digital control offers the closed-loop performance that favourably compares with the performance of the conventional analog control.

Design of push-pull mode digital control for LLC converter
This section presents the design of the proposed push-pull mode digital control, adapted to a 150 W experimental LLC converter. The digital compensation design is based on the standard emulation method, nonetheless, it considers the wide-varying power stage dynamics and DCO gain, to obtain good performance for the entire operational range.  [16]. Procedures for DSP selection for the given application are presented in Appendix. The 10-bit ADC inside the DSP accepts the sensed output voltage in the range of v sense = 0−3.3 V. The digital compensation F v (z) receives the error signal e[n] from ADC and provides the input signal c[n] for the DCO. The DCO operates with a counter-based digital-PWM scheme [3]. The DCO outputs derive two MOSFET switches, Q 1 and Q 2 , in a push-pull mode of operation [16], where the turn-on durations of the two switches are individually controlled by the two DCO outputs. For the given input and load specifications, the operational region of the converter can be defined on the voltage gain curves, as  For the given LLC converter, the operating point normally lies on the curve between Point A and Point B: V S = 340−390 V with I O = 6 A. Accordingly, the dynamic analysis and control design will be mainly focused on Points A and B. Nonetheless, the converter performance will be evaluated for the entire operational region.

Power stage dynamics
The earlier studies [18][19][20][21][22] proved that small-signal dynamics of LLC converters vary substantially as operational conditions are altered. The major result of these analyses is shown in Fig. 3 in conjunction with the small-signal dynamics of the experimental LLC converter. Fig. 3a depicts the pole/zero trajectory of the frequency-to-output transfer function with respect to the input voltage variation. The trajectory portraits the locations of the poles and zero as the input voltage decreases from V S = 390 V, represented by Point B in Fig. 3, to V S = 340 V, denoted as Point A, while delivering the load current of I O = 6 A. Detailed analyses for the locations of poles and zero at Point A and Point B were given in [18][19][20][21][22].
Fig. 3b displays the measured Bode plot of the control-to-output transfer function, G vc (s), at Point A and Point B. For the G vc (s) measurement, an analog control is employed to the experimental converter. The transfer function exhibits notable changes, in the exact same manner as predicted from the pole/zero trajectory in Fig. 3a. It is observed that Point B has a single pole ω pl at low frequencies and shows the first-order system behaviour from lowto mid-frequencies. In contrast, Point A reveals the second-order behaviour with rapid-declining phase characteristics because of the two neighbouring poles, v ′ pl and ω sp1 . Point A presents the worse small-signal dynamics and thus becomes a logical target for the compensation design.
From Fig. 3b, an approximated expression for the control-to-output transfer function at Point A is determined as where K vco A is the gain of the analog VCO at Point A and K vf A is the low-frequency gain of the frequency-to-output transfer function at Point A. Although the expression (1) does not account for the high-frequency dynamics, it adequately describes the converter dynamics up to mid-frequencies and thus can be used as a basis for the compensation design. The esr zero in (1) is calculated as ω esr = 1/(CR c ) = 7.5 × 10 4 rad/s. The neighbouring poles in Fig. 3b are estimated as v ′ pl = 5.0× 10 3 rad/s and ω sp1 = 7.0 × 10 3 rad/s. The low-frequency asymptote of Fig. 3b is observed as 20 log K vco A K vf A = 20 dB. The analog VCO gain at Point A was measured as K vco A = 2p · 6.10 × 10 4 . The low-frequency gain of the frequency-to-output transfer function at Point A is now determined as K vf A = 10/K vco A = 2.61 × 10 −5 .

s-Domain compensation formulation
An s-domain compensation is initially formulated and later converted into the z-domain compensation using the emulation method. The s-domain compensation is designed using the control-to-output transfer function at Point A,G vc (s) A , to secure stability and performance for the entire operational range.
An earlier publication [18] showed that a three-pole two-zero compensation provides good dynamic performance for the experimental converter over the entire operational region the v z1 = v ′ pl = 5.0 × 10 3 rad/s, ω z2 = ω sp1 = 7.0 × 10 3 rad/s, ω p1 = ω esr = 7.5 × 10 4 rad/s and ω p2 = 9.5 × 10 4 rad/s. For a practical design implementation, the integrator gain K v is determined after the selection of loop gain crossover frequency, ω c [26]. The loop gain crossover frequency is selected at ω c = 2π · 2.3 × 10 3 rad/s for a sufficient phase margin. The evaluation of the required integrator gain K v will be discussed later. HK where ω c is the loop gain crossover frequency and K v is the integrator gain. The required K v for the desired ω c is now determined as

Conversion to z-domain compensation
The s-domain compensation (5) is converted into the z-domain compensation through the bilinear transform using MATLAB software. For the push-pull mode control with two ADC samplings in one switching period, the sampling time period for the s-to-z-domain compensation conversion, t samp , is given by t samp = 1/(2f sw ) where f sw denotes the switching frequency at Point A. The bilinear-transformed z-domain expression of (5) is determined as and later converted into the parallel structure Fig. 6 is the simulation block diagram of (7), which can readily be converted into the C-code programming. Fig. 4b shows the measured and simulated Bode plots for |G vcA | and |T mA | of the experimental LLC converter at Point A with the proposed digital control. The time-domain simulation method [18] using PSIM software is employed to generate the simulated Bode plots. Fig. 4b closely resembles Fig. 4a, thereby validating the proposed design procedures.

DCO gain and total time delay of digital control
This section analyses the small-signal gain of the counter-based DCO and the total time delay in digital control. The current section also addresses the features of the push-pull mode control in comparison with those of the complementary mode control. The variable N is then multiplied with a prefixed DCO clock, t clk , to update the switching period of the two complementary-driven MOSFET switches. This operation is illustrated in Fig. 7a. The frequency of the period updating is given by

DCO and small-signal gain
For this case, the period updating frequency is the same as the switching frequency: f update = f sw . The operation of the push-pull mode control is illustrated in Fig. 7b, where the ADC sampling is performed twice in one switching period. For this case, the intermediate variable is calculated as N′ = 0.5K DCO c[n] and subsequently multiplied with the t clk to determine the duration of the ensuing half of the switching period, thus enabling to immediately use the result of the accelerated ADC sampling. The period updating frequency now becomes (9) For this case, the period updating frequency is double the switching frequency: f update = 2f sw . The input variable of the DCO is the c[n] and its output variable is the frequency of the period updating, f update . Thus, the small-signal gains of DCO for the two different operational modes are evaluated as (see (10)) where f sw = 1/(K DCO c[n]t clk ) is the switching frequency. As shown in (10), the DCO gains in both the cases increase as a quadratic function of the switching frequency. More importantly, the DCO gain of the push-pull mode control is two times larger than that of the complementary mode control. The DCO gain in (10) contains the two constants, t clk and K DCO . These constants are determined as follows. First, the DCO clock in dsPIC33FJ16GS is given by t clk = 1.04 × 10 −9 s. As demonstrated in Fig. 2b in 2.2, the switching frequency of the experimental converter varies between 50 < f sw < 110 kHz. The lower limit of the switching frequency is set at f sw lower = 35 kHz to secure a 15 kHz margin from the minimum switching frequency of 50 kHz. The constant K DCO is determined such that the DCO generates the upper limit of the switching period when the 'digital-equivalent' value of '1' appears as the input signal c[n]. The upper limit of the switching period is then determined as t sw upper = 1/f sw lower = 1/35 × 10 3 = 28.6 μs. Thus, K DCO is calculated as t sw upper t clk = 28.6 × 10 −6 1.04 × 10 −9 = 2.8 × 10 4 Fig. 7c shows the DCO gain curves evaluated using (10) with K DCO = 2.8 × 10 4 and t clk = 1.04 × 10 −9 . The DCO gain at Point A with f sw = 50 kHz is calculated as f DCO A = 2(50 × 10 3 ) 2 2.8 × 10 4 1.04 × 10 −9 = 1.5 × 10 5 which was used in (4) to determine the integrator gain K v .

Comparison with complementary mode digital control
The push-pull mode control and complementary mode control produce the different DCO gain and total time delay. The performance of the experimental LLC converter is investigated with the two control schemes, to assess the merits of the respective control scheme. The loop gain magnitude is uniformly decreased by 6 dB because the DCO gain is reduced to half the push-pull mode control case. More importantly, the phase curve reveals much increased phase delay at the high frequencies, as a direct consequence of the longer time delay in the complementary mode control. This indicates that the push-pull mode control provides an exact 6 dB gain boost over the conventional complementary mode control, as predicted from the DCO gain expression in (10). In addition, the push-pull mode control significantly improves the phase characteristics at high frequencies because of the reduced time delay.
To compensate for the DCO gain reduction, the integrator gain is doubled, K v = 3.12 × 10 4 , for the complementary mode control and the resulting loop gain characteristics are shown with the dashed line. Although the loop gain magnitude is restored to the value of the push-pull mode control, the phase curve still shows an excessive high-frequency phase delay.

4.1.2
Step load change responses: Fig. 10 Fig. 11 illustrates the comparison of performances of the proposed push-pull mode digital control with the case of the conventional analog control. The potential merit of the proposed digital control using a counter-based DCO is highlighted. Fig. 11a depicts the measured and simulated loop gain characteristics of the push-pull mode digital control in comparison with those of the analog control. The analog control is optimally designed based on the design procedures proposed in [18]. The digital control produces larger phase lag at high frequencies, as a result of the unavoidable time delay in digital control. Except for the additional phase lag, the digital control nearly duplicates the loop gain characteristics of the analog control at Point A.

Loop gain characteristics:
At Point B, the loop gain of the digital control exhibits a 7 dB magnitude boost, compared with that of the analog control. The magnitude boost is an outcome of the non-uniform DCO gain. As shown in Fig. 7c, the DCO gain at Point B is larger than the DCO gain at Point A by a factor of (75 × 10 3 /50 × 10 3 ) 2 = 2.25. The The non-uniformity in the DCO gain can be exploited to compensate for unwanted and undesirable variations in power stage dynamics; the magnitude of the frequency-to-output transfer function is inversely proportional to the switching frequency. This gain decrease can be cancelled with an increased DCO gain at high frequencies.

Conclusions
This paper presented the design and performance evaluation of the push-pull mode digital control, adapted to an LLC series resonant dc-to-dc converter operating with wide input and load variations. The non-iterative compensation design procedures are proposed. Although the standard emulation method is employed, the design procedures correctly incorporate the variations in the frequency-to-output transfer function and DCO gain, and offer satisfactory performance for the entire operational range.
The design procedures and performance of the proposed digital control are validated using a 150 W experimental LLC converter. The performance of the push-pull mode digital control is compared with that of the complementary mode digital control and conventional analog control. With an enhanced ADC sampling rate and integrator gain, the push-pull mode digital control revealed the superior performance over the other two control schemes, thereby demonstrating the application potential of the proposed digital control for resonant dc-to-dc converters.

Appendix: Selection procedures for DSP
As shown in Fig. 2b in 2.2, the switching frequency of the experimental converter varies between 50−110 kHz. The upper limit of the switching frequency is selected as f sw upper = 120 kHz, to provide a 10 kHz buffer from the maximum switching frequency of 110 kHz. For the proposed push-pull mode control, the minimum process time from the ADC sampling to the period updating is given by t process min = 0.5/f sw upper = 0.5/120 × 10 3 = 4.2 μs.
The three-pole two-zero digital compensation used for this application requires 125 instruction cycles. Thus, any DSP chip which could complete the AD conversion plus 125 instruction cycles within 4.2 μs is suited for this application. The 16-bit dsPIC33FJ16GS from Microchip [16] is selected as the most cost-effective solution. The total process time for dsPIC33FJ16GS is given by t process = n ADC t ADC + n comp MIPS × 10 −6 (11) where n ADC = 18 is the ADC clock cycles of the DSP, t ADC = 50 × 10 −9 is the ADC clock period of the DSP, n comp = 125 is the total instruction cycles of the three-pole two-zero compensation, MIPS = 40 is the DSP spec in the unit of Million Instructions Per Second. Evaluation of (11) with the given data yields t process = 18 · 50 × 10 −9 + 125 40 × 10 −6 = 0.9 × 10 −6 + 3.13 × 10 −6 = 4.03 ms , 4.2 ms thereby confirming the proper operation for the entire operational range of the converter.