Pulse delay control for capacitor voltage balancing in a three-level boost neutral point clamped inverter

The cross regulation effect in multi-output DC/DC converters offers a reliable support for the grid integration of multilevel inverters by balancing the capacitor voltages. The capacitor voltage balancing by single input dual output boost converter is often realised by conventional three-level switching scheme. The three-level operation benefits lower inductor ripple current, but it limits the maximum possible compensation voltages. In this study, the entire operating modes of the boost converter is presented and all the possible cases which contribute to the voltage balancing are employed for balancing the capacitor voltages in a three-level neutral point clamped inverter. A proportional-integral controller based duty ratio control and pulse delay control are used for DC link voltage regulation and capacitor voltage balancing. Since the classical state-space averaging technique is not suitable for SIDO converters, inductor current ripple averaging technique is utilised for controller design. The circuit simulation is performed in Matlab/Simulink. The digital controller is realised using the Virtex-5FPGA in Labview/CompactRIO module. Both simulation and experimental results are presented to validate the controller performance.


Introduction
The increased grid integration of renewable energy resources, especially from offshore platforms, demands power transmission at high voltage to limit the current and thereby, associated losses. The power conditioning systems such as inverters and DC/DC converters are often required to provide electricity to the load centres. In response to the growing demand for medium and high power applications, multilevel converters are chosen to be the inevitable appliance for power conversion. Neutral point clamped (NPC) inverter is one of the main attractive topology among multilevel inverters for renewable energy conversion and for drive industry so far. However, capacitor voltage imbalance with respect to the neutral point is one of the key areas under discussion [1]. Several voltage balancing techniques for conventional NPC inverter are discussed in literature. Every method is generally based on either adjusting the modulation strategy, or adding passive or active elements. Jie Shen et al. have presented the self-balancing property of a three-level NPC converter in [2]. Since the neutral-point (NP) voltage drifts for small variations in the system parameters, self-balancing technique will not always suffice. NP voltage control methods based on carrier pulse width modulation (CPWM) and space vector modulation (SVM) strategies are discussed in [3][4][5][6][7][8][9][10]. In addition, several hybrid modulation strategies are also developed for voltage balancing [11][12][13]. In contrast, these modified PWM methods increase the complexity and digital resource consumption. Several NP voltage balancing circuits for NPC inverter are presented in literature [14][15][16].
A single input dual output (SIDO) boost converter, which is often called as three-level boost (TLB) converter, can halve the power device voltage stress compared with the conventional two-level boost converter, which is more suitable in low voltage input-high voltage output applications. Additionally it has several advantages in high voltage applications such as reduced switching losses and lower reverse recovery losses of the diode compared with the conventional boost converters [17,18]. The SIDO boost circuit for power factor correction is discussed in [17][18][19]. The maximum power point tracking by direct duty ratio control of this converter using a power hysteresis is presented in [20]. A TLB converter circuit is proposed for NP voltage balancing in [17,18,[20][21][22]. Independent duty ratio control of the switches are considered for voltage balancing of dc-link capacitors in [20,21]. Xia, et al. have proposed switch signal phase delay control (SSPDC) method for balancing the NP voltage with simulation results, where the signal phase delay lies between d and (1 − d) for a duty ratio d [22]. A similar method is experimentally proved for resistive loads at 50% duty ratio in [23]. PDC technique is based on the dynamic variation of pulse delay to compensate the capacitor voltages, which results different cases, including either two, three or four modes of operation of the SIDO boost converter. In this article, the authors extend the operation of the converter to eight different cases to compensate the neutral voltage imbalance where the delay varies from zero to the switching period, T. This paper discusses the control and implementation of the SIDO boost converter for DC voltage boosting and PDC based NP voltage balancing. It operates as front-end of a three-level NPC inverter. The capacitor voltage deviation at steady state and proportional-integral (PI) controller parameter calculation methods are derived for each cases. The simulation and experimental results are provided to validate the DC link and NP voltage control techniques.

SIDO boost converter
The schematic circuit of three-level boost NPC (TLBNPC) inverter considered for analysis is shown in Fig. 1a. The input is a DC voltage source in series with an inductor L.
The NP of the inverter is connected to the midpoint of the switches S 1 and S 2 . R s , C s and D s are the snubber circuit elements for transient voltage protection. C 1 and C 2 are the DC link capacitors. The NPC inverter is connected to a RL load. The boost converter allows four different modes of operation. It gives different behaviours depending on the switching sequence and the time of operation of each mode. To analyse the modes of operation, the NPC inverter can be replaced by variable resistive loads. It is assumed that the inductance L is large enough to maintain the current in continuous conduction mode and the capacitors are large enough to keep the output voltage constant. The four modes of operation of boost converter in steady state with relevant voltage and current equations in ideal condition can be summarised as follows. In mode 1, both S 1 and S 2 are ON. Therefore, the inductor current increases and the load current is supplied by C 1 and C 2 as shown in Fig. 1b. The relevant voltage and current equations during this interval is given in (1) where p is the differential operator d/dt. v in is the input voltage, v C1 , v C2 represent the corresponding voltages across C 1 and C 2 , i L is the inductor current and R 1 , R 2 are the load resistors. In mode 2, S 1 is ON and S 2 is OFF. Therefore, the capacitor C 2 charges and the capacitor C 1 discharges to the load as shown in Fig. 1c. The state equations in this mode are presented in (2) In mode 3, S 1 is OFF and the switch S 2 is ON. The input current flows only through the first output (C 1 and R 1 ) and current through R 2 is supplied by the capacitor C 2 as shown in Fig. 1d. Equation (3) shows the voltage and current equations during this interval In mode 4, both S 1 and S 2 are OFF as shown in Fig. 1e The input current flows through both outputs and delivers energy to both. The state equations can be expressed as in (4)

SIDO boost converter control
The NPC inverter input voltage control and capacitor voltage balancing are considered as the control objectives of the SIDO boost converter. The controls are realised using two PI controllers. The DC link voltage control and balancing can be achieved by minimum number of sensors. The control block diagram is given in Fig. 2.

DC voltage control
Similar to the conventional boost converters, the steady state output voltage of the SIDO converter can be calculated approximately using the input voltage V in and the duty ratio d as in (5).
The DC link voltage control utilises the boost capability of the SIDO converter to calculate the duty ratio of the switches to obtain the desired voltage across the DC link capacitors. It provides a high voltage at the input of the NPC converter; thereby total harmonic distortion of the inverter output voltage improves. The DC link control is achieved by a PI controller as shown in Fig. 2. The output of the PI controller is proportional to the duty ratio of the switches to achieve the desired DC link voltage. The voltage error e vd can be defined as V dref − v d ; where V dref is the desired DC link voltage and v d is the actual voltage across C 1 and C 2 .

Pulse delay control (PDC)
The capacitor voltages are regulated by PDC using a PI controller as shown in Fig. 2. In this method, both switches operate at the same duty ratio and constant switching frequency. To compensate the voltage in neutral point a delay is introduced to move the control signal G S1 either forward or backward in relation with G S2 , where G S1 and G S2 are the control signals of S 1 and S 2 , respectively. In the PDC control, two capacitor voltages are sensed and the voltage difference is compared with the set point. The output of the PI controller is proportional to the delay between the two control signals to achieve NP voltage to zero. To balance voltages of both capacitors the reference value of NP voltage, V npref is set to be zero. Therefore, the error in NP voltage, e np can be defined as The pulse delay ratio is defined as l = Delay between G S1 and G S2 T (7) Depending on the value of duty ratio d and pulse delay ratio l, the SIDO converter operates in ten different cases which are shown in Table 1. In contrast with [22], according to PDC method, mode 1 is also possible when d < 0.5. The duration of mode 1 (d 1 ) can have two values d 11 and d 12 in case VI. Similarly, for the mode 4 in case IX, each duration is represented by d 41 and d 42 . The duration of mode 2 (d 2 ) and mode 3 (d 3 ) are the same in all cases. The expressions to calculate the duration of each mode for all the cases are given in (8) Equation (5) can be rewritten as The cases of SIDO converter with the variation in d and l are given in Fig. 3.

Controller design
The parameter identification for total DC link voltage regulation is similar to the conventional boost converter using classical state space averaging technique. The transfer function of v d (s)/d(s) for case II can be simplified into G 1 (s) where C = C 1 = C 2 and R = R 1 = R 2 . In contrast, the conventional state space averaging technique may not be useful for designing the voltage imbalance regulator as the ripple in the inductor cannot be ignored [24]. Inductor current ripple based averaging method is used for deriving the system transfer function v np (s)/l(s) and also for the controller design. For example, the voltage imbalance regulator design for case II is given below.
In Fig. 4a, the switching pulses, inductor current and voltage across the inductor for case 2 operation is given. The inductor current ripple levels are denoted by m, n, p  and q In (12), Substituting (12) in (11), the average inductor current in each mode can be estimated as follows In general, the system representation in state space form iṡ The average inductor current, I L in each mode is replaced by the corresponding expressions given in (13), (14) and (15).
The state matrix in each mode can be expressed as (see (17) at the bottom of next page). (see (19) at the bottom of next page).
The NP voltage deviation can be derived by subtracting the elements in second row by the third row in (19) and (20). The expressions for neutral point voltage from DC and AC analysis can be derived by perturbation method by adding the disturbance terms to the state variables as d = D +d, In steady state Closed loop transfer function, G c2 (s) can be written as The PI controller parameters can be calculated as where j is the damping ratio and w n is the natural frequency of the converter. The expressions for k dc and k ac in each case are summarised in Tables 2 and 3. The inductor ripple current is similar in case II and case III, case V and case VII, case VI and case IX and case VIII and case X. From the controller design, the parameters values are obtained as positive gains for cases II, III, V and VII. For cases VI, VIII, IX and X, the controller gains are negative. The normalised value of compensation voltages (V np,norm = V np /V d ) in steady state by SSPDC and PDC methods are presented in Fig. 5. The Fig. 5a shows the compensation voltages by SSPDC when Λ varies from d to (1 − d).    The main modulation techniques for NPC inverter can be classified as CPWM and SVM. The different CPWM techniques for NPC converters are presented in [25]. The three main techniques are phase disposition PWM (PDPWM), alternative phase opposition disposition (APOD) and phase opposition disposition (POD) PWM. The switching state relation of NP voltage imbalance can be clearly explained with SVM. At the same time, it increases the computational complexity. CPWM method is simpler for implementation. PDPWM method considered in this paper needs two carrier signals to specify the boundaries between the voltage levels. This modulation strategy retains lower harmonic energy in the line-line inverter output voltage compared with other CPWM methods such as APOD or POD [26]. The peak value of NPC inverter output phase voltage can be calculated as where m i is the modulation index.

Simulation results
The functionality of the proposed control algorithm is examined via simulations performed in Matlab/Simulink. The circuit and controller parameters used for simulation are given in Tables 4 and 5, respectively. These values are chosen to match with the system used for subsequent experiments. The PI controller response for DC voltage control is given in Fig. 6a. The capacitor voltages before and after balancing are presented in Fig. 6b

Control implementation
The control algorithm is implemented in Labview/FPGA. The complete algorithm is executed in independent synchronised parallel loops. If the error between the controller reference and actual value is less than the tolerance level, the error is assumed to be zero which avoids the oscillations around the set point as given in (29). The control loop updates the duty ratio and the phase value in every 0.04 ms. The pulse G S1 for S 1 is generated from the duty ratio value obtained from the DC voltage controller. The pulse G S1 delays G S2 with a phase value corresponding to the error in voltage difference. The delay controller receives a new value only when the voltage error is within the tolerance band. It avoids the transients when the duty ratio and phase change occur simultaneously. The control signal G S2 is generated in two sequential steps, the first is responsible for the pulse delay and the second is for the pulse generation. The delay loop waiting length (D LWL ) is modified with the value from the PI controller in each iteration of the loop. If the delay time is used directly as the loop waiting length, the delay between G S1 and G S2 grows in every switching   cycle for a positive phase value. This results in deviation of NP voltage from equilibrium. To prevent this delay increment, the loop waiting length is modified as in (30).
where Δl k = l k + 1 − l k , is the difference in pulse delay ratio in kth and (k + 1)th switching period. To keep the frequency constant, the waiting time for the S 2 control signal loop must be equal to the switching period. However, an additional delay of 0.4 μs taken by the internal logic blocks is also considered to synchronise the control signals of S 1 and S 2 . The NPC inverter control signals are generated using PDPWM at a frequency of 1.85 kHz in two parallel loops. The reference signals generation and PWM operation are synchronised symmetrically, that is, one sampling point of the reference signal is considered in each carrier interval. The reference signal generation loop takes an internal logic delay of 75 ns. To avoid the DC link shoot through, the control signals are generated with a dead time of 22.5 μs.

Experimental results
A laboratory prototype for TLBNPC inverter, shown in Fig. 7, is built and tested to verify the feasibility of the control algorithm. The inductor for the boost converter is designed experimentally in order to keep the process in continuous mode with the smallest possible value. To avoid the inrush current, the hardware circuit is started while the SIDO converter operates in mode 4. During that, there is no NPC input voltage boosting. If the voltage boost control and PDC start simultaneously, there is no risk of unequal voltages at the capacitor even when the boost gain varies. The step response of the PI controller for NPC input voltage control is shown in Fig. 8a. The capacitor voltages before and after balancing are presented in Fig. 8b.
If the PDC begins after the boost control and especially the NP voltage is higher than the achievable compensation voltage for that particular duty ratio, high voltage oscillation occurs at the NP voltage and that reflects on the duty ratio as well. This situation is noteable to some extent in Figs. 8c and d where the NP voltage is at the marginal compensation voltage. To re-compensate this situation, the input voltage needs to be increased or the desired voltage at NPC input should be decreased, otherwise a large current will be drawn from the source to balance the voltages. To ensure shoot through protection for SIDO boost circuit, the duty ratio is limited to 99% of the switching period. If the NP voltage is less than the possible compensation voltage at specific duty ratio, the PDC brings the capacitor voltages to equilibrium without any oscillation. Therefore, once the voltages are balanced by PDC, any increase in the desired NPC input voltage or TLB input voltage does not introduce any high voltage oscillation or deviation. The NPC inverter line to line voltage and current before and after balancing are presented in Figs. 10a and b.   Fig. 6 Step responses of DC voltage and PDC a PI controller response for DC voltage control b Lower and upper capacitor voltages before and after voltage balancing. NPC inverter output waveforms before Land after capacitor voltage balancing c Voltage (time axis = 10 ms/div, voltage axis = 10 V/div) d Current (time axis = 10 ms/div, current axis = 0.5 A/div) Fig. 7  Similar to the simulation results, the experimental waveforms are not symmetrical and have high harmonic content before balancing. The waveforms are perfectly symmetrical once the PDC is activated.

Conclusion
In this paper, the SIDO boost converter is investigated in all possible switching cases for balancing the NP voltage. The presented boost converter topology is able to achieve high voltage gain conversion compared withĆuk DC/DC converters [14]. The DC voltage control and the capacitor voltage balancing are achieved by PI controller based duty ratio and pulse delay regulation. The PI controller parameters are designed by inductor current ripple averaging method. The main advantage of three-level operation of SIDO converter is the lower inductor ripple amplitude compared with conventional boost converter. But, the imbalance compensation voltage in each mode depends on the inductor stored energy in the preceding mode. Therefore, the full range variation of delay gives higher compensation voltage than in the three-level operation. Compared with the conventional three-level switching used in SSPDC, 18.43% higher compensation voltage can be achieved by PDC method. In duty ratio control of NP voltage compensation, the total DC link voltage deviates from the reference value if the duty ratio is adjusted for one of the switch. Therefore the controller has to calculate the effective duty ratio and its deviation in addition to the regulation of total DC link voltage as in [20] In PDC method, both switches are operated at same duty ratio which keeps the total DC link voltage same even if the pulse delay varies. Therefore the controller objectives can be reduced. Even though the duty ratio and pulse delay are inter-dependent to produce the compensation voltage, the good agreement between simulation and experimental results show a stable operation of the converter.
The capacitor voltages remain in balance if the required compensation voltage is less than 39% of the total DC link voltage, but this value is only 16% for a three-level buck boost converter [27]. Subsequently, the inverter output waveform distortions are decreased after compensating the capacitor voltage balancing. Step responses of DC voltage and PDC a PI controller response for DC voltage control b Lower and upper capacitor voltages before and after voltage balancing. NPC inverter output waveforms before and after capacitor voltage balancing c Voltage (time axis = 10 ms/div, voltage axis = 10 V/div) d Current (time axis = 10 ms/div, current axis = 0.5 A/div)