Single-harmonic active power line conditioner for harmonic distortion control in power networks

: In this contribution, a novel alternative concept and solution procedure for single-harmonic active power line conditioner (SHAPLC) planning is proposed to control voltage harmonic distortion in power networks. The development of the proposed solution concept, de ﬁ ned and detailed in this paper, is based on seeking a proper solution to practical situations, taking into account the particular harmonic distortion pattern and con ﬁ guration of the power system in question. The location of the SHAPLC ’ s, for each harmonic h of interest is determined through feasibility and sensitivity analysis. Once the best location for the SHAPLCs is known, the injection currents are determined by solving a non-linear programming algorithm. The usefulness and novelty of the SHAPLC planning methodology is illustrated with a case study, where results show its effectiveness to control the harmonic distortion in the power system. The solution procedure proposed in this contribution is aimed to achieve and assure individual harmonic distortion and total harmonic distortion indices meet recommended limits by Std-519 IEEE using SHAPLCs devices. According with revised literature, this goal has only been approached with certainty and suf ﬁ ciency (not trial and error) by considering multiple injection currents at different harmonic frequencies from the selected bus.


Introduction
Harmonic distortion is increasing in distribution power systems because of the proliferation of non-linear loads, such as adjustable speed drives and rectifiers. To correct this power quality problem the active power line conditioner (APLC) has demonstrated to be an appropriated tool to keep harmonic distortion indices in the power system within the recommended guidelines [1][2][3][4][5][6][7][8][9][10].
The APLC is a type of active power filter; a converter-based compensation device designed to reduce the harmonic distortion of the entire electric network by injecting corrective harmonic currents at selected (sensitive) buses. Their placement, sizing and their injection currents are usually determined by using an optimisation-based approach [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. Some authors have proposed different alternatives about the number of APLC units necessary to reduce and control the harmonic distortion levels below those recommended by the standards (e.g. as specified by IEEE Std-519 [16]). In [2,5], a single APLC is used to achieve acceptable harmonic distortion indices through the entire electric network.
On the other hand, arguing the possible scenario of a high harmonic pollution in the electric system and a restriction on the maximum permissible rating (maximum affordable size) of the APLC units, in [3,6,7] and [10] multiple APLC units are considered to mitigate the harmonic distortion below recommended limits. Even though it is clear that both viewpoints are valid, at some point it is important to clarify some situations, for example, for the case of a single unit APLC planning in [2,5,12,13]; is it equally convenient to inject the correction harmonic currents, for each different harmonic h, at the same (selected) node of connection? And for the case of multiple APLC planning in [3, 6-7, 10, 14, 15]; how convenient is to afford the control algorithm for all the APLC units, for all the harmonics, at the same time?
In this paper, a methodology is proposed that takes into account both situations mentioned above on the decision making of APLC planning. The final goal is to maintain the harmonic distortion indices individual harmonic distortion (IHD) and total harmonic distortion (THD) of voltage below the permissible levels imposed by the IEEE Std-519, with a methodology employing multiple compensation devices (as many as required according with the presence of harmonic distortion) and lower computational effort on the control algorithm. Foremost, it is proposed to use a single-harmonic active power line conditioner (SHAPLC) which can be seen as a variant of the traditional APLC. The difference with the APLC is that the SHAPLC only injects a single-harmonic current. The total number of SHAPLCs required to achieve the control of harmonic mitigation is justified by the need of compensate the harmonic distortion in the power system at frequencies whose presence is most dominant. Finally, the size of the SHAPLCs will be optimally obtained, by solving a non-linear programming problem that minimises the SHAPLCs injection currents.
The determination of the size of the SHAPLC using an optimisation approach is a very important part of the solution procedure, particularly important due to fact that one of the main disadvantages of the SHAPLC device is the higher cost against passive filtering solutions [10]. Therefore, the proposed solution procedure in this paper is aimed to obtain the lesser rms filtering current (i.e. smaller size) of the SHAPLCs that would do the work of compensating the harmonic distortion under selected guidelines. Under the same idea, as explained in detail in Section 2.2.1, the number of SHALP is determined according the harmonic distortion pattern in the power network, and increased only when necessary, in order to incorporate the smaller number of SHAPLCs.

Statement and formulation of the problem and determination of the reference filtering currents
The APLC has demonstrated to be an effective compensation device to control the mitigation of harmonic voltage distortion in distribution systems [1][2][3][4][5][6][7][8][9][10]. Its working principle consists in injecting harmonic currents into the electric network as corrective measure and the goal is to mitigate the harmonic distortion so that the harmonic indices IHD and THD meet those levels imposed by the recommended standards. Usually, the two main stages during the APLC planning are: (i) determining the location and number of compensation devices and (ii) obtaining their injection currents. Now, even though a previous concept for harmonic mitigation similar to the SHAPLC was presented in [2], the procedure was not finally intended to assure that the levels of THD meet the standard requirements. In addition, in [2] the location bus for the compensation device is chosen by testing the algorithm for every single bus and selecting the best bus candidate by observing and comparing the obtained results. In the methodology developed in this contribution the authors assume that the system harmonic impedances and the bus harmonic voltages are known; it has been also assumed that there is no coupling between harmonics.

Harmonic propagation because of the SHAPLC injection current and the IHD index
First of all it is necessary to establish the basis on how the system harmonic voltage is altered by the injection current of the SHAPLC and how this injection current is reflected on the IHD index. The SHAPLC injection current should mitigate the voltage magnitudes for the harmonic h through the entire electric network; the change in the nodal harmonic voltage can be expressed as where the subscripts old and new correspond to bus voltages at any bus n before and after the SHAPLC injection current, respectively. The superscript h refers to the harmonic h. In terms of the elements of the network impedance matrix; the voltage change at bus n, due to SHAPLC injection current at bus p, can be expressed as where n = 1, 2, …, N, and where Z h np , is the harmonic transfer impedance between buses n and p, which includes both real and imaginary parts. I h p , is the injection current at bus p for the harmonic h. Individually, the new harmonic voltage at bus n, can be expressed as (see (3)) where the superscript r and i are the real part and imaginary part, respectively.
On the other hand, according to IEEE Std-519 [16], the IHD index for the harmonic h at bus n is given by The restriction imposed by the IEEE Std-519 establishes that for all harmonics h at bus n the following applies Substituting (3) into (4) and using (5), and after some algebraic manipulation, for convenience in further analysis, the inequality restriction (5) can now be expressed as (see (6)) where N is the total number of nodes and H is the set of harmonics under consideration. The inequality restriction expressed in (6) represents the IHD index at bus n for the harmonic h, as a function of the SHAPLC injection current. Finally, we have a first expression to work with, in order to examine the performance of the proposed methodology of the SHAPLC planning, detailed in the sections to follow.

Determination of number and location of SHAPLCs
In the proposed methodology, the determination of the number of SHAPLCs is based on an iterative process, and the location for each one of the SHAPLCs is determined with a feasibility/sensitivity combined approach. At the end of the first stage of this planning process it is assured that the final configuration of SHAPLCs is able to mitigate the harmonic voltage distortion throughout the entire electric system, below minimum recommended levels by the IEEE Std-519. corrective measure. Therefore, the SHAPLC should be placed to compensate the harmonics that are most predominant in the harmonic distortion. One SHAPLC has to be considered for each harmonic h for which the IHD index is beyond the recommended limit at any bus. Then, this preliminary number of SHAPLC has been considered for the SHAPLC planning process, the best location for each one of the SHAPLCs should be identified according to Section 2.2.2.
Once the preliminary number of SHAPLC has been considered, and its buses had their best location identified, the test for the THD index has to be tested according to Section 2.2.3. If this test is not met, a new SHAPLC has to be added to the previous group of SHAPLCs and its best location identified, so that the test condition for the THD index has to be tested again, and this process will be repeated iteratively until the condition for the THD index is satisfied.

Location of SHAPLCs:
The determination of the location of a SHAPLC is based on a two-step procedure, that is, (i) it is necessary to find which bus is a feasible candidate bus for placing the SHAPLC. This is done by identifying the bus from which it is possible to mitigate the harmonic distortion and to control the IHD index below recommended levels at all nodes of the system for a particular harmonic h of interest. (ii) If as a result of the first step, several feasible buses exist, then it is necessary to identify which of the feasible buses is the best bus candidate. This is achieved with a sensitivity analysis that identifies the candidate bus that is most sensitive, so that the necessary injection current in pu to produce the desired results is less than the necessary current that would be required if the SHAPLC is placed at any of the other feasible nodes.
Identification of feasible buses: In (6), we have expressed the IHD index as an inequality restriction in function of the SHAPLC injection currents. To identify a bus p as a feasible bus, it is necessary to determine if the SHAPLC injection current at bus p is able to guarantee that (6) is satisfied at all buses of the electric system for the harmonic h. In [2], a graphical representation given as the general form of a circle is used to determine the feasible area of solution. In this contribution, a different graphical representation is chosen by rearranging (6) and taking it from the general form of a circle to the canonic form of a circle, which has a centre (q, w) and radius r, that is, For different values of r we can graphically see (7) as the concentric circles of Fig. 1a. For a value of r = 0, the circle is a single point, that is, the centre (q, w), which represents null harmonic distortion because of the injection currents, see Fig. 1a.
On the other hand, the largest value of r, that is, the exterior circle of Fig. 1a, called distortion limit circle (DLC), represents the maximum value for which the inequality condition of (6) still holds.
Therefore, it is convenient to convert the inequality condition expressed in (6) into an equality condition, which we can later evaluate as the exterior circle, that is, the DLC. To continue with the transformation of (6) to the form of (7), we have re-arranged (6) as given in (8), and then we complete the squares in (8) to obtain the result expressed in (9) (see (8)) (see equation (9) at the bottom of the next page) After factorising the left side and some algebraic manipulation on the right-hand side of (9), it can be reduced to the form of (10) which has the same form of (7), that is, the canonic form of a circle with centre at (11) (see equation (10) at the bottom of the next page) In (11), we have the injection current at bus p which will produce a null harmonic distortion at bus n, for the harmonic h. From an optimisation point of view, it is easy to demonstrate that the injection current in (11) is a minimum of (8), [3,6]. For different values of α, for example, 0 < α ≤ 0.03, the value of the radiuses of the concentric circles, as illustrated in Fig. 1b, are given by From (12), it is clear that the radius of the concentric circles of Fig. 1b for a bus n and harmonic h, is in function of the impedance matrix element between the bus n and the bus of   SHAPLC injection current p, the nodal voltage at fundamental frequency, and α. Therefore, the exterior circle identified above as DLC, will be found at the recommended value α, for example, α = 3%, see Fig. 1b. The centre of the DLC is given for the values of the injection current as expressed in (11). It is important to notice that the area of the DLC of Fig. 1b represents the feasible region where the values of the injection currents of the SHAPLC meet the inequality condition of (6). In order to determine if a bus p is a feasible bus for the placement of the SHAPLC, it is required that the DLC of all nodes do share a common feasibility region where each DLC has an index IHD ≤ α (α = 3%).
Here, a three step procedure is proposed. It consists of three conditions that have to be satisfied to assure that a bus p is a feasible candidate bus to place the SHAPLC. Although a similar procedure was proposed in [2], (11) and (12) developed in this contribution will enable us to obtain closed formulae for these three conditions, and then further evaluations can be easily computer-programmed.
Redundant circles must be taken out of the analysis: If a DLC circle contains a smaller DLC circle, see Fig. 2, then the larger circle must be taken out of the analysis. This condition is intended to simplify the procedure by eliminating unnecessary calculus of further analysis. The feasibility region of the larger circle will be represented by the smaller circle.
The identification of a larger circle containing a smaller circle can be achieved by comparing the distance between the centres of both circles with the difference between their radiuses, as illustrated in Fig. 2.
If the relationship of (13) is satisfied for any bus m, the DLC of the respective bus n must be taken out of further analysis The remaining circles, after the first condition is satisfied, should be included in a set Ch. Circles in the Ch set must share a feasibility region: One way of knowing if two DLCs share a feasibility region is to compare the distance between their centres with the sum of their radiuses, see Fig. 3. If two DLCs do share a feasibility region in common, the following relationship holds In a similar way, (14) can be expressed in the general form (15) to include all the buses in the set Ch. If the    Existence of a common feasibility region: Once the second condition is satisfied, it must be ensured that a common feasibility region exists for all the circles in set Ch. For this case, a point F can be identified as contained into a common feasible region by comparing the distance from the centre of the DLC in question to the feasible region with the radius of the DLC. Fig. 3 illustrates this condition, where F is any point contained in the feasible region. Therefore if the condition (16) holds for all the DLCs included in the set Ch then F is contained in the common feasible region, thus demonstrating that the common feasible region actually exists. If (15) and (16) are satisfied for the set Ch, the bus p is a feasible bus for the placement of the SHAPLC. Finally, for a particular harmonic h, a set Ph will be formed with the group of feasible buses C h n=1 d nF ≤ r n (16) Sensitivity analysis over the feasible buses: Once we have determined the buses that are feasible candidates for the placement of the SHAPLC for the harmonic h, it is necessary to determine, among the feasible buses, which bus is the best option for the SHAPLC location. To achieve this aim, a sensitivity analysis is proposed. Here, we have used the simplest interpretation of the sensitivity analysis, that is, the rate of change of a function due to the unitary change of a dependent variable. Therefore, it is required to estimate the rate of variation of the harmonic voltage in the electric network produced by the current injection of a SHAPLC at bus p. According to (2) the harmonic voltage variation produced by the SHAPLC injection current at bus p including the rectangular components can be expressed as The magnitude of the sum of the rate variation of ΔV h , with respect to a unitary chance of each one of the rectangular components of the SHAPLC current injection is given by The best bus location, for the harmonic h, will be the bus with the largest sensitivity value according to (18). This means that for the harmonic h, an injection current at the most sensitive bus will produce the highest distortion, higher than the distortion that would be produced in any other bus in the set of feasible buses Ph; though in this case, the distortion will be a planned and favourable distortion, provided by the SHAPLC as a corrective measure.

Test for the THD index:
Once we have chosen the set (number and location) of SHAPLCs that assure that the IHD index meets the recommended limits by the IEEE Std-519, there is still an important situation to take into consideration. Is this configuration (number and location) of SHAPLCs, capable to provide enough harmonic mitigation, in order to meet the imposed limits by the IEEE Std-519 in the THD index throughout the electric network? To answer this question, we have to determine how much distortion mitigation can provide the SHAPLCs, at its respective harmonic h. Then an evaluation on the THD index for all buses will give us the result. According with the IEEE Std-519 the THD index is to be evaluated by (19) and the THD index should meet the inequality condition (20) where β is the recommended limit by the IEEE Std-519 (β = 5%). The square of the new harmonic voltage, for harmonic h at bus n, is given as (see (21) using (21) the new nodal voltages for the harmonic h due to the injection of the SHAPLC current from bus p is (see (23)) where the subscript AB stands for all buses. To proceed with the search of the maximum harmonic distortion mitigation that a SHAPLC can provide through the entire network, we use a direct approach to minimise (23). Deriving (23) with respect to the rectangular components of the SHAPLC injection current and solving for the injections currents we get the current for which the SHAPLC, placed at the bus p, will achieve the maximum voltage harmonic mitigation through the entire network for the respective harmonic h, that is where the subscript max stands for the SHAPLCs injection current which provides the maximum harmonic mitigation at bus p for harmonic h.
Once (24) and (25) are calculated for all the SHAPLCs included in the analysis, these injection currents are substituted in (22). The evaluation of (22) will indicate if the selected set of SHAPLCs is able to provide enough harmonic mitigation to meet the IEEE Std-519 imposed limit on the THD index.

Determination of the optimal injection currents
The objective function considered in the SHAPLC planning is to minimise the SHAPLCs injection currents. From an optimisation point of view it is more convenient to work with the square magnitudes of the SHAPLC injection currents, that is In (26), P is the set of nodes considered for the location of a SHAPLC. The calculation of the optimal injection currents, and sizing of the SHAPLCs, is based on solving the constrained non-linear optimisation problem (27). In this problem, the harmonic distortion indices, IHD and THD, must meet IEEE Std-519, according with (6) and (22), respectively. The non-linear optimisation problem is a convex optimisation problem, so a local minimum that satisfies the non-linear conditions of (27) will also be a global minimum [17] Min f obj s.t. IHD h n ≤ a h [ HC, n = 1, 2, . . . , n, . . . , N THD n ≤ b n = 1, 2, . . . , n, . . . , N where HC is the set of harmonics considered for which a SHAPLC has been considered (Fig. 4).

Proposed SHAPLC planning procedure
A step by step SHAPLC planning procedure, illustrated in Fig. 5, is described next: 1. Identify the harmonic for which the IHD index is higher than recommended at any bus of the electric system. Add

Case study
The proposed solution algorithm for SHAPLC planning is tested using a 30-bus distribution system [18]. The objective is to determine the number and location of the SHAPLCs as well as their optimal injection currents to control the system harmonic voltage distortion through the entire power network. The system data is given in [18]. The harmonic sources are three six-pulse converters located at buses 16, 17 and 22, respectively. The non-linear loads information is given in Tables 1 and 2. For a proper description of the non-linear loads, the non-linear loads information in Table 2 gives both the active and reactive part of the load. On the other hand, the percentages of harmonic currents given in Table 1 corresponds to the characteristic harmonic content given the said non-linear load. In Fig. 5, the IHD and the THD indices, respectively, of the power system are illustrated. It can be observed that the system is highly harmonic distorted, and the values of IHD and THD are beyond the limits recommended by IEEE Std-519.

Solution procedure
The seven-step procedure proposed for SHAPLC planning is as follows: 1. Fig. 5a shows that the maximum permissible limit α = 3% for the IHD index is violated for the harmonics 5 and 7 at several buses of the electric system for both harmonics. Even though the harmonic distortion is present at other harmonics, their IHD index values are not beyond the maximum permissible limit. Therefore, the set HC is only formed as HC = {5 7}. 2. According with the feasibility analysis for IHD mitigation; for the harmonic 5 the set of feasible nodes is P5 = {10, 17, 21, 22}, and coincidentally for the harmonic 7 the set of feasible node is P7 = {10, 17, 21, 22}. 3. The sensitivity values, δh, for each bus included in sets P5 and P7, at their respective harmonic h, are summarised in Table 3. The sensitivity analysis shows that the best option for the placement of the SHAPLCs for the harmonics 5 and 7, are the buses 22 and 10, respectively. 4. The injection currents of the SHAPLCs for maximum harmonic mitigation from the buses 22 and 10 for    5. The injection currents calculated in step 4 are the injection currents for which the maximum harmonic distortion mitigation that the SHAPLCs can provide is obtained. The results in the harmonic mitigation are illustrated in Fig. 6. Fig. 6a shows the maximum reduction of IHD index for harmonic 5 with a SHAPLC placed at bus 22 and Fig. 6b shows the maximum reduction of IHD index for harmonic 7 with a SHAPLC placed at bus 10. Substituting the values of the SHAPLC injection currents obtained at step 4 and evaluating the inequality in (22), we get that condition (22) is satisfied for all buses of the system. Therefore, the set of SHAPLCs can sufficiently mitigate the harmonic distortion throughout the network to meet the harmonic distortion indices IHD and THD as recommended by IEEE Std-519. As a result, only two SHAPLCs are necessary; one for the harmonic 5 at bus 22 and one for the harmonic 7 at bus 10. We skip step 6, as there is no need to iterate the solution process, and go to step 7 to solve the non-linear programming problem, in order to obtain the optimal injection currents. 6. Now that we know the number and location of the SHAPLCs needed to achieve the sought harmonic mitigation, it is required to determine the minimum injection currents that will produce that the harmonic indices be within permissible limits.
The non-linear optimisation problem to be solved according to (27) Then, the optimal injection currents for the SHPALCs are  Fig. 7 shows the harmonic distortion indices in the electric system after the SHAPLCs compensation with the optimal injection currents. Fig. 7a illustrates how the IHD index meets permissible levels at all buses of the system. The active inequality condition, that is, nodes with IHD = 3%, associated with the IHD index are: at bus 17 for the harmonic h = 5, and at bus 22 for the harmonic h = 7. On the other hand, the THD index illustrated in Fig. 7b is satisfied at all nodes of the system. The only active inequality condition, that is with a THD = 5%, is at bus 10.
In the case of load variation, the filtering injection current should be calculated again by solving (27), provided that injection currents for maximum harmonic mitigation obtained with (24) and (25) still satisfies the THD recommended limit for all buses. Special attention must be given to the case of network reconfigurations; if that is the case, conditions for feasibility and location should be recalculated as well, to assure that the methodology is correctly applied.

Conclusions
In this paper, an alternative procedure in the APLC planning field for harmonic voltage mitigation in power networks has been proposed. The proposed planning methodology is based on the SHAPLC concept, which basically injects  only a single-harmonic injection current as the corrective measure.
The number and location of the SHAPLCs are determined to meet the recommended guidelines by the IEEE Std-519, so that, the determination of both, number and location, takes into consideration the severity of harmonic distortion present in the electrical network.
The proposed procedure has shown some important computational advantages, without neglecting the importance of assuring that harmonic distortion limits are met after compensation. For instance, due to the reduced injections currents, a significant reduction on the computational effort needed to compensate the harmonic distortion in the electric network has been obtained, as compared to conventional multiple APLC planning. This is clear since to meet the IHD index guidelines the control algorithm for each SHAPLC unit is only required to be solved for a single-harmonic frequency, and a combination of the SHAPLCs can also ensure that the harmonic index THD will be satisfied at all buses.
The analysis and formulation have been developed in detail, providing mathematical justification/validation and closed formulae that allow the control algorithm to be completely programmed and incorporated in a software package.
Even though the proposed SHAPLC planning has shown remarkable results in the 30 nodes system illustrated in the case study section, the methodology can be extended in future research to include the APLC planning in larger-scale systems.
The proposed methodology assumes that the system harmonic impedances and all the bus harmonic voltages are known; it has been also assumed that there is no coupling between harmonics. Both considerations are currently being addressed in follow-up research by the authors.