Binary-weighted photonic digital-to-analogue converter

: In fifth-generation (5G) mobile networks the available bandwidth and the range of carrier frequencies will be significantly larger than in current mobile networks. To cope with the consequent increase in traffic 5G networks will be digital radio over fibre (DRoF) networks for deploying cloud radio access networks. As conventional electronic data converters in DRoF networks suffer from jitter at very high giga sampling rates while photonic data converters have better performance, photonic data converters are considered a fundamental building block of a DRoF system for 5G. All photonic DRoF (AP-DRoF) is a suitable candidate for carrying future 5G data traffic from a central station for delivery to remote pico-cells. In this study an 8-bit binary-weighted photonic digital to analogue converter (PDAC) for AP-DRoF is proposed for the conversion of an optical bit stream generated by a photonic analogue-to-digital converter into optical analogue signal for delivery to the photo diode of a remote station's photonic antenna. The potential performance of the proposed PDAC is investigated at a sampling rate of 60 Gsample/s through simulation in terms of its effective number of bits and spurious free dynamic range.


Introduction
A digital radio over fibre (DRoF) system has better performance than a conventional analogue radio over fibre system in terms of its dynamic range, resource sharing, transmission range and nonlinearity [1,2].Furthermore, digital systems are flexible, more reliable and robust against additive noise from devices and channels, achieve better dynamic range than analogue systems, and more conveniently interface with other systems.Electronic analogue-to-digital and electronic digital-to-analogue converters (EADC and EDAC, respectively) are the interfac0es between the analogue and the digital worlds of electronic signal processing, and are the key components of existing DRoF systems [2,3].EADCs and EDACs are susceptible to timing jitter of the sampling clock.Therefore, using a low jitter femtosecond scale mode-locked laser (MLL) sampling clock in a photonic high-speed system introduces photonic data converters that represent a significant breakthrough in terms of jitter suppression and provide more bandwidth and a higher effective number of bits (ENOBs) at multi giga sample per second.An all photonic DRoF (AP-DRoF) system will be a promising candidate for dominating the electronic data conversion challenges faced by under exploited fourth-generation and future fifth-generation mobile communication networks [4].Photonic analogue-to-digital converter (PADC) and photonic digital to analogue converter (PDAC) are fundamental building blocks of AP-DRoF systems.The focus of this paper is on the design of an efficient PDAC for AP-DRoF.
Several schemes have been proposed for PDAC.A 2-bit PDAC architecture at 1 Gs/s based on the weighting and summing of highspeed MLL pulses is reported in [5].In [6] a binary weighted (BW) architecture is proposed in which electrical binary data is converted to an optical analogue signal using a BW attenuator to modulate electrical digital data using a series of Mach Zehnder Modulators (MZMs), and an optical coupler as an incoherent adder.
In [7] a BW architecture is proposed which is similar to the architecture of [6], electrical binary data is converted to an optical analogue signal that uses a BW splitter that splits continuous wave (CW) laser power into binary levels, then similarly to the architecture in [6], this CW BW intensity laser power is used to modulate the electrical digital data using a series of MZMs and an optical coupler used as an incoherent adder.In [8] a binary PDAC is proposed which is composed of two main parts, a multi-wavelength optical differential phase-shift keying transmitter and a direct detection receiver.In the transmitter, N channels of independent lightwaves of different wavelengths pass through N MZMs, respectively.A high speed 4-bit PDAC is demonstrated in [9] based on four-channel integrated optical phase modulators for a 12.5 GS/s sampling rate.In [10], PDAC architecture is proposed where weighted multi-wavelength pulses are delayed and summed in the time domain through dispersion and each weighted pulse with a specific wavelength corresponds to a bit of input digital data.This architecture is evaluated for a 3-bit PDAC with a sample rate of 2.5 GS/s.In [11], a PDAC based on a multi-electrode Mach Zehnder Interferometer is presented.A 4-bit bipolar PDAC architecture based on optical differential quadrature phase shift keying modulation coupled with differential detection is reported in [12] at a 2.5 GS/s sampling rate.
In this paper, an optical PDAC based on a binary-weighted architecture is proposed for converting a received optical bit stream, that is generated by a PADC in the central station of a AP-DRoF system, into an optical analogue signal for feeding to a photo diode in a photonic antenna in the remote station [13,14].The proposed scheme is significantly different to the methods outlined above, in the proposed scheme an optical bit stream is synchronised by MLL pulses [13] using a purely optical gate, an optical BW attenuator and amplifiers are then used to improve the signal to noise ratio.The main weakness of previously reported architectures is that for an additional N bits the attenuation rate will be increased by order of 2N, whereas in the architecture proposed in this paper the use of an attenuator and amplifiers avoids this problem.
The rest of this paper is organised as follows: in Section 2 the proposed binary-weighted PDAC architecture is described.The simulation model of the system and the simulation results are analysed in Section 3, and compared with results published for other PDAC architectures.Finally, the conclusions are presented in Section 4.

Binary-weighted PDAC architecture
A functional block diagram of an N-bit DAC is shown in Fig. 1.In an N-bit digital-to-analogue converter (DAC), parallel input digital signals are converted into an analogue value S out that is given by: IET Optoelectron., 2017, Vol.11 Iss. 1, pp. [20][21][22][23][24][25][26][27][28] This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) where, G ref is a reference value and B j are the binary values of order j of the digital value of the input signal, B 0 and B N−1 are the least significant bit (LSB) and the most significant bit (MSB), respectively.
The minimum change of analogue output S out , which is equal to the step size, can be related to the LSB's value.B N − 1 B 1 …B 0 = ′0…01′.From (1), the minimum change of analogue output or step size q s can be given by: (2)

2-bit PDAC concept
The concept of the proposed architecture of a 2-bit PDAC system is based on (1) and shown in Fig. 2. In this scheme, the two optical digital input signals P Bit 2 and P Bit 1 represent the MSB and LSB bits power with identical magnitude.The LSB powerP Bit 1 is attenuated by 6 dB and added to the power of the MSB, P Bit 2 after passing through a delay block that imposes a delay of T d seconds that matches the propagation delay of the attenuator block so the two input pulses are added in-phase, the phase matching of the corresponding optical signals could be performed by other methods using a non-linear medium [15][16][17].A directional coupler is used as the optical adder.This architecture is based on the BW summation of the corresponding electrical fields of the MSB and the LSB that would be generated in a PADC and which are assumed to be in-phase.A 6 dB attenuator is inserted in the path of the LSB optical signal because of the half amplitude contribution of the LSB in the BW PDAC algorithm, as the optical power is related to the square of electrical field of the corresponding electrical signal.Furthermore, an optical adder performs summation on the input optical fields.By considering the phase matching assumption, the vector summation can be simplified to adding the corresponding scalar quantities otherwise there is some error.If we assume the electrical field corresponding to the optical signal at the input of the attenuator is E Bit 1 (t), expressed by: where A(t) is the electrical field amplitude and ω 0 is its angular frequency.The electrical field corresponding to the optical signal at the output of the attenuator E Bit 1 ′ (t) is given by: where and T d ′ ≃ T d is the insertion delay of the attenuator which is negligible in comparison with the input pulse width.Therefore, the square of the corresponding electrical field of the summation signal at the output of the optical adder is given by: where E D/ A (t) and E Bit 2 ′ (t) are the corresponding signal electrical fields of the optical signal at the output of the PDAC, and of the MSB optical signal at the output of the delay block T d , respectively.
As optical power is related to the square of the corresponding electrical field amplitude, the output power of the 2-bit PDAC is given by: Where K is a constant.Consequently, where

8-bit PDAC deployment
On the basis of the 2-bit PDAC architecture, an 8-bit PDAC design is shown in Fig. 3.This scheme is composed of upper and lower nibbles.For the upper nibble, optical amplifiers are used and their gains are scaled down based on their binary order similarly to the fundamental 2-bit PDAC block but deployed for two nibbles (4 bits).For example, , where G B(n) is the gain of the optical amplifier to which P Bit n is applied.This circumvents the need to deploy very high attenuations at lower value bits.Meanwhile, this procedure is repeated for the lower nibble by replacing the BW gain amplifiers with the corresponding attenuators.In the simulated model, the gains of the amplifiers were 12, 6 dB for G B8 , G B7 , respectively, with 4 dB of the noise figure (NF) and the attenuation of the attenuators was 0, 6 12, 18, 24 and 30 dB for Att B6 , Att B5 , Att B4 , Att B3 , Att B2 , and Att B1 , respectively.To mitigate the amplified spontaneous emission (ASE) noise of the amplifiers, an optical Gaussian bandpass filter (OBPF) of central wavelength 1545 nm and bandwidth of 6 nm is used following each amplifier.
A parameter that indicates the dynamic performance of the nonlinearity of the data converters is spurious free dynamic range (SFDR), which is defined as the ratio of the rms signal amplitude to the rms value of the peak spurious signal over the bandwidth of interest where the spur is typically a harmonic of the original signal [18,19].The ENOB is given by: ENOB = SFDR dBc /6.02 (10) It is assumed that the added electrical fields are in phase because when optiwave-optisystem is used to simulate the adding of electrical fields, phase mismatch between the electrical fields causes some error which is taken into account in the simulation.This would impact on the SFDR of the simulated PDAC.The bandwidth of the OBPF is chosen based on the sampling frequency of the DAC to improve the SFDR.The filter bandwidth of these filters has a significant impact on the performance of the PDAC in terms of its SFDR magnitude.The adder is an optical coupler.

Analysis and discussion
The gain of the electrical field corresponding to the output resulting from the optical digital signal input of the 2-bit PDAC at 60 Gsample/s sampling frequency is given by the slope of the line shown in Fig. 4, which highlights that the proposed 2-bit PDAC has a suitably linear gain over its operational range when compared with the gain of a linear transfer function model of the input output relationship.
Differential non-linearity (DNL) is a measure of the uniformity of the quantisation step size over the operating range of the PDAC converter.In this performance characteristic each step size in the quantisation process is compared with the ideal step size with the difference in magnitude reported as the non-linearity error.Integral non-linearity (INL) is defined as the deviation of the code midpoint values from the ideal.The differential error is a measure of the error in step size at a specific location within the PDAC transfer function.INL is the summation of these individual errors over the entire PDAC transfer function [20].The relation between DNL and INL is given by: The INL and DNL of the proposed 2-bit PDAC was investigated to assess its non-linearity.As shown in Fig. 5, the INL for digital input '01' is about 0.0072 × LSB and for digital input '10' is about 10.0018 × LSB, where '×' denotes the multiplication operation.The DNL for digital input '01' is about 0.0072 × LSB, for input '10' is about −0.0091 × LSB, and for input '11' is about 0.0018 × LSB.This illustrates that the proposed 2-bit PDAC has appropriate linearity with respect to digital input signal changes.
To evaluate the dynamic performance of the proposed PDACs, a sample analogue electrical signal can be sampled and quantised using a PADC.Then, the generated optical digital data fed to the proposed PDACs to demonstrate their performance individually [13,14].After detection of the recovered analogue signal using a photo diode, the output electrical spectrum of the 2-bit PDAC is given in Fig. 6.In Fig. 6, the fundamental signal amplitude at 586 MHz is −2.6 dB and the strongest spur signal magnitude at the third harmonic is −13.3 dB, therefore, the SFDR is 10.7 dBc.Fig. 7 enables the assessment of the linearity of the proposed 8bit PDAC.Fig. 7 shows the proposed PDAC has a suitable linear amplitude response.Fig. 8a shows that the maximum and minimum INL are about 10.84 × LSB and −7.64 × LSB, respectively, while Fig. 8b illustrates the DNL of the PDAC, which has a maximum difference non-linearity of 15.04 × LSB and a minimum difference non-linearity of −10.69 × LSB.
Fig. 9 shows the fast Fourier transform (FFT) spectrum of the two recovered radio frequency (RF) electrical signals, of a simulated AP-DRoF system that includes the 8-bit PADC and  PDAC, in two back-to-back tests, one for a single tone and other for dual tones.These signals are at the output of the photo diode in the remote station of the AP-DRoF system that detected the regenerated optical analogue signals using the proposed 8-bit PDAC [4,13].Fig. 9a shows the output spectrum at the output of the PDAC for a single tone RF input at 15 GHz.The FFT amplitude of the fundamental signal is 2.3 dB and the amplitude of the strongest spur signal is −22.5 dB.Therefore, the SFDR is about 24.8 dBc.Using a 8 bit PDAC, the number of quantisation bits has increased, hence the SFDR seems to be improving, compared with that of a 2 bit PDAC.Another index to assess the converter performance is two-tone intermodulation distortion (IMD), which is measured by applying two spectrally pure sine waves to the PADC at frequencies f 1 and f 2 , usually relatively close together.The amplitude of each tone is set slightly more than 6 dB below full scale so that the PADC does not clip when the two tones add in phase.The second-order products fall at the frequencies that can be removed by digital filters.However, the third-order products 2f 2 -f 1 and 2f 1 -f 2 are close to the original signals and more difficult to filter out.This IMD can significantly reduce the dynamic range of the data converter.
Fig. 9b enables the evaluation of the system functionality in response to two-tone input at frequencies 15 and 14.8 GHz.The output spectrum shows that the fundamental signals amplitudes at frequencies 14.8 and 15 GHz are −3.6 and −3.4 dB, respectively, and the strongest inter-modulation distortion amplitude is −18.96dB.
To demonstrate the PDAC functionality in the time domain a simulated 5 GHz bandwidth RF signal is sampled with 60 GHz MLL pulses in the PADC.The sampled signal is quantised using a modelled PADC with ENOB equal to 4.1 at the central station of the AP-DRoF [13].The input RF reference signal, MLL pulses train, and discrete samples of the PADC are given in Fig. 10.The generated 8 bits of optical data are that fed to the input of an 8-bit PDAC are shown in Fig. 11 in which 'p' refers to pico and 'm' refers to 'mili'.
The quantised output bits of the PADC are shown in Figs.11ah, which, respectively, correspond to Bit 8 to Bit 1 at the PADC's output.As shown in these figures, each sample of the optical signal in Fig. 10c is quantised into 8 bits that correspond to a sample of the original signal.According to the sampling shown in Fig. 10b, the following optical digital data is generated at the output of the PADC, the first to eighth sample are quantised to '11111111', '01011111', '00000111', '00111111', '00011111', '00011111', The discrete-time domain optical signal, which is the converted back 8 bits digital optical signal and the corresponding electrical signal of the filter output of the detected discrete-time optical signal are shown in Fig. 12.This figure demonstrates the proper functioning of the proposed 8-bit PDAC.Fig. 12a shows the discrete-time domain optical signal power of the converted back digital optical signal.This discrete-time optical signal is detected using a photo diode and the corresponding discrete-time electrical signal is fed to an analogue 15 GHz bandwidth Gaussian low pass filter to smooth it out, giving the analogue electrical signal of Fig. 12b.
Table 1 gives a comparison of the proposed 8-bit BW-PDAC with other reported PDAC.

Conclusions
While a number of different methods have been reported for implementing PDACs to convert digital electrical signals to the corresponding analogue optical signals, in this paper a BW-PDAC is proposed, which optically converts optical signals bit streams to their corresponding optical analogue signals.The 8-bit BW-PDAC architecture has been modelled and simulated in the optiwaveoptisystem simulation tools environment.The simulated SFDR at the output of the PDAC of a back-to-back setup of PADC and PDAC is 24.8 dBc, therefore the ENOB of the 8-bit-PDAC is 4.11.
As the proposed BW-PDAC comprises several optical amplifiers and optical filters, the cost of such system is currently unaffordable.In any future work undertaken to implement this system, using an integrated modulator with optical amplifiers will reduce the cost of the system [14].Furthermore, the unit cost of optical amplifiers and optical filters can reasonably be expected to fall as optical networking becomes ubiquitous and its underpinning technologies advance.In this respect this it is hoped that this work can contribute additional momentum to this trend by identifying additional drivers for the associated investment required.

Fig. 1 Fig. 2
Fig. 1 Functional block diagram of a DAC

Fig. 6 Fig. 7 Fig. 8
Fig. 6 Output electrical magnitude spectrum at the output of the 2-bit PDAC at Nyquist zone at 60 GHz sampling rate, with the input fundamental frequency at 586 MHz

Fig. 9 Fig. 10 Fig. 11 Fig. 12
Fig. 9 FFT spectrum of the two RF electrical signals (a) FFT Spectrum at the output of the 8-bit PADC and PDAC back-to-back test at Nyquist zone at 60 GHz sampling rate of an input single-tone frequency at 15 GHz, (b) FFT Spectrum at the output of the 8-bit PADC and PDAC back-to-back test at Nyquist zone at 60 GHz sampling rate of two-tone input at frequencies 15 and 14.8 GHz