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Scan cell design for launch-on-shift delay tests with slow scan enable

Scan cell design for launch-on-shift delay tests with slow scan enable

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Most scan-based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but requiring a fast scan enable. A low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge is presented. The new design is much more efficient when compared with other recent proposals and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve transition delay fault coverage approaching 95% for the ISCAS89 benchmarks.

Inspec keywords: integrated circuit testing; clocks; flip-flops; integrated circuit design; delay circuits

Other keywords: clock edge; global control signal; launch-on-capture delay tests; scan cell design; launch-on-shift delay tests; slow scan enable; flip-flops; transition delay fault coverage

Subjects: Logic circuits; Digital circuit design, modelling and testing; Logic and switching circuits; Other circuits for digital computers; Other digital circuits; Semiconductor integrated circuit design, layout, modelling and testing

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