Transient voltage stresses in MMC–HVDC links – impulse analysis and novel proposals for synthetic laboratory generation

To evaluate and optimise insulation coordination concepts for state of the art high-voltage direct current (HVDC) transmission systems, appropriate test voltage shapes are required for laboratory imitation of occurring stresses. While especially transient voltages in the monopolar modular multilevel converter (MMC)–HVDC links show an extensive deviation from commonly applied switching impulse shapes, this study focusses on the analysis of over-voltages subsequent to direct current pole to ground faults. Additionally, novel methods for synthetic laboratory test voltage generation are proposed. Based on simulated transients occurring during fault scenarios in different symmetrical monopolar ±320 kV MMC–HVDC schemes, curve fitting, and related analysis techniques are used in order to compare simulated over-voltages with standard test voltage shapes. Moreover, these techniques further allow the identification of novel relevant impulse characteristics. Subsequently, design considerations for the generation of non-standard impulses based on single-stage circuits are derived and discussed. Those synthetically generated voltages may, later on, provide the basis for future investigations on related dielectric effects caused by those non-normative over-voltages.


Introduction
High-voltage direct current (HVDC) transmission is currently a vital part of the area of electric energy transmission technology. While modular multilevel converters (MMCs) have been steadily established due to their superior characteristics [1], insulation coordination aspects -especially if rated voltages increase even further -require additional investigations. Until now, applicable switching impulse (SI) test voltage ratings for MMC-HVDC monopolar configurations are not yet fully standardised compared with high-voltage alternating current [2,3] and line commutated converter-HVDC schemes [4]. Nevertheless, recent research activities and provided case studies in the field of transient system simulations show a rising interest in corresponding overvoltage shapes [5][6][7][8][9]. While the latter research activities are mostly related to cable stresses, associated impacts on air clearance calculation [10] at the converter direct current (DC) busbar are still rare.
Even though calculation methods (e.g. [11]) based on normative standard impulses, such as lightning impulses and SIs, provide first steps towards insulation strategies, no general standard exists for voltage source converters [12]. Under consideration of [10], major differences between standard SI and occurring over-voltages are evident. To evaluate associated consequences for insulation coordination concepts, transient voltage stresses at the converter DC busbar in MMC-HVDC schemes need to be evaluated, analysed and compared with normative impulses in greater detail. Furthermore, besides theoretical influence analysis based on accessible test data results, novel proposals to generate nonstandard laboratory test voltage waveforms need to be derived.

Transient simulation of MMC-HVDC transmission schemes
To cover the variety of available transmission technologies and different corridor lengths in recent MMC-HVDC projects, different monopolar schemes are investigated in this contribution as visualised in Fig. 1. The following paragraphs provide a brief overview of the selected technical system parameters, on the different scenarios and load flow set points as well as on implemented system protection loops. An appropriate simulation time step is selected as slow-front transient events shall be evaluated [4].

System modelling
Converter and system modelling are of significant importance to derive feasible results in transient time domain investigations. According to [13], a consensus on implementation possibilities has been defined, where the selected classification (Types 1-7) is related to the underlying study purpose. Within the context of this simulation framework, either Type 3 for single sub-module related faults or Type 4 (computationally improved) Thévenin equivalent representations [14,15] for other system faults are utilised. Further in depth analysis related to insulated-gate bipolar transistor (IGBT) and diode modelling is elaborated in [16], where appropriate conformity of non-linear and simplified (on-/off-resistance) power electronic device representations is identified. As a remark it should be noted that switching actions of power electronic devices (e.g. changing diode conduction states) require appropriate software-specific electromagnetic transients (EMT) solving techniques in addition to suitable modelling approaches. Besides, frequency dependent XLPE cable and overhead line (OHL) models are considered as short circuit faults and the following sub-module blocking events are investigated. Especially an appropriate representation of a travelling wave phenomenon is inevitable to determine transient voltage overshoots with an acceptable accuracy at the DC clamps. In addition, surge arrestor columns have a severe impact on the system overvoltage level as well as on shape and need to be modelled carefully. Due to the fact that slow-front transients are in the scope of this contribution, a non-linear V-Icurve with regard to this type of stimulus has been selected and is implemented accordingly. This leads to the related SI protective level of 512 kV (1.6 pu) @ 1 kA discharge current. The detailed V-I characteristics related to a 30/60 μs current shape are attached within Table 1, while other relevant system parameters are summarised in Table 2.

Transmission scenarios
Besides basic design, the selected transmission technology as well as different power transfer set points influence shape and severity of over-voltages due to inherently different system conditions. To address these differences appropriately, in total eight scenarios are further evaluated. Hereby, varying fault resistances (between 1 m Ω − 30 Ω ) during a DC pole to ground fault at the positive pole of MMC 1, as depicted in Fig. 1, are investigated. The directly affected station MMC 1 is a DC current controlled converter, MMC 2 at the opposite end acts as the DC voltage regulating station. Additionally, both converters obtain a reactive power reference of +300 MVA (cap.). An overview of all scenarios is provided in Table 3.

System protection
To derive feasible over-voltages, appropriate system behaviour after fault inception is required. Therefore, the implementation of protection loops at both converter stations of the MMC-HVDC link is an essential aspect to be considered. In contrast to ideal (non-delayed) converter blocking subsequent to arbitrary DC faults, results considering current and voltage thresholds, protection delays and measurement-quantity-triggered module blocking provide more realistic results in terms of accuracy. Especially the latter issue leads to time-shifted travelling wave phenomena affecting the transmission system. This has a significant influence on transient voltage peaks, their instant and maximum level.
This contribution considers both a simple converter arm overcurrent and a DC pole to ground voltage imbalance detection concept. The scheme has been initially proposed and described in [10]. While the overcurrent threshold is related to technical boundaries of state of the art IGBTs (maximum allowed peak current 2.7 kA), the voltage imbalance criterion is related to a deviation from normal operation conditions (imbalance > 50 kV). A brief overview of this scheme and relevant parameters is shown in Fig. 2.

Transient simulation results
Based on the underlying simulation framework introduced in Section 2, results obtained using PSCAD™-EMTDC™ with a simulation time step 5 μs for the OHL and 25 μs for the different cable schemes are presented in the following paragraphs. Besides a discussion of main characteristics like general shape, rate of rise and remaining steady state levels, results for the different transmission scenarios are additionally compared amongst each other.

Scenario OHL 150 km
For an OHL transmission setting with a total length of 150 km, transient over-voltages at the healthy pole of MMC 1 are shown in   While especially recent offshore MMC-HVDC links for wind farm connection are relatively short regarding the transmission distance, which is reflected in the last scenario cable 50 km shown in Fig. 4c, the visible initial voltage post-fault step nearly disappears. Generally, due to reduced wave travelling times, occurring converter-individual effects become blurred and are more challenging to be differentiated based on the obtained transients. System behaviour tends towards the initial OHL response in terms of general shape, as overall system capacitance continues to decrease for a shorter cable length.

Evaluation methods
Insulation coordination which either follows well-established standards known from AC [2,3] or is based on guidance for line commutated HVDC converters [4] aims for the determination of withstanding voltages (U w ). These withstand voltages are related to their corresponding representative voltages and over-voltages (U rp ) determined by system analysis. During the converter design stage focusing on transient phenomena, the determination of representative voltages and over-voltages is inevitably linked with fault scenario analysis, as shown in Section 3. To evaluate and compare those results, derived and applied methods which allow a simulation data reduction (SDR) followed by different overvoltage approximations concepts and related evaluations are presented in the following.

Simulation data reduction
In a first step, maximum occurring over-voltages based on an extensive set of simulations for each scenario need to be determined. Therefore, data is condensed into one worst-case voltage-time curve u SDR t for t flt ≤ t ≤ t sim, max . This voltage time curve consists of the maximum absolute voltage per time step and scenario. As a major difference compared with [10], different power flow configurations (sub-scenarios a and b) are not considered separately, aiming in the derivation of a more generic voltage time curve in dependence on transmission technology (IDs: O-150, C-150, C-100, C-50).

Derived methods for over-voltage approximation
Influences of SI voltages superimposed on a DC pre-stress are investigated in [17,18]. Here it is concluded that for practical external air insulation influences of DC pre-stress may be disregarded, if instead impulses having the combined amplitude U SI + U DC are considered. As concluded in [10], voltage shapes differ significantly from any normative SI, therefore a deeper analysis of impulse shapes is required.

Estimation of SI amplitudes (SI estimation):
Voltage time behaviour of normative SI is described using the solution for the differential equation of single-stage equivalent circuits for impulse voltage generation [19] where U A instead of (U 0 /K) ⋅ (1/ α 2 − α 1 ) is used. For normative SI 1/α 1 yields to 1/α 1 = 3155.0 μs and 1/α 2 = 62.48 μs, respectively. Instead of using simplified peak amplitudes only, (1) allows the determination of U A using least-squares solution techniques for non-linear curve-fitting problems. Generally, Levenberg-Marquardt algorithm may be chosen, whereas solution techniques using the trust-region-reflection (TRR) method also achieve similar results. For this purpose, the TRR method is chosen.

Double exponential impulse (DEI) estimation:
With the objective of improving the approximation by a DEI on simulated data, the degree of freedom in (1) is increased allowing the approximation of U A , α 1 and α 2 . Resulting exponential impulses u DEI contain fault related transients and steady state DC voltage prior to the fault.

Superimposed DEI estimation:
Known from HVDC cable tests [20] and motivated by previous considerations presented in [10], superimposed testing is considered as a promising approach for laboratory imitation of obtained over-voltages and for identification of relevant overvoltage impulse parameters. Therefore, DC steady-state operational voltage prior to the fault is subtracted and DEI estimation is carried out in order to obtain u SDEI . This approximation is especially meaningful as it allows the determination and discussion of relevant circuit parameters for a laboratory imitation of simulated over-voltages utilising superimposed double exponential impulses (SDEIs).

Derived methods for evaluation of overvoltage approximation
To evaluate the goodness of derived overvoltage approximations and to highlight major differences between considered scenarios, different criteria are used. For an assessment of the voltage curve approximation over an evaluation time window t flt ≤ t ≤ t eval the method uses the basic idea of voltage-time areas. The overall peak voltage approximation is rated using parameter q fit, max , whereas parameter q fit, A is used to quantify overall voltage approximation In the case of SI estimation u i = u SI t , in the case of DEI estimation u i = u DEI t and in the case of SDEI estimation u i = u SDEI t + U DC t flt are considered. Besides this, amplitude comparison uses q fit, max introduced as focusing on obtained maximum voltages with the same underlying restrictions as for (2).

Derived methods for quantification of transmission technology influences
The quantification of influences related to chosen transmission technologies is carried out based on the evaluation of suitable voltage time approximations. For this aim, parameters such as time to peak t p and time to half t 50 ratios are used. Parameter q p allows time to peak, q 50 time to half and factors q A, ∞ and q A, eval voltage time curve area comparison. Quantities follow each using suitable overvoltage approximations for u i, e t , t p, e , t 50, e as the enumerator and for u i, d t , t p, d , t 50, d as the denominator. Time parameters for time to half values are obtained using the numerical solution of (1).

Over-voltage analysis
This section is separated into four parts. First, obtained results for overvoltage approximation using different fitting horizons are shown and associated impacts are discussed. This results in the selection of a suitable evaluation time window for further analysis. Second, the evaluation of the voltage curve approximation is presented. Third, differences in chosen transmission technologies are investigated. Last, key results for overvoltage approximation and analysis are summarised.

Over voltage approximation
Considered curve fitting horizons are closely linked to potential post fault measures within the system. Initially, as previously shown in [10], subsequent to t flt = 1.45 s no further overvoltage reduction measures till t sim, max = 1.84 s are assumed. In contrast, assuming feasible AC circuit breaker opening delays prior to related DC de-energisation measures yield reduced overvoltage durations and therefore to a shorter curve fitting horizon. The reduced horizon is, in this case, limited to t sim, red = t flt + 40 ms, corresponding to two AC grid cycles after the fault. For the purpose of identifying influences related to additional delays, e.g. due to fault detection or AC breaker restrikes, additional cases are considered using t sim, red, 60 = t flt + 60 ms and t sim, red, 100 = t flt + 100 ms. Related impulse parameters are shown in Tables 4 and 5.
Results of overvoltage approximation for 150 km OHL and 150 km cable transmission based on SDR voltage time curves using the reduced curve fitting horizon t flt ≤ t ≤ t sim, red = t flt + 40 ms are presented in Fig. 5. From the first impression, results appear similar to those presented in [10] using the increased curve fitting horizon (t flt ≤ t ≤ t sim, max = t flt + 390 ms) but show greater deviations if impulse parameters shown in Tables 4 and 5 are taken into account.
In the case of cable transmission, time to half values decrease and impulse amplitudes increase when the chosen fitting horizon is shortened. Furthermore, a slight reduction of time to peak values in case of SDEI is observed, whereas a reduction in horizon length leads to a slight increase of time to peak values for DEI impulses. Considering OHL transmission (O-150) sporadic discrepancies on those observations arise which are related to the chosen curve fitting methods in the least square sense.
Nevertheless, it is obvious, if no countermeasures are considered, time to half values are tremendously long. Especially in the case of cable transmission technology, this is leading to values being up to 18 times larger for DEI and SDEI estimation. Whereas, if a reduced fitting horizon of t flt ≤ t ≤ t sim, red is used, time to half values are reduced from several seconds to milliseconds. Therefore, it is considered more reasonable to focus on obtained curve parameters taking into account the reduced curve fitting horizons related to overvoltage reduction measures.
Time to peak values is less affected by post fault behaviour. Furthermore, it is evident for SDEI impulses that time to peak decreases with a reduction of cable length, whereas the shortest time to peak is found for OHL. Besides this, SDEI impulses clearly show that time to half values is minor affected by cable length, but  A quantification of the voltage curve approximation is carried out in the next section.

Evaluation of over-voltage approximation
To evaluate the goodness of the overvoltage approximation, methods introduced in Section 4.3 are applied leading to results shown in Table 6. The evaluation window boundary is equalised to t eval = t flt + 40 ms in order to guarantee a consistent investigation of all voltage curve approximations independent of the chosen curve fitting horizon.
It is found that voltage time areas q Fit, A are for SI within the range of about q fit, A = 16.55%. Therefore, voltage time areas are significantly smaller in the case of SI approximation compared with simulated over-voltages. Furthermore, occurring SI peak voltages q fit, max = 167.7% are leading to peak stresses being roughly 1.7 times higher compared with obtained simulation results. Approximations of q fit, A and q fit, max are found unaffected for SI approximation if either extended or reduced curve fitting horizon is chosen. This is related to the aspect that only parameter U A is determined and the overall duration of normative SI compared with chosen curve fitting horizon and evaluation window is rather short, causing minor effects on related results. Changes are observed for DEI and SDEI approximation methods as the degree of freedom for the underlying optimisations is significantly increased.
Voltage curve approximation is utilising curve fitting methods which are carried out in the least square sense. Therefore, from a mathematical perspective, it is a causal consequence that those overvoltage approximations using equal curve fitting horizon and evaluation window will obtain superior results in terms of voltage time areas q fit, A , whereas, this is not necessarily valid for evaluation of peak voltage approximation q fit, max .
These findings are noticeable if q fit, A and q fit, max for DEI and SDEI impulses are considered. As the value chosen for t eval is identical with t sim, red , approximations using the reduced curve fitting horizon are leading to a perfect reconstruction of the voltage time area. Contrary, if the extended curve fitting horizon is considered all evaluation parameters are smaller, as discussed above. Evaluation value q fit, max indicates that representation of simulated over-voltages is less accurate if DEI approximation is chosen. Good results are obtained using SDEI approximation utilising the reduced curve fitting horizon (t flt ≤ t ≤ t sim, red ). Therefore, it can be concluded that an increased curve fitting horizon will lead to longer time to half values but in a less accurate representation of peak voltages.
Besides this, for the determination of relevant impulse characteristics of over-voltages in MMC-HVDC links, suitable  evaluation windows, and curve fitting horizons are required. As already mentioned in Section 5.1, it is considered more reasonable assuming suitable post fault measures leading to reduced overvoltage durations and related curve fitting horizons. With the intention of analysing and imitating over-voltages during DC pole to ground faults, SDEI impulses are capable of representing the voltage time area. However, for an accurate representation of peak insulation stresses the peak voltage approximation (parameter q Fit, max in Table 6) demands for additional safety margins. This especially gains importance if SDEI impulses are considered as a test voltage waveform, or are used in future investigations related to associated dielectric effects.

Quantification of transmission technology influences
Based on derived voltage time approximations it is now possible to address aspects caused by different transmission technologies. Therefore, parameters introduced in Section 4.4 are used in conjunction with overvoltage approximations based on SDEI. In this case, t p , t 50 , u i, e and u i, d used in (4)-(6) refer to the superimposed impulse voltages, which are applied to constant DC voltage U DC t flt . For determination of q A, eval based on (7), impulse data u i, e and u i, d are set as u i = u SDEI t + U DC t flt . The overall transmission technology comparison matrix, focussing on the reduced curve fitting horizon and SDEI approximation, is shown in Table 7. Additionally, Fig. 6 summarises SDEI voltages for all four scenarios.
It is found that voltage time areas for t flt ≤ t ≤ t eval are nearly unaffected by chosen transmission technology as parameter q A, eval ≃ 1. If overall voltage time area is taken into account, voltage time areas are less affected by cable length but by transmission technology. Parameter q A, ∞ indicates that voltage stresses associated with voltage time areas are reduced in the case of OHL to ∼73-74% compared with cable transmission. Similar observations are enabled focusing on time to half. The parameter q 50 is nearly independent of cable length but tremendously affected by transmission technology. Time to half is in the case of a 150 km cable 1.54 times larger than for a 150 km long OHL. Peak voltages Û DC + I , see Table 5 (values in bold), are found within the same range with the highest values occurring for OHL systems. This value is 4.4% larger than for the shortest cable transmission (50 km). Considering only peak voltages Û I of the superimposed impulses, this effect is slightly more severe as values occurring for OHL systems are 11.1% larger. In the case of time to peak, indicator q p allows the identification of cable length and transmission technology influences. OHL has the shortest t p which is compared with a C-150 ∼31 times larger. Besides this, a reduced cable length is always accompanied by a reduced time to peak.
Indicative values for extended curve fitting horizon and SDEI can be found in [10] and for the sake of closed-form representation in Table 8. Deviations are mainly due to the chosen SDR method, which combines both power flow configurations.

Summary of results
Based on yet presented results, several key aspects are found.

Laboratory test voltage generation
Under consideration of presented results in Section 5, it is considered most promising to use superimposed impulses for a synthetical approximation of simulated over-voltages within a high voltage laboratory. This entitles an evaluation of the influences on discharge and material behaviour and their related causes on the dielectric strength in the case of non-standard impulses. To discuss related influences and challenges for the design of test circuits indicative considerations based on single-stage equivalent circuits are derived. A description of considered design rules will be given in Section 6.1. In the subsequent section, aspects related to the realisation of superimposed test setups are presented and associated consequences are discussed. A comparison between voltage approximations derived in Section 5 and those voltage time curves obtained using circuit simulation is presented in Section 6.3.

Consideration and design rules for single-stage equivalent circuits
Focusing on impulse voltage generation, circuit parameters as shown in Fig. 7, may be obtained following [19,21] leading to simplified (8)- (11). If Marx generators are used, their related single-stage equivalent circuit needs to be determined in the first place It is found that parameters α 1 and α 2 identified during voltage approximation are vital for solving the equations above and are therefore presented in Section 6.2.1. Besides this, values for C 1 and C 2 are required. More accurate efficiency calculation is achieved, if instead of (10) is used. Test circuit design is usually carried out under various limitations, such as available laboratory equipment, space considerations and relevant electrical parameters of the device under test (DUT). Due to this, circuit design will be discussed within this contribution in a more general manner. For a realistic circuit parameter estimation, a capacitance of 750 nF with a maximum voltage of 100 kV per stage of Marx-generator is assumed. Besides this, the degree of simplified efficiency following (10) is set to a minimum of η = 85%.

Superposition of an impulse voltage on a DC voltage
This section describes the necessities for impulse voltage generation. It is followed by additional considerations which need to be taken into account for superimposed tests.

Impulse voltage generation:
The highest amplitude of superimposed voltage approximation is in combination with the claimed degree of simplified efficiency demanding for at least three stages of a Marx generator. This is resulting in a maximum capacitance of C 1 = 250 nF and leads to C 2 = 44. 2 nF. Table 9 lists the overall curve parameters and their related circuit parameters. To guarantee the validity of the equations above, the assumption R 1 ≫ R 2 ≫ R 3 is used. Large values for R 1 are required in order to minimise any further charge process of C 1 and C 2 during the tail of the impulse. Instead of using large values for R 1 , it may also be technically considered switching off the AC supply which feeds the diode rectifier prior impulse triggering as depicted in Fig. 8.

Superposition of impulse voltage on DC voltage:
To separate DC voltage generation from impulse voltage generation and vice versa, additional components such as blocking capacitors and protection resistors are required. Those components and additional measuring devices need to be considered in circuit design as well. An overview of the overall circuit for synthetic overvoltage imitation is provided in Fig. 8. Following [22], values are set for the blocking capacitor C 4 = 1000 pF and for impulse measuring using a capacitive voltage divider C 3 = 500 pF. These additional components affect the circuit behaviour. Especially the blocking capacitor in combination with the DUT will act as a capacitive voltage divider limiting the maximum peak voltage. Assuming that this voltage divider reduces the single-stage circuit efficiency by another η VD = 85%, this is limiting maximum capacitance of the DUT to C 5 = 176 pF. To keep the efficiency of the Marx generator and its calculated parameters, as shown in Table 9, the value for C 2 needs to be corrected to C 2 * following: Overall efficiency for the peak amplitude at the DUT may, in this case, be approximated using η ges = η ⋅ η VD = 72.3%. To obtain more accurate values for efficiency and consequently for the relevant impulse capacitor loading voltage U DC, L calculation follows (11) and takes the efficiency of the additional capacitive voltage divider into account as shown in Table 10.
To obtain circuit parameters for a simulation of the DC voltage generation, similar assumptions as chosen for the Marx circuit are used, leading to C 6 = 187.5 nF.
Based on [22], for measuring and protection devices values of R 4 = 2.5 MΩ, R 5 = 1100 MΩ and R 6 = 500 kΩ may be chosen. If these parameters are considered for the depicted circuit design retroactive effects on DC generation cannot be excluded. In this case, the resulting impulse voltage at the DUT will be heavily affected due to the resistive voltage divider is given by R 4 and R 5 . Bearing information from Table 9 in mind, the ratio (U DC t flt /Û I ) ≃ 1.85, …, 2.02 is found. Therefore, the same ratio has to be chosen for R 5 /R 4 , resulting in a realisation using values of R 5 = 1100 MΩ and R 4 = 550 MΩ. If instead R 4 = 2.5 MΩ and R 5 = 5 MΩ are chosen, an impact on time to half values will be observed, as an additional and non-negligible discharge path for C 5 has to be considered. Instead of taking the ratio of the resistive voltage divider into account, whilst avoiding a further deenergisation of C 5 , a diode stack behind R 4 provides a remedy. In this case, for a technical realisation, the impulse strength and parasitic capacitances of the used diodes need to be considered. Besides this, retroactive effects have always been considered in order to avoid any damage to the used DC generator.

Results of circuit simulation and discussion
Within this subsection results based on circuit simulation for a laboratory impulse generation of SDEI voltages are presented. This is followed by a discussion of the results and capabilities of the presented circuit.

Results
: For all simulations, the following parameters are used: C 1 = 250 nF, C 2 * = 43.6 nF, C 3 = 500 pF, C 4 = 1000 pF, C 5 = 176 pF, C 6 = 187.5 nF, R 1 = 1 MΩ, R 6 = 500 kΩ, R 7 = 1 MΩ. Besides this, all circuit components are considered as ideal including spark gaps (SGs). Overall three different realisations are discussed for scenarios O-150 and C-150. The first realisation (A) considers the use of a resistive voltage divider R 4 = 550 MΩ and R 5 = 1100 MΩ. For the second realisation (B), the same values are chosen for R 4 and R 5 but an additional diode after R 4 is used. The third implementation (C) follows [22] with R 4 = 2.5 MΩ and R 5 = 1100 MΩ, but is also extended with an additional Diode after R 4 . For O-150 simulations, impulse forming resistance values are set to R 2 = 285.6232 kΩ and R 3 = 0.4941 kΩ, whereas impulse capacitor loading voltage is set to U DC, L = 243.90 kV and a Table 9 Voltage waveform data (see Table 5), related exponents and calculated circuit parameters following (8) and (9) SDEI Curve fitting horizon t flt ≤ t ≤ t sim, red t p in μs t 50 in ms α 1 in 1/s α 2 in 1/s Û DC + I in kV   Fig. 9.

Discussion and further opportunities for the presented circuit:
It is noteworthy that overall design considerations and aspects presented in Sections 6.2.1 and 6.2.2 lead to a good realisation of voltage waveforms accompanied by the derived novel impulse parameters. Associated nominal times to peak are ranging from 155 μs ≤ t p ≤ 4775 μs and time to half values from 58.4 ms ≤ t 50 ≤ 90.1 ms. Superior results are obtained, if R 4 is followed by a diode stack as considered for realisation (B). Table 11 presents the results and related errors for each parameter.
Similar results are found for implementation (C), resulting for O-150 in Δ t p − C ≃ 0.6%, Δ t 50 − C ≃ 0%, Δ Û − C ≃ − 0.1% and for C-150 in Δ t p − C ≃ 0.4%, Δ t 50 − C ≃ 0.2%, Δ Û − C ≃ − 0.4%. If realisation (A) is considered associated errors are higher, especially considering the time to half values, leading for O-150 approximation to Δ t p − A ≃ − 1.1%, Δ t 50 − A ≃ − 15.1%, As a consequence of the associated errors related to realisation (C), it is found that the use of the diode stack is beneficial in order to keep the shape of impulses as close as possible to the desired voltage waveform. If the use of this additional diode is not applicable, a different supportive measure may be provided by the impulse generator. In Section 6.2.1, a further charge process of C 1 and C 2 was stated avoidable in order to stop an enlargement of the wave tail. This identified causality provides valuable benefits. A further charge process may act as a supportive measure to enlarge the wave tail, especially if the de-energisation caused by R 4 , R 5 (Section 6.2.2) or additional parallel resistances of used capacitors or currents due to surface contaminations are taken into account.
Furthermore, the use of switching concepts besides commonly used air filled SGs may be broached in order to ensure the desired trigger operation. If commonly used air filled SGs cannot guarantee reliable operation without a self-extinguishing arc, compact pressure controlled gas insulated SGs may provide a remedy. Besides this, circuits based on semiconductors, as recently presented in [23], seem promising in the future. Those may provide additional benefits if electrode erosion or trigger problems are taken into account.  After a brief conclusion, an outlook motivating further research aspects is presented in the following.

Conclusion
Transient overvoltage stresses in MMC-HVDC links have been simulated and investigated for DC pole to ground faults. As slow front transients do occur, a feasible non-linear surge arrestor V-Icurve needs to be selected. Furthermore, varying fault resistances (between 1 mΩ and 30 Ω), different load flow scenarios and appropriate post-fault system behaviour influences -caused by the system protection setting -are considered. To determine as well changes occurring in over-voltages associated with different transmission technologies, simulations are carried out for OHL and cable schemes. The analysis of obtained simulation results shows that normative test voltage waveforms such as SIs only allow a poor approximation of the occurring over-voltages. As occurring voltage shapes differ significantly from any normative SI, further analysis of the impulse shapes is carried out. It is concluded that double exponential voltages provide benefits for analysis and imitation of occurring over-voltages in MMC-HVDC schemes. Superior results are obtained if a double exponential voltage superimposed on a constant DC offset is considered. The use of curve fitting techniques allows the identification of several valuable overvoltage parameters. Time to peak significantly increases with increasing cable length and is the fastest for OHL transmission, whereas time to half is the shortest for OHL transmission technology and in the case of cable transmission larger. Peak voltages are found around the same range independent of the chosen transmission technology.
To propose a laboratory imitation of those impulses, circuit design based on single stage impulse equivalent circuits is presented and related aspects for superimposed testing are derived and described. Those synthetically generated voltages may, later on, provide the basis for follow-up investigations on related dielectric effects caused by those non-normative over-voltages.

Outlook
The field of transient voltage stresses in MMC-HVDC systems is a vital area for high-voltage research. While solely monopolar configurations have been investigated within this initial study, ongoing considerations related to bipolar topologies and their different characteristics seem essential. Additionally, refinements regarding modelling accuracy related to superposed high frequent occurrences meanwhile or subsequent to converter blocking are desirable.
Concentrating on test voltage application, the use of Marx generators or their related single stage equivalent circuits is one option, especially if in the first instance consequences for air insulation as mentioned in Section 4.2 and [10,11,24] are addressed. The presented concept may result in application challenges if the derived novel waveforms are applied on DUT with an increased capacitance. In this case, charging the DUT to peak voltage and utilising a defined ohmic path for a slow discharge process is considered beneficial for the generation of the relevant time to half values. The regard of a negative impulse superimposed on this positive decaying voltage may provide the relevant dynamics. Besides this, achieving time to half values whilst using a controllable DC supply or more general an appropriate voltage converter with sufficient output current is seen promising. For this purpose, utilising high-voltage transformers, as presented for SI generation in [25] may provide benefits for a future generation of presented novel impulse shapes.
Moreover, the consideration of parasitic influences, as presented in [26] during circuit simulation prior to laboratory implementation is seen valuable. Future experiments are considered precious in order to evaluate the effects caused by those non-standard impulses on HVDC insulation. As accessible research data of air discharge mechanisms for impulses under consideration of DC pre-stress are only available for SI, those investigations are of high importance besides investigations on cables and their accessories. Furthermore, if analogies to already existing normative test voltages can be concluded, a more transparent way for distance estimation during the design stage of a converter, as mentioned in [10,11,24] will be enabled.