Structure and non-blocking properties of bidirectional unfolded two-stage switches

Two-stage switch networks are an emerging design option for relatively small-capacity space switches. They are classiﬁed into two categories: folded and unfolded. Although folded switches have been well stud- ied, research on unfolded two-stage switch networks (UTSNs) remains limited. Here, non-blocking UTSNs are considered. First, a new UTSN design is presented that consists of input and output switch modules (ISMs and OSMs) using bidirectional switching techniques. The pro- posed UTSN is represented by B( n , m , r ), where n , m , and r denote the number of input ports of the ISM, number of OSMs, and number of ISMs, respectively. Second, the maximum number of rearrangements for B( n , n , r ) is proved to be (cid:2) ( r − 1) / 2( n − 1) (cid:3) in general, whereas it is limited to two when n ≥ r . The strictly non-blocking condition for B( n , m , r ) to be m ≥ n + 1 is also determined. Finally, it is shown that the switch hardware complexity becomes minimal at n = √ N / 2 and saturates at N 2 /2 as N → ∞ .

Introduction: As serious attention has been recently given to spacedivision multiplexing technology for scaling optical network capacity [1], multistage space switch networks have become a key component for creating high-port-count optical interconnects and cross-connects [2,3]. Although the three-stage Clos architecture is a well-established and highly practical design principle for scalable space switches [4], twostage networks (TSNs) are emerging as a new design option for relatively small-capacity switches [5]. TSNs are classified into folded and unfolded switches. The folded TSN is equivalent to a three-stage Clos network, and its structure and non-blocking capabilities are well known [6]. In contrast, unfolded TSNs (UTSNs) are not yet completely understood; there are few types of UTSNs, all of which are rearrangeably non-blocking (RNB) [7]. To the best of our knowledge, this is the first study to consider a strictly non-blocking (SNB) UTSN. First, we present a new design principle of UTSN, which consists of input and output switch modules (ISMs and OSMs) with a bidirectional switching capability. The proposed UTSN is represented by B(n, m, r), where n, m, and r denote the number of input ports to the ISM, the number of OSMs, and the number of ISMs, respectively. Second, we formulate the maximum number of rearrangements for B(n, n, r) and the minimum value of m to satisfy the SNB condition for B(n, m, r). Finally, we briefly estimate the complexity of the switch hardware.
Structure of B(n, m, r): A design example of B(n, m, r) is shown in Figure 1, where there are r ISMs and m OSMs; each is denoted by I p , 1 ≤ p ≤ r, and O q , 1 ≤ q ≤ m. Every ISM has n inputs, and the total number of inputs is given by N = nr, while every OSM has N outputs, of which the first and second halves are provided at the top and bottom edges. Every pair of an ISM and an OSM is interconnected with a pair of internal links, that is, one link between an outlet on the top of the ISM and an inlet on the left side of the OSM and the other link between the bottom of the ISM and the right side of the OSM. Here, we use 'inlet' and 'input' (and similarly 'outlet' and 'output') quite differently: 'inlet' and 'outlet' are internal ports, whereas 'input' and 'output' are external ports.
Although the ISM is an n × 2m switch, it can be implemented by an n × m bidirectional crossbar switch (BXS) and n 1 × 2 switches, as shown in Figure 2. Every input signal to the ISM may be switched to its outlet at either end of the column. Let (i, k) be a connection between an input i, 1 ≤ i ≤ n, and an outlet k, 1 ≤ k ≤ 2m, in the ISM. Similarly, let (l, j) be a connection between an inlet l, 1 ≤ l ≤ 2r, and an outlet j, 1 ≤ j ≤ N, in the OSM, which can be implemented by an r × N/2 BXS, as shown in Figure 3. Every jth outlet in the OSM is coupled in the jth output via a passive coupler, which is shown as a dashed triangle in Figure 1. The Because every input signal in Figure 2 is routed to either a left or right inlet through a 1 × 2 switch, every row of ISMs takes only a single signal at most. It can be seen that every column of ISMs and OSMs is shared by a couple of signals, that is, one signal headed for the top and the other signal down for the bottom. However, we assume that every column of the ISMs and OSMs can take a single signal at most to avoid blocking. As a result, every row of OSMs also takes a single signal, because the column of an ISM is combined with a row of an OSM. Note that these constraints will be referred to in the following discussion of the nonblocking properties. If the ISM is implemented with a conventional n × m crossbar switch: m outlets at the top of the ISM are not necessary and the 1 × 2 switches should be relocated to the left inlets of the OSM. In both cases, the 1 × 2 switches cause no exchange between any pair of connections; thus, their column cannot be counted as an independent switching stage [7]. Non-blocking properties of B(n, m, r): Although our main objective is the SNB condition for B(n, m, r), let us begin with the rearrangement process for B(n, n, r), which provides some insights into the SNB condition. It is evident that no blocking occurs in the ISMs because the ISMs function as an incomplete n × 2m switch under the constraints. Blocking can occur in the OSM in the following worst-case scenario: Assume that n -1 inputs of an ISM I p1 , 1 ≤ p 1 ≤ r, are already connected with n -1 outputs. Without loss of generality, we assume that the n -1 input signals enter the OSMs from their left inlets. Then, the last connection request in I p1 , which is denoted by the dashed line in Figure 4, is issued. Further, assume that the request has a destination output j 0 , 1 ≤ j 0 ≤ N/2, while j 0 = j 0 + N/2 corresponds to I p2 , 1 ≤ p 2 ≤ r, as shown in Figure 4, where we assume that p 2 = p 2 + r and all of the n inputs to I p2 are already in use. Note that the prime mark denotes the inlets on the right side and the outlets on the top edge. Blocking occurs in the j 0 th column in O n owing to the violation of the constraints. In this case, it can be seen that every j 0 th column in the OSMs, except O n , is idle. If the new connection (p 1 , j 0 ) is rerouted to the j 0 th column in an OSM O b , 1 ≤ b ≤ n -1, which is connected to I p1 , an existing connection denoted by (p 1 , j 1 ) in O b should be moved to O n , only where inlet p 1 is idle. However, this rearrangement can cause blocking if the j 1 th column in O n is already used. Note that j 1 = j 0 holds because the blocking in the j 0 th column has already been addressed. In other words, each existing connection in O n experiences a rearrangement only once. Because there are r -1 existing connections in O n , the rearrangement process will last r -1 times at most between O n and O b . Let R 1 be the number of rearrangements in this case. Now, consider another rearrangement process that begins with p 2 in O n . If the new connection (p 1 , j 0 ) is provided in O n , the existing connection (p 2 , j 0 ) should be rerouted to the j 0 th column in O b . However, blocking will occur in the OSM because there is another existing connection (p 2 , j 2 ) or (p 2 , j 2 ), with j 2 = j 0 and j 2 = j 0 , which should be moved to O n , only where inlets p 2 and p 2 are idle. The second rearrangement process also lasted r -1 times at most. Let R 2 be the number of rearrangements in this case. Because the connections involved in R 1 and R 2 are different from each other, the following relation holds: (1) Both R 1 and R 2 are integers, and the minimum number of rearrangements is expressed as where x denotes the largest integer less than or equal to x. Note that O b was fixed in the above discussion. By examining the number of rearrangements for every O b , the minimum number of rearrangements at large, denoted as R 0 , can be derived as follows in a similar manner to the derivation of Equation (2): When n ≥ r, we have more freedom to exchange the blocked connection (p 1 , j 0 ) with other existing connections. As shown in Figure 4, I p1 and I p2 have n -1 and n connections under the worst-case scenario. These assumptions allow us to choose an outlet, which is not included in the r -1 existing connections in O n , out of the n existing connections in I p2 . Accordingly, when we move (p 2 , j 0 ) to an appropriate OSM, of which the j 3 th column is occupied by an existing connection, that is, (p 2 , j 3 ) or (p 2 , j 3 ), whereas the j 3 th column in O n is idle. As a result, the number of rearrangements is reduced to two at most.
Based on the above discussions, we readily have an SNB condition as follows: When m = n, we need to move the blocked connection to another OSM, where blocking can occur. However, if we set m = n + 1, the last connection request may be provided in the (n + 1)-th OSM, where both p 1 and j 0 are idle. Consequently, the SNB condition for B(n, m, r) is given by Hardware complexity of B(n, m, r): When m = n + 1, the total number of cross-points becomes large and is expressed as a function of n as follows: where the first and second terms in Equation (5) correspond to the crosspoints of the OSMs and ISMs, respectively. C p (n) has a minimum value at n opt = √ N/2 , as follows: C p (n opt ) converges to N 2 /2 as N → ∞. It is worth noting that some RNB UTSNs also have N 2 /2 cross-points [7]; hence, the bidirectional UTSN has achieved SNB properties with approximately the same crosspoints as RNB UTSNs.

Conclusion:
We unveiled a new design principle for UTSNs using bidirectional switches. The bidirectional UTSN is represented by B(n, m, r), which consists of r ISMs, each of which has n input ports, and m OSMs. We proved that the maximum number of rearrangements for B(n, n, r) is given by (r − 1)/2(n − 1) in general, whereas it is limited to two when n ≥ r. We identified the SNB condition for B(n, m, r) to be m ≥ n + 1. We also found that the UTSN hardware complexity becomes minimal at n = √ N/2 and saturates at N 2 /2. Although experimental performance analyses need to be conducted in future studies, the bidirectional UTSN could be a potential candidate for scalable space switches.

Conflict of Interest:
There are no conflicts of interest to be declared.