A dual-rate burst-mode receiver with rapid response and high CID tolerance for XGS PON

A burst-mode receiver chip-set including a preampliﬁer and limiting ampliﬁer which can recover both 9.95 Gb/s and 2.49 Gbit/s packets within a short 64.3 ns preamble time is described in this paper. This receiver is also able to settle while receiving a packet that includes over 72 bits of CID. To realise these characteristics, we placed a rapid peak- detecting AGC in the preampliﬁer IC and a rapid discharge block between the ICs. Our receiver achieved high sensitivities of –31.2 dBm for 9.95 Gb/s and –36.5 dBm for 2.49 Gb/s within a 64.3 ns preamble and with a payload packet that includes 72 bits of CID. In addition, this receiver meets the ITU-T G.9807.1 E1 and G.987.2 E1 Recommendations even if a packet includes such long stretches of constant signal level as 768 bits of CID in the case of 9.95 Gb/s and 256 bits of CID in the case of 2.49 Gb/s.

Introduction: Since the standardisation of G-PON in 2003, gigabit-class passive optical networks (PON) have spread worldwide because they enable the CAPEX and OPEX of optical access networks to be reduced by having multiple optical network units (ONUs) share the same optical line terminal (OLT) and feeder fibre. G-PON can support 2.5 Gb/s downlink and 1.25 Gb/s uplink. IP traffic is increasing steadily, and the recent increases in the demand for video services and remote working caused by Covid-19 [1] are motivations for upgrading the speed of optical access systems. To improve network performance, XG-PON was standardised in 2010, and XGS-PON followed in 2016. The XG-PON and XGS-PON systems respectively support 2.5 and 10 Gb/s uplink speeds, in the same 1260 to 1280 nm wavelength range. These systems depend on coexisting with the widespread G-PON systems to minimiSe the CAPEX of these new systems. As a result, XGS-PON systems are found working alongside XG-PON in some networks. In that case, the OLT receiver is required to support dual-rate operation because the same uplink wavelength channel is used. In addition, due to the widespread use of G-PON systems, a loss budget better than 29 dB is also required for XG-PON and XGS-PON systems, especially in rural areas. This means that the dynamic range of the receiver should be as wide as possible in order to minimise the types of burst-mode receiver required. Further, it is necessary for the burst-mode receiver to recover the received signal during a short preamble in order to maximise the upstream throughput. These requirements normally induce signal degradation by patterns of consecutive identical digits (CID), but good performance is still required. To date, several 10 Gb/s burst-mode receivers have been reported for feasibility studies [2][3][4][5]. However, to the best of our knowledge, there have been no reports of meeting all the following requirements: 10 and 2.5 Gb/s dual-rate operations, wide dynamic range, rapid burst-mode response, and high CID tolerance.
As reported in this paper, we have developed a receiver for an XGS-PON OLT with a wide dynamic range, rapid response, and high samesign proof stress. In order to achieve a wide dynamic range, we have developed automatic gain control (AGC) and automatic threshold control (ATC) circuits for incorporation in the receiver preamplifier TIA. In order to achieve the required rapid response, the AGC and ATC are constructed from circuits that can converge in nanosecond order. Further, in order to achieve both rapid response and high CID tolerance, we adopted a means of switching the time constant of the high-pass filter formed by the AC coupling capacitor between the TIA and the limiting amplifier (2R). With these unique receiver ICs, we achieved high sensitivities of -31.2 dBm for 9.95 Gb/s and -36.5 dBm for 2.49 Gb/s with packets having a 64.3 ns preamble and whose payload includes 72 bits of CID. The ITU-T G.9807.1 E1 and G.987.2 E1 recommendations were also met, even if a packet includes such long stretches of constant signal level as Configuration of dual-rate burst-mode receiver: To accommodate both 9.95 Gb/s and 2.49 Gb/s data rates, we developed a preamplifier and a limiting amplifier which can rapidly adjust their own operating states to suit each packet. Figure 1 shows the block diagram of the dual-rate burst-mode receiver for an XGS-PON OLT consisting of an avalanche photodiode (APD), a burst-mode pre-amplifier IC and a burst-mode limiting amplifier IC. A commercial-available mass-produced 10 GHzclass APD was applied for the dual-rate burst-mode receiver. The preamplifier and limiting amplifier ICs were fabricated in 0.13 μm SiGe BiCMOS. The receiver is split into two blocks to realise the following features: fast settling time, wide dynamic range, and tolerance of long CID sequences. The first preamplifier stage incorporates the AGC and ATC circuits to achieve a wide dynamic range. The second stage has a discharge circuit in the limiting amplifier to achieve a fast settling time and tolerance of long CID sequences.
The burst-mode pre-amplifier can be divided into two main blocks. The first block is a trans-impedance amplifier (TIA) whose gain is set by the peak-detecting AGC circuit. The second block is a single-ended differential converter for which the threshold level is generated by the fast/slow switching ATC circuit. To set both the AGC and ATC circuits to the fast mode, a reset signal is an input from outside the receiver chipset. When the reset signal is input, the peak-detecting AGC sets the gain of the TIA within the short preamble time, and holds its gain after detecting the peak of the signal [6]. It is noteworthy that the TIA gain is set by an external rate select signal for receiver sensitivities appropriate for signals of both bit rates, but that a common AGC circuit is used to minimise the size of the TIA circuit. At the same time, the fast/slow switching ATC circuit is set to the fast mode for rapid receiver settling. After a period which is slightly longer than the settling time of the TIA gain, the ATC circuit changes its transient response time from fast to slow. The same fast and slow transient response times are used for both bit rates to keep the circuit as simple as possible.
AC coupling between the preamplifier and limiting amplifier ICs is preferred because the common-mode voltages at the output of the preamplifier and the input of the limiting amplifier are different for the best performance of each IC. However, an AC coupling also slows the transient response and/or causes low CID tolerance. To avoid this, the fast discharge circuit discharges the AC coupling capacitor quickly when the reset signal is input. After that, the transient response time of the AC coupling is set to high by switching the terminating resistor following the AC coupling capacitor in the fast discharge circuit from low to high. However, 10 Gb/s and 2.5 Gb/s signals are not usually sent to the limiting amplifier when the high terminating resistor only is used at the input because there is then poor impedance matching between the preamplifier and the limiting amplifier. To get an impedance match, 50 ohm resistors are combined with capacitors at the input of the limiting amplifier, the differential output impedance of the preamplifier being 100 ohms. Both a sufficiently low cut-off frequency and impedance matching of the 10 Gb/s signals could be obtained by adding suitably small capacitors to the 50 ohm resistors. Although we placed the AC coupling capacitors and the sets of 50 ohm terminating resistors and capacitors outside the limiting amplifier ICs to obtain the best circuit parameters during our evaluation, these components could be integrated in the limiting amplifier to minimise the size of the burst-mode receiver. The switching time of the discharge circuit is set by the signal detect The bandwidth of the limiting amplifier is switched by the external rate select signal to suit either the 10 Gb/s or 2.5 Gb/s signal rate to cut off any noise at a higher frequency than the signal. It is noted that the bandwidth of the limiting amplifier is set by changing only the parameters of the passive filter in the input stage. As a result, its power consumption is the same as a single-rate limiting amplifier.
Experimental results: We demonstrated the performance of this dualrate burst-mode receiver by connecting it to XG-PON and XGS-PON ONU transmitters. The extinction ratio is 7.3 dB for the 9.95 Gb/s transmitter and 7.9 dB for 2.49 Gb/s. One ONU sent 'loud'packets and the other ONU sent 'soft' packets to evaluate the burst response and bit error ratio (BER) performance of our receiver. Figure 2 shows the uplink burst composition for evaluating our ICs' performance. The soft packet optical signal was 2 μs long and consisted of a 64.3 ns preamble with a repetitive '01 pattern and a payload with a PRBS 2 31 -1 pattern to evaluate the 9.95 Gb/s performance. We used a PRBS 2 23 -1 pattern to evaluate the 2.49 Gb/s performance. For each data rate, the payload also included both 72-bit '1 and 72-bit '0 CIDs. When evaluating the 9.95 Gb/s burst response, the loud packets are 2.49 Gb/s ones with a PRBS2 23 -1 payload at -7 dBm optical power, described as the maximum level of N1 in ITU-T G.987.2. Conversely, when evaluating the 2.49Gb/s burst performance, the loud packets consist of a 9.95 Gb/s PRBS2 31 -1 payload at -9 dBm optical power, described as the maximum level of E1 in ITU-T G.9807.1 Amendment 1. After a loud packet, we set a 51.4 ns interval to the next soft packet as a guard time. This value is a strict requirement of ITU-T G.9807.1 Amendment 1. Figure 3 and Figure 4 show the respective measured burst-mode output waveforms of the limiting amplifier when receiving at 9.95 Gb/s and 2.49 Gb/s. In each figure, the left-hand set of images shows the wave- forms at the head of a soft packet, and the right-hand set shows the eye diagrams of the receiver. In Figure 3, the waveforms in the upper row are at -31 dBm soft packet received optical power, the lower limit of sensitivity, the middle row is at -23 dBm, the error-free power level, and the bottom row is at -5 dBm, the maximum soft packet overload power. As shown in the left-hand set of images, our receiver achieves fast settling from the maximum loud packet to any soft packet power level within the 64.3 ns preamble period. The evaluation packets include 72 CIDs, and the right-hand column shows that our receiver receives such packets stably at each power level. Figure 4 similarly shows the performance at 2.49 Gb/s, at -36 dBm as the lower limit of sensitivity, at -29 dBm as the error-free power level, and at -7 dBm as the maximum overload power. As when receiving 9.95 Gb/s packets, our receiver also has a good settling performance at 2.49 Gb/s. Figure 5 shows the measured BER characteristics of our dual-rate receiver. We used the same packet configuration as we used for evaluating the burst response: see Figure 2. A lower limit of receiver sensitivity of -31.2 dBm was obtained for 9.95 Gb/s, and a dynamic range of 26.2 dB was also achieved. This characteristic satisfies the minimum receiver sensitivity requirement of ITU-T Rec. G.9807.1 E1 and the overload requirement of ITU-T Rec. G.9807.1 N1. In addition, a lower limit of receiver sensitivity of -36.5 dBm was obtained for 2.49 Gb/s, and a dynamic range of 29.5 dB was also achieved. This characteristic satisfies the minimum receiver sensitivity requirement of ITU-T Rec. G.987.2 E2 and the overload requirement of ITU-T Rec. G.987.2 N1. Table 1 summarises the performance characteristics. The minimum receiver sensitivities are -30.6 dBm (converted for an extinction ratio of 6.0 dB) at 9.95 Gb/s, and -36.6 dBm (converted for an extinction ratio of 8.2 dB) at 2.49 Gb/s with a short settling time of 64.3 ns. Our receiver achieves good characteristics at both bit rates. CID tolerance (bit) 72 n/a n/a 72 a Converted for extinction ratios of 6.0 dB at 9.95 Gb/s and 8.2 dB at 2.49 Gb/s b These sensitivities are the values read from the figure assuming that the APD conversion efficiency is 8 A/W. c This research was for 10G-EPON systems. Therefore the bitrates and the settling time specifcation are very different from [2] and this work.

Fig 6 Minimum receiver sensitivity plotted against preamble length
We also measured the minimum receiver sensitivities for both 9.95 Gb/s and 2.49 Gb/s signals when the length of the preamble changes. The other parameters are the same as for the BER measurement. Figure 6 shows the measured minimum receiver sensitivity plotted against the preamble length. As can be seen, the minimum receiver sensitivities at 9.95 Gb/s and 2.49 Gb/s were -31.3 dBm and -36.6 dBm, respectively, when the preamble length was set to 1000 ns, which are almost the same as the sensitivities for the preamble length of 64.3 ns. This means that our burst-mode receiver can achieve the same receiver sensitivity whatever the preamble length is set to in the ITU-T Recommendations.
In addition, we measured the minimum receiver sensitivities for both 9.95 Gb/s and 2.49 Gb/s signals when the CID length changes. Figure 7 shows the measured minimum receiver sensitivity plotted against the number of CID bits. As shown in Figure 7, if a packet includes a constant signal-level stretch as long as 768 bits of CID at 9.95 Gb/s, our receiver will satisfy the minimum receiver sensitivity requirement of ITU-T Rec. 9807.1 Amendment1 E1, and likewise, with 256 bits of CID at 2.49 Gb/s, our receiver will also satisfy the requirement of ITU-T Rec. 987.2 E1.

Conclusions:
We developed receiver ICs with fast-acting AGC and ATC, an alternate-pattern signal-detection circuit and a rapid switching discharge block, and achieved a sensitivity -31.2 dBm and a dynamic range of over 26 dB for 9.95 Gb/s, and a sensitivity of -36.5 dBm and a dynamic range of over 29 dB for 2.49 Gb/s, in both cases with packets with a 64.3 ns preamble and a payload including 72 bits of CID. Also satisfied were ITU-T Rec. G.9807.1 E1 and G.987.2 E1, even when a packet includes such long stretches of constant signal-level as 768 bits of CID at 9.95 Gb/s and 256 bits of CID at 2.49 Gb/s.