Fault-tolerant multi-node coupling triple mode redundancy voltage controlled oscillator for reducing soft error in clock and data recovery

A voltage controlled oscillator (VCO) applied to phase-locked loop with multi-node coupling triple mode redundancy is proposed in this Letter. The proposed VCO consists of three independent operating VCOs. These VCOs are coupled through a metal oxide metal capacitor to synchronise the output of the three independent VCOs. The pro- posed VCO does not introduce loop delay, and the frequency and phase noise do not decline.

Introduction: In nuclear and space communication applications, highspeed serial data communication links are essential. The data transmission and clock recovery from a serial data stream are achieved by using a phase-locked loop (PLL).
Voltage controlled oscillators (VCOs) have been verified as the dominant source of single-event transient (SET) in PLLs [1,2]. Fig. 1 shows the SET occurrence in the VCO of the unhardened clock and data recovery (CDR). To evaluate the effect of particles on the PLL, we simulate the SET current by using technology computer-aided design and then establish the corresponding spice current. The SET current pulse that results from a particle strike is then described as a pulse width linear function. When the SET happens in different nodes of the VCO, the PLL is affected.  Fig. 2 shows, the waveform in the blue block shows that output frequency modulation, amplitude modulation, and a temporary loss of oscillation occur when there is an ion strike in the VCO. Output frequency modulation and amplitude modulation may lead to a large phase error in the phase interpolator (PI), finally making the CDR sample the error data. Loss of oscillation may lead the CDR to become out of lock, which needs more time to recover the locking state. The bit error rate (BER) may greatly decrease if the CDR is out of lock.
Multiphase and high-frequency VCOs are essential for SerDes. However, the redundancy and voting techniques used in [3] to radiation hardened the VCO at the expense of slowing down the operating frequency. Evenly spaced multiphase outputs are also impossible for that structure.
Circuit design: As shown in Fig. 1, a traditional unhardened VCO is composed of bias circuits and a ring oscillator. The ring oscillator is made up of four of the same differential delay units. Differential buffers are used to improve the output drive and balance the loads.
The bias circuits provide voltage for the delay cells and buffers. The cell circuit, which consists of the NM4 and NM5 for the differential input transistors, PM3, PM4, PM5, PM6 (the active load), PM7, and PM8, both of transistors make the positive feed to accelerate the operating frequency of the VCO.  3 shows the proposed VCO circuit. Compared with the unhardened VCO, a multi-node coupling triple-mode redundancy VCO (M-VCO) implements three self-running VCOs (identical to the unhardened VCO in Fig. 1) in parallel, each with its own feedback path. Since any minor variations in the device or parasitic elements result in unsynchronised operations and increased jitter in the three independent VCOs. The inner nodes of the M-VCO are cross-coupled with metal oxide metal (MOM) capacitors to synchronise the output of the three independent VCOs to avoid these problems.  Compared with traditional VCOs, the proposed M-VCO forces three VCO phases to follow each other due to the effect of capacitance. This structure allows for the avoidance of the effect of layout design asymmetry and process deviation on the three VCO outputs with different frequencies and the initial phase of vibration. As Fig. 4 shows, the phase jitter of the M-VCOs is confined in a small range.
The sinusoidal output waveform of the VCO is converted into fullswing square wave by the CML2CMOS module, and the square wave signal generated by the same phase is input into the majority voter. As shown in Fig. 3, BN00, BN01, and BN02 are input into the voter. The function of the voter is to filter out different signals when one of the three inputs is different from the other two.  T1   T2   T3   T1   T2   T3   T1 T2 T3  T1 T2 T3   jitter1  jitter0   jitter2 jitter3 ΔΦ Fig. 4 Operating principles of proposed VCOs As shown in Fig. 1, once the red line lags behind the black line around ΔΦ e , this leads to increasing BER. ΔΦ e is the phase between the red solid line and the black solid line (the line at the rising edge of normal CLK). To maintain the system when SET occurs, the jitter plus the phase drift cannot exceed ΔΦ c , the phase between the green solid line and the black solid line (the line at the rising edge of normal CLK).
As Fig. 5 shows, when SET occurs, the proposed VCO has the following response: when the SET current hits the bias circuits or buffer in VCO0, a large frequency difference results, but it can be filtered by the voter. The M-VCO only introduces slight frequency modulation. When the SET current hits the CELL in the ring in VCO0, VCO0 has a temporary loss of oscillation. By using the TMR strategy, because VCO1 and VCO2 still maintain oscillation, the amplitude modulation and a temporary loss of oscillation are avoided in the M-VCO. Only a small phase error is introduced by PI. The MOM capacitor should be small in order to reduce the impact of the normal operating VCO and the VCO hit by an ion strike. BER maintains stable as usual when SET occurs.  There are several advantages associated with this hardening method. First, the structure of unhardened VCO is unchanged. Therefore, the M-VCO can provide evenly spaced multiphase outputs. Secondly, as shown in Fig. 6, the M-VCO does not attenuate the frequency and phase noise. The disadvantages are the area penalty and large power consumption. The simulation tuning range of the proposed VCO is from 0.3 to 6.25 GHz. The performance of the proposed VCO is summarised and compared to other published CMOS VCOs in Table 1. Conclusion: By using three independent operating VCOs coupled using a MOM capacitor, the proposed M-VCO can protect the PLL from losing a lock state when an SET current occurs in the sensitive node of the VCO. This structure has very good phase noise performance compared to others.