Efficient design of 15:4 counter using a novel 5:3 counter for high ‐ speed multiplication

This paper proposes an efficient approach to design high ‐ speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re ‐ ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16 ‐ bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.


| INTRODUCTION
Multiplier circuit is a data-path element of the processor and specialised hardware circuits that are used for signal/image processing applications. The high-speed multiplier design is still a need of the hour. One can design a high-speed multiplier by reducing the delay of the partial product reduction stage. Many techniques are available in the literature for the reduction of partial products. Among all, the compressor and counterbased reduction techniques are popular ones [1,2]. The basic difference between compressor and counter depends on the carry and Cout weights [1,2]. For example, a 4:2 compressor will be designed using two full adders, as shown in Figure 1, with the following equations.
The 5:3 counter is designed using two full adders and one half adder, as shown in Figure 2. The 5:3 counter will have the equation as follows: From the compressor Equation (1), the Cout and Carry will have the same weights (2 1 ), but from the counter Equation (2), the Cout and Carry will have different weights, that is, 2 1 and 2 0 , respectively. The compressor and counter functionality is the same (both counts the number of 1's present in the input). It produces the results as binary in different weights. For example, consider X0 ¼ 1, X1 ¼ 1, X2 ¼ 1, X3 ¼ 1, and Cin ¼ 1 then the 4:2 compressor produces the result as (Cout, Carry and Sum) ¼ 111 (value is five based on Equation (1)) and the 5:3 counter will produce the result as (Cout, Carry and Sum) ¼ 101 (value is five based on the Equation (2)). The rest of the input combinations and their corresponding outputs for the compressor and counter is shown in truth Tables 1 and 2. This paper proposes a novel 5:3 counter and the proposed design is efficient in terms of area, power and delay. The The designed counters are used in the partial product reduction stage of the multiplier. The energy per operation of the proposed multiplier is less than the existing one from the literature.
The rest of the paper is organised as follows. Section 2 presents a detailed literature review of counter-based multipliers. Section 3 gives the details of the proposed 5:3 and 15:4 counters and multiplier design methodology. Section 4 discusses implementation details and results and followed by the Section 5 Conclusion.

| LITERATURE REVIEW
The basic 5:3 counter is designed by two full adders and one half adder as shown in the Figure 2. Each full adder is designed by two XOR gates and a majority circuit [3]. In total, the 5:3 counter is designed using five XOR gates, five AND gates, and two OR gates. Since the basic 5:3 counter uses five XOR gates and it consumes more power and delay. Chowdhury et al. [4] has proposed a 5:3 counter with a lesser delay than the basic 5:3 counter. The authors have replaced the full adder design using two XOR gates and one multiplexer as shown in the Figure 4. The overall 5:3 counter design will have five XOR gates and two multiplexers, and one AND gate. The authors have used their proposed 5:3 counter to design 15:4 counter [4]. Authors [5] have proposed a 15:4 counter using a 5:3 counter. The 5:3 counter design of Marimuthu et al. [5] has shown in the Figure 5. The authors have focused on reducing the delay using 4:1 multiplexer. Asif and Kong [6] have proposed a 4:3 counter, 5:3 counter and 7:3 counter using propagation and generation blocks. The existing three types of counters are used in the 16-bit Wallace tree multiplier. Few more designs from the literature are available in Hsiao et al. [7] and its circuit diagram is shown in Figure 6.
The authors have designed a 5:2 compressor using a 4:2 compressor and 3:2 counter. The proposed 5:2 compressor is used in designing multiplier, and thereby they have designed 16 � 16 MAC [8]. The worst path of this 5:2 compressor will have four XOR gates. 7:3 parallel counter is designed to implement the faster 16 � 16 multiplier [9], and the worst path of this counter has three XOR gates and three NAND gates. Authors [10] used BiCMOS technology and implemented the basic building blocks of the multiplier, thereby designing arithmetic circuits. A new unit adder and 4:2 compressor were designed to enhance the performance of the multiplier [11]. Pass transistorbased multiplexer is used to design a 4:2 compressor and adder as a fundamental building block of the 54 � 54 bit multiplier [12]. The design of a parallel counter ranging from 3:2 to 31:5 is demonstrated by Jones and Swartzlander [13]. Authors proposed on the fly multi-speculative multiplier, which uses the partial carry-save tree and booth encoding to reduce the depth of the multiplier structure [14] and radix-8 based multiplier designed by Del Barrio et al. [15]. using the input re-ordering circuit to reduce the circuit complexity. As the proposed counter uses primitive gates, XOR gate, and one 2:1 multiplexer. This paper also proposes a 16-bit multiplier design using proposed 15:4 and 5:3 counters. The circuit complexity of the proposed design is lesser than the existing counters based multiplier design. As a result, the power delay product reduces.

| PROPOSED HIGH-SPEED MULTIPLIER DESIGN USING PROPOSED COUNTERS
This Section proposes a high-speed multiplier design using the proposed novel 5:3 and 15:4 counters. The rest of this Section is organised into three parts. Part A presents the proposed novel 5:3 counter design methodology, followed by part B illustrate the design of 15:4 counter using the proposed 5:3 counter, and finally, part C explains the design methodology of high-speed multiplier design using the proposed counters.

| Proposed novel 5:3 counter
The basic operation of the 5:3 counter is to count the number of 1's present in the input combinations, and the resultant output will vary from value 0 to 5, as shown in the truth Table 2. In truth Table 2, the value column represents the number of 1's present in the input combination. The value 1 as output has occurred for five different input combinations in Table 2. All these five input combinations can be reduced to fewer combinations if one can re-order the inputs. For example, value 1 occurs for different input combinations such as 00001, 00010, 00100, 01000 and 10000. These five combinations are applied to the input re-ordering circuit to produce the output as three combinations 10000, 00001 and 00100. On the sameline rest of the combinations can also be reduced using the input re-ordering circuit. The basic intuition is to reduce the number of output combinations from the input using the input re-ordering circuit, as shown in Figure 7 for the truth Table 2.
The input re-ordering circuit will reduce the input 32 combinations into 18 combinations, as shown in Tables 3 and 4. The Table 4 shows the reduced 18 combinations and the number of times each combination has occurred. The input re-ordering circuit's output can be expressed in the following Boolean This Section proposed a novel 5:3 counter, as shown in Figure 8. The proposed 5:3 counter truth table is shown in Table 4. The Boolean expressions for Cout, Carry and Sum is as follows and its circuit diagram is shown in Figure 9. Carry where The proposed 5:3 counter is shown in Figure 8. The existing design, as shown in Figure 4, will take the three XOR gate delay to compute the Sum, and the proposed design requires only two XOR gate and AND-OR-Inverter gate. The proposed 5:3 counter is efficient in terms of power and delay compared with the literature's existing designs, and its detailed gate-level analysis presented in Table 5.

| Proposed novel 15:4 counter design
This Section proposed a novel 15:4 counter [5] design using the proposed 5:3 counter of the above Section and optimised the parallel adder of the final stage. The proposed 15:4 counter consists of five numbers of full adders connected in parallel in stage one. In stage two, it uses proposed 5:3 counters, and followed by stage three uses 4-bit parallel adder. In stage one, all the 15 inputs are connected to five full adders. As a result, full adders output 10 outputs (five Carrys and five Sums).

F I G U R E 6
The existing 5:3 counter by Asif and Kong [6] F I G U R E 7 Input re-ordering circuit L. ET AL.

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These 10 outputs are fed to all the carrys to one 5:3 counter, and all the sums are fed to another 5:3 counter. As a result, it produces three outputs (Cout, Carry, Sum) from each 5:3 counter. These six outputs are added using a parallel adder.

| Proposed high-speed multiplier design
The high-speed multiplier design uses the proposed 15:4 counter and 5:3 counters. The Figure 10 shown 16 � 16 multiplier design

| RESULTS AND DISCUSSIONS
Each design has been modelled using Verilog HDL, simulated using Cadence Inclusive Unified Simulator v6.1. All the designs are implemented using the TSMC 45 nm technology library (tcbn45gsbwpbc0988 ccs:lib) using the Cadence Genus electronics design automation tool. The derived net-list was then passed to the Cadence tool for floor planning and routing. All