Thermal synergies in 50 nanometer CMOS and below

F. S. Shoucair, 981 Tulare Ave, Berkeley, CA 94707, USA. Email: zeropi@copper.net Abstract An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<�100 ppm/°C) and currents (<�400 ppm/°C) in standard complementary metal oxide semiconductor (CMOS) processes over wide temperature spans (–55°C to þ163°C). The method involves combining devices with the same polarity (e.g. n‐channel MOSFETs in p‐well processes and vice versa) in a judicious manner suggested by theory, which side‐steps the need for disparate elements such as resistors, diodes, and bipolar transistors, whose thermal variations are more difficult to model and offset mutually; the more so, the wider the temperature range. The close agreement between analysis and simulations (BSIM4) is illustrated by representative circuit design examples embodying the proposed principles. The concepts set forth offer advantages as generally accrue from design simplification and reduced circuit complexity; they are scalable as industrial silicon CMOS processes – which are not optimised for extended thermal operation – evolve below 50 nm, and suitable to other technologies which find applications in the automotive, aviation, aerospace, energy, and geophysical sensing sectors, among others, such as silicon carbide, wherein MOSFETs can operate above 300°C.


| INTRODUCTION
Commercial complementary metal oxide semiconductor (CMOS) processes continue to evolve in the direction of miniaturization, the primary purpose of which is to increase the density and speed of integrated circuits, digital and analogue, for telecommunications and related applications. Integrated electronics required in a number of other applications must perform reliably under harsher circumstances, often including wide thermal cycling and/or radiation, such as those prevailing in automotive and aircraft engines, in the aerospace realm, in power plant monitoring and control, and in environmental sensing under growing extremes of climate and exploration conditions. For such otherwise demanding applications, design simplification and overall savings may be achieved, where costly custom and/or non-standard processes may be replaced by their standard, junction-isolated, CMOS counterparts.
Integrated references, or stable voltages and currents, which have been critical building blocks of data converters and analogue circuits since their inception in the 1960s, now exist in many guises and degrees of complexity, which meet or exceed the stringent measures of temperature coefficients (TC) below �100 ppm/°C (�100 parts per million per degree Centigrade, or �0.01%/°C) and power supply rejection (PSR) of 60 dB or higher, even over the military range [-55°C,þ125°C]. Their underlying principles, as well as those of other references, generally entail the arrangement of two (or more) circuit elements, the variations of whose voltages and/or currents oppose each other and, ideally, cancel over a specified temperature range. While this general concept is straightforward in principle, its practical implementation is critically dependent on the behaviour of circuit elements available in a given fabrication process.
Bandgap references (BGR), CMOS compatible or otherwise, are prized for many applications wherein the highest possible TC and PSR performances are required, although their bipolar junction transistor (BJT) currents increase exponentially with temperature. The well-known metal oxide semiconductor field effect transistor (MOSFET) "V TH -R" references, which operate at low currents, are likewise susceptible to the deleterious effects of junction leakage currents and require calibration in conjunction with resistive layers, as do their BGR counterparts, in order to remain within their design specifications despite short-and long-term temperature variations and drifts. Further discussion on leakage currents can be found in Section 6.
While the thermal current-voltage characteristics of MOS-FETs are intermediate in complexity between those of passive resistors (linear) and BJTs' (exponential), they also exhibit the unique advantageous feature of built-in, opposing, trends among their two dominant current-controlling parameters, namely the threshold voltage V TH (T), and the conducting channel's electron (or hole) carrier mobility µ (T). Insofar as integrated MOSFETs in modern standard CMOS processes continue to exhibit these long-standing phenomena, as well as a generally lower parameter drift than their forerunners, the main objectives of the sequel are to (a) assess the extent to which they may achieve stable voltages and currents without the compensating thermal effects of BJTs, resistors, and elements other than MOSFETs, and (b) determine the performance trade-offs and limitations thereby ensuing over the thermal range for which standard CMOS processes are specified and beyond, especially where wide thermal functionality is of foremost concern.
Towards these objectives, an analysis of the dominant thermal effects on the characteristics of integrated MOSFETs in strong inversion reveals two regions of operation, in each of their triode and saturation regimes, which offer advantages of voltage and current stabilization with respect to temperature variations, especially so when their properties are combined. While these regions have generally been exploited separately towards the aforementioned objectives, advantageous synergies between these are elaborated which result from judicious combinations thereof.
After describing, analysing, and quantifying the relevant individual effects in the triode and saturation regions of MOSFETs (Sections 3 and 4), we assess the thermal stability of the voltages and currents resulting from their interaction in pertinent circuit combinations, along with the effects of threshold voltage mismatches (Section 5). Considerations pertaining to leakage currents, to PSR and noise, and to process and supply voltage scaling are discussed in Sections 6-8, respectively.
Our results indicate an overarching trade-off between power consumption and biasing stability, whereby the latter is critical to the operation of analogue circuits over wide thermal spans. The range [-55°C, þ163°C] ¼ [218 K, 436 K] is used throughout because it corresponds to a 2:1 span for T (°K), whose convenience will be justified in Section 5.2.

| MOSFET MODELS
The physical and mathematical descriptions to follow pertain to long n-channel MOSFETs such as encountered in standard CMOS processes, and are equally valid for their complementary (p-channel) devices with appropriate polarity allowances. The temperature range of their suitability to a given process is that over which leakage currents may be properly neglected relatively to channel currents for the particular application at hand. Although for typical silicon processes and devices an upper temperature near to þ175°C is generally a reasonable estimate, absent disconfirming evidence, considerations pertaining to leakage currents and to downscaling effects are discussed in Sections 6 and 8. The body and drain output conductance effects are not considered explicitly since they introduce no additional qualitative effects for our purposes; these restrictions promote the modelling of the essential, salient, thermal effects with a minimum of analytical complexity, without the sacrifice of accuracy or generality. While the parameters used below are typical of contemporary CMOS processes with minimum channel lengths near to 50 nm (Figure 1a,b), the ongoing potential of their scaled counterparts for analogue circuits has been reported recently for a 28-nm industrial bulk CMOS process [14].

| DESCRIPTION OF THE MOSFET's THERMAL CHARACTERISTICS
The two dominant temperature-dependent parameters are the threshold voltage V TH (T) ¼ p o T þ q o and the channel mobility µ(T) ≈ µ o (T/T o ) -m , T being the absolute temperature in degrees Kelvin, p o ¼ (dV TH /dT) and q o are known (measured) constants for a given process, typical values for which are -0.5 mV/K and 450 mV, respectively, m ≈ 3/2, and V TH (300 K) ≈ 300 mV at V SB ¼ 0. A very nearly linear dependence of V TH on temperature is expected on theoretical grounds and has been observed across many process generations, as has a power law for µ(T) in silicon inversion layers, where µ o is the mobility at reference temperature T o . While the precise value of m in the mobility's power exponent does not alter the substance of our treatment, 1 the validity of the foregoing simple relationships appears to be sustained by the near-roomtemperature characteristics of thin-oxide MOSFETs in the aforementioned 28-nm process [14], as was the case for preceding generations of processes in the range of 180-65 nm.
The drain current characteristics in Figure 1a,b appear to suggest the existence of two bias gate-source voltages, V GS * (sat) and V GS *(triode), respectively, at which |(dI D /dT)| ≈ 0, especially when the current is displayed over many orders of magnitude, or on a logarithmic axis (see Figure 1 in [14], for example). On a sufficiently expanded scale, however, one observes that they merely intersect pairwise in a region of V GS spanning tens of millivolts, while not all intersecting at a single, sharply defined, point. Less obvious in Figure 1a,b, even as displayed on expanded linear axes, is that there exists a gate voltage (V GSq ¼ q o ) at which I D varies as √T in the saturation region (I Dq (sat)(T)), and as (1/√T) in the triode region (I Dq (triode)(T)) at fixed drain-source voltage. The analysis in Section 4 confirms that these effects are predicted by standard models, appearances notwithstanding. Figure 1c abstracts the relative locations of V GS *(sat), V GSq ¼ q o , and V GS *(triode), along with the corresponding currents for a typical device in each region of operation, and is intended to guide the reader's eye towards the bias regions of interest in Figure 1a,b. Since these three distinct voltages are essentially fixed (by V TH ) for a given process, they may be used as built-in reference potentials leading to simple, MOSFETonly, circuit arrangements achieving zero-voltage TC nominally and minimum-current TC simultaneously, as illustrated in Section 5. Moreover, as it will be established (see Equation (15)) that q o is the arithmetic mean value of V GS *(sat) and V GS *(triode), Figure 1a,b may serve to provide an independent estimate of q o for a given device, which should be consistent with that obtained from V TH (T ) data for the same device in a given process.
The main thrust of this work is aimed at highlighting valuable advantages derived from judicious combinations of the properties of the aforementioned, distinct, bias regions, namely the features of the regions where the saturation and triode |(dI D / dT )| are at their minima, and those prevailing at Whereas the former have generally been favoured in the literature, the latter bias region was chosen by Blauschild et al. [15], who demonstrated a MOSFET-only voltage reference in an enhancement/depletion n channel metal oxide semiconductor process, wherein they biased MOSFETs in saturation at V GSq ¼ q o as defined above, where I Dq (sat)(T ) varies as √T. Their reference was developed from the difference between the threshold voltages of their enhancement and depletion devices, while these devices' aspect ratios were scaled in approximate proportion to their (different) mobility variations with temperature. They achieved excellent results over the range [-55°C, þ125°C] even with non-ideal geometries and delicate compromises with respect to device mismatches.
In the stages considered in Section 5, the dominant, consequential, mismatches and drifts pertain to identical devices, which is a further advantage to their relative simplicity and to their potential for providing low TC voltages and currents simultaneously.

| ANALYSIS OF THE MOSFET's THERMAL CHARACTERISTICS
The emphasis of the following analysis being on first-order effects, it is intended to guide hand calculations for computeraided design. Long-channel devices are assumed, whose terminal potentials are referenced to the source. Per conventional notation in this context, K(T) ¼ µ(T)C ox bears the same temperature dependence as does µ(T), C ox being the gate oxide F I G U R E 1 Typical n-channel MOSFET characteristics in a 50-nm CMOS process with S ¼ (W/L) ¼ 10 and V SB ¼ 0. Also. see Figure 1 in [14] for corresponding data of a 28-nm process. (a) Saturation region,  (25)); q o is the arithmetic mean of V GS *(sat) and V GS *(triode) (per Equation (15)). The percentages in Figure (c) indicate the maximum deviation, as evaluated in Section 4, of each current over [-55°C,þ163°C] relatively to its midrange value at þ54°C, when the corresponding gate voltage is kept constant SHOUCAIR -185 capacitance per unit area, and S ¼ (W/L) is the geometrical aspect ratio (width/length) of a transistor. As earlier stipulated, body and output conductance effects are neglected. Leakage currents are likewise justifiably neglected for the thermal span under consideration, as elaborated in Section 6.

| Saturation region conditions at
Putting (1), we have the equivalent expression: which reduces to Hence, when the MOSFET is biased at the fixed gate voltage V GSq ¼ q o in the saturation region, its current will vary as √T and, consequently, (dI Dq (sat)/dT ) ≠ 0. The current I Dq (sat)(T ) at V GSq ¼ q o is thus expected and indeed observed to vary by approximately �20% over [-55°C, þ163°C ], relatively to its mid-range value (at 54°C ¼ 327 K), as predicted by Equations (1) and (3), where it takes on the approximate value of 18 µA for an n-channel MOSFET of aspect ratio S ¼ 10 and V TH (54°C) ≈ 300 mV (see Figure 1a).

| Triode region conditions at
The last approximation, valid if V DS << V GS -V TH (T), will be assumed below. Proceeding as above, by putting (4), we have the equivalent expression: which reduces to: Hence, when the MOSFET is biased at the fixed gate voltage V GSq ¼ q o in the triode region, its current will vary as (1/√T ) at fixed drain-source voltage V DS and, consequently, (dI Dq (triode)/ dT ) ≠ 0. The current I Dq (triode)(T ) at V GSq ¼ q o is likewise expected and observed to vary by approximately �20% over [-55°C, þ163°C], relatively to its mid-range value (at 54°C ¼ 327K), as predicted by Equations (4) and (6), where it takes on the approximate value of 5 µA (at V DS ¼ 20 mV) for an nchannel MOSFET of aspect ratio S ¼ 10 and V TH (54°C) ≈ 300 mV (see Figure 1b).

| Saturation region conditions for minimum |(dI D /dT )|
Setting the derivative of Equation (1) hence to the equivalent requirement that which cannot be met by a fixed value of V GS as the temperature varies. As noted in [16], however, an analytical minimum for the variations of I D over a specified temperature range [T lo , T hi ] exists, which corresponds to the mean value V GS *(sat) of V GS as given by Equation (8) over [T lo , T hi ], or by putting (8): Putting Equation (9) into Equation (2) indicates that when the MOSFET is biased at this fixed gate-source voltage, its current is Evaluating this current at (10) is expanded in a Taylor series about T ¼ T o , these ratios are nearly accounted for by the second and thirdorder terms of the series. Hence the magnitude of I D *(sat)(T) is predicted to vary by no more than 3.3% at these extremes, consistently with typical observations over the same range [-55°C, þ163°C] relatively to its mid-range value of I D *(sat) (T o ) ≈ 32 µA at T o ¼ 54°C ¼ 327 K (Figure 1a), as compared to �20% noted in Section 4.1 for the bias condition is widely referred to as the saturation region's 'zero temperature coefficient' (ZTC) current in the literature, the nomenclature 'minimum temperature coefficient' (MTC) would be more accurate.

| Triode region conditions for minimum |(dI D /dT)|
Setting the derivative of Equation (4) which differs from Equation (8) only in the sign of the first term on the right-hand side and, likewise, cannot be met by a fixed value of V GS as temperature varies. The analytical minimum for the variations of I D over [T lo , T hi ] now occurs at where V GS *(triode) < q o since p o < 0. To this fixed gate voltage put into Equation (4), and at fixed V DS , corresponds the current is the arithmetic mean of the two foregoing values of V GS * at which the current variations are at their minima over [T lo ,T hi ], as indicated in Figure 1c. Since the magnitude of p o decreases with technological downscaling V GS *(sat) and V GS *(triode), as given by Equations (9) and (13), respectively, will tend to converge on their arithmetic mean value q o , which tracks V TH (T o ) approximately, hence with the advent of process downscaling. Consequently, the three gate bias voltages of interest V GSq ¼ q o , V GS *(sat), and V GS *(triode) will converge.

| APPLICATIONS OF THE RESULTS OF SECTION 4
For purposes of developing a stable voltage with respect to temperature, the results of Sections 4.1 and 4.2 are suggestive of a combination of MOSFETs biased at V GS ¼ q o in triode and in saturation. While such devices are combined in Figure 2, a low TC voltage is indeed achieved but current variations are not at a minimum, as anticipated from the foregoing analysis. The arrangement in Figure 3 augments the latter with a design technique suggested by the results of Sections 4.3 and 4.4, thereby readily achieving the desired minimum current variations simultaneously. The effects of mismatches between the threshold voltages of the same polarity devices are discussed in Section 5.3, wherein we find that those of the current mirror devices are dominant. Figure 2 is a special case of Figure 3, an analysis of which can be found in Appendix 1. These arrangements are intended to serve as illustrative examples of applications of the foregoing analytical results, insofar as they may confer advantageous latitude, for consideration by system designers otherwise aiming to meet multiple performance objectives constrained by complex trade-offs among such concerns as PSR, noise, and supply voltage reduction, to which Sections 7 and 8 refer.  (3) and (6), respectively, we have which will be constant if constant, which is satisfied since it is equivalent to (17). (18) is ≈ 12:8 mV: which agrees with the corresponding result indicated in Table 1, as does the value for bias current I Dq (sat)(54°C) ≈ 18µA determined uniquely by these choices. MX may be configured so as to allow post-fabrication trimming and/or other means of calibration or, simply, by leaving its gate open so that it may be driven by an external 'tuning' voltage. TA B L E 1 Summary of simulations (BSIM4) for Figure 2 50-nm CMOS process Maximum deviation of I D relatively to its midrange (54°C) value: ≈ �18% .V DS (triode) is proportional to absolute temperature, per Equation (17) 188 -

SHOUCAIR
The results summarized in Table 1 also confirm that V DS (triode)(T ) varies as T, per Equation (17), that the variations of the bias current are as √T per Equation (3), and that the magnitude of TC (V out ) is below 100 ppm/°C, absent higher order process-specific effects neglected in the analysis leading to (19). The latters' influence on TC(V out ), should they prove non-negligible post fabrication, may be minimized via MX as aforementioned.
While this stage differs conceptually from the well-known 'V TH -R' reference where I ≈ V TH /R is low when V GSref ≈ V TH hence R large, here MREF is biased well above V TH , hence the current not restricted to low values and R dispensed with entirely. The present method thus promotes stability over a wider temperature range than do traditional V TH -R references because all MOSFETs are biased at higher channel currents relatively to junction leakage currents, which is an important, concomitant, potential advantage permitting a trade-off between power consumption and thermal span.

| Augmented saturation and triode combination (Figure 3) ([dV out /dT ] ¼ 0 and |[dI D /dT ]| minimum)
Although the stability of the bias current is not the primary objective in a voltage reference, the foregoing analytical results can be further applied toward low TC current sources by minimizing |(dI D /dT )| concurrently with the condition (dV out /dT ) ¼ 0, as illustrated by the following design procedure. The circuit in Figure 3 improves upon the previous one by a form of 'triangulation'; it establishes its unique bias point at I D *(sat) ≈ 32 µA by virtue of an additional constraint imposed by two more, properly sized, transistors such that (dV out /dT ) ¼ 0 occurs at V GS *(sat) ≈ 500 mV instead of at q on ≈ 450 mV. The result is TC(V out ) ¼ 0 nominally and minimum |(dI D /dT )| simultaneously, while a voltage PTAT is produced with respect to the reference potential across M163.

| Design procedure
The following considerations pertain to Figure 3.
(a) The temperature span of interest being [T lo , This span encompasses most of the useful range of stateof-the-art bulk silicon CMOS processes and limits the detrimental effects of junction leakage currents and their associated conductances as well [16]. A suitable choice for SiC devices could be the 2:1 range [400 K, 800 K] ¼ [127°C, 527°C].
(b) If MREF1 and MREF2 are matched, nominally identical, devices, we have or, equivalently: (c) If (geometrically identical) MREF1 and M163 were operating at T lo and T hi . respectively, we would have for these devices: While all transistors operate at essentially the same temperature, a sufficiently accurate approximation to a device operating at T hi (here M163) may thus be created by shifting the characteristics of a reference device (MREF1) operating at T lo by ∆V TH as per Equation (22), and by scaling the resulting, shifted, curve per Given T hi ¼ þ163°C and T lo ¼ -55°C, we have (T hi / T lo ) ¼ 436K/218K ¼ 2, hence (S 163 /S ref ) ≈ 2 À 3/2 ≈ 0.35, as shown in Figure 4(a). As their common (on-chip) temperature varies, M163 will thereby behave nearly as if it were always operating at least 218°C above MREF1, such that the separation of the two curves in Figure 4a establishes a welldefined intersection point throughout the thermal range of interest. V GS *(triode), respectively, Equation (21) would take on the particular form: which is the difference between Equations (9) and (13), and is independent of q o .
(e) Hence, in order for (22) and (24) to hold simultaneously, we must have which is true independently of p o , if and only if T hi ¼ 2T lo , as indeed the case per item (a) above and, consequently, of V TH since it is also independent of q o , as indicated in Figure 1(c) above. A mismatch ∆p between the devices's p o parameters resulting in (T hi /T lo ) ¼ 2 (1 � ∆p/p o ), one may expect the nominal scaling between the devices, per (23), to be modified by a factor of order (1 � ∆p/p o ) À 3/2 , which remains near to unity for (∆p/p o ) << 0.1 corresponding to a conservative 10% relative mismatch between similar devices situated in close proximity.
(f) Since the current mirror imposes I DREF1 ¼ I D163 , MREF1 and M163 conduct equal currents while their characteristics differ in the same manner as if they were operating at different temperatures. Their common current must therefore be I D *(sat)(T) as given by (10), which corresponds to V GS *(sat) per Equation (9). Hence the current common to MREF1, M163, and MTRIODE is I D * (sat) ≈ 32 µA, which is the desired triple conjunction illustrated in Fig.4(b).
(g) The current mirror causing equal I D *(sat) and I D *(triode), we can estimate the ratio (S tr /S ref ) using Equations (10) and (14) directly or, equivalently, using Equations (8) and (12) without assuming V out constant a priori:  (17)). As this is the only step involving p o , which is readily determined from two values of V TH at two different temperatures, the design of this stage requires only this minimal amount of information.
(h) The foregoing design procedure is general since the devices' relative dimensions are in ratios whose values depend only on the mobility's temperature variations, per Equation (23), and on p o , per Equation (26). As such, it is expected to remain applicable with process downscaling for silicon and for other technologies (e.g. SiC) where FETs obey essentially similar models.
As V DS (triode) increases (Table 2), V out moves toward V GS *(sat) ≈ 500 mV where (dV out /dT ) ≈ 0 and, simultaneously, I D moves toward I D *(sat) ≈ 32 µA where |(dI D /dT )| F I G U R E 4 Arrangement for circuit of Figure 3. (a) V TH (T) shift equivalent per Equation (22), and aspect ratio scaling of M163, causing M163 to behave as if it were operating at 163°C when MREF1 is operating at -55°C, and subsequently as if it remains ≥ 218°C higher than MREF1 throughout the operating range, thereby establishing the desired bias current I D *(sat) ≈ 32 µA. (b) Triple current match for MREF1, MTRIODE, and M163. V out ≈ V GS *(sat) ≈ 500 mV is the fixed arithmetic mean of V GS (tr)(T ) and V GS163 (T ) at the bias current established by (a), that is, I ≈ I D *(sat) ≈ 32 µA. When the circuit is operating at T lo ¼ -55°C, V GS *(sat) is midway between V GS *(triode) and V GS163 . As the operating temperature increases, ∆V GS (triode)(T) ¼ -∆V GS163 (T). Vout ≈ V GS *(sat) remains stable because of KVL constraint (20) is minimum. The sign of TC(V out ), reversing near V DS (triode) ≈ 21 mV, indicates the expected null. The results summarized in Table 2 are shown graphically in Figure 5, whereby the value of V out , initially near q o ≈ 450 mV at low V DS (triode)(T) ≈ 15 mV, converges monotonically on V GS * (sat) ≈ q o þ ∆q o ≈ 500 mV near V DS (triode) ≈ 21 mV (Figure 5a), while the bias current converges on I D * (sat) ≈ 32µA (Figure 5b). The TC(V out ) and (∆I D /I D ) data for Figure 2 are indicated along the right-hand side, vertical, axes of Figure 5a,b, respectively, for ready comparison with those of Figure 3. Figure 6 shows the relative variations of the output voltage and current for Figures 2 and 3   in Figure 3 does I out achieve ≤ � 400 ppm/°C simultaneously, which is near the theoretical minimum evaluated in Section 4.3.

| Effects of threshold voltage mismatches
If, in Figure 3, ∆V THp is the threshold voltage mismatch between the p-channel mirror devices MP1 and MP2 (whose aspect ratios are assumed perfectly matched), and ∆V THn the corresponding quantity between MREF and MTRIODE then, to the extent that these differences may be regarded properly as incremental quantities, a small signal analysis yields: which indicates that the effects of V THp mismatches are dominant over those of V THn , as confirmed by simulation results (columns (a) and (b) in Table 1). For |(∆V THn /V THn )| ¼ |(∆V THp /V THp )| ¼ 0.05, corresponding to �5% mismatch, as assumed in Tables 1 and 2, we thus expect |∆V out | ≈ |∆V THp | ≈ 15 mV. This estimate compares favourably with the worst case results listed in Table 1, wherein ∆V out ≈ �19 mV at -55°C, �16 mV at 54°C , and �14 mV at 163°C, and with those in Table 2, wherein ∆V out ≈ �18 mV at 54°C. When the mismatch percentages are increased beyond approximately 10% however, their combined effects drive at least one device out of saturation under worst case conditions. Since V TH mismatch distributions in modern CMOS silicon processes can achieve standard deviations on the order of a few millivolts, one can reasonably expect | ∆V TH /V TH | ≈ 0.01 (�1% mismatch) or better between devices with sufficiently large gate area, such that the �5% mismatch condition posited in Tables 1 and 2 may be regarded as conservative, even allowing for geometrical aspect ratio mismatches of the same order (�1%) concurrently. While the V TH mismatch distributions' standard deviations can be expected to decrease with process downscaling [18], the effects of drifts of the values of p o and q o with temperature and distance (across wafer) are difficult to predict analytically absent detailed process/layout data, even for nominally identical devices, although they may be estimated by means of Monte Carlo analyses. The numerical results ( Table 1) also confirm that (∆I D /I D ) decreases with increasing temperature, as expected with increasing gate voltage overdrive |(V GS -V TH )|, as the magnitude of V TH decreases with V GS nearly constant.

| Prospects for low TC current sources
The � 4% current variations achieved by Figure 3 over the range [-55°C, þ163°C] correspond approximately to � 400 ppm/°C. If, in Figure 2, V DS (triode) is held constant, at its midrange value, for example, the TC of the sum of I Dq (sat)(T) and I Dq (triode)(T) halves, to �200ppm/°C approximately. Further improvement would be achieved by a circuit configuration producing the product of I Dq (sat)(T) and I Dq (triode) (T ), such that their respective √T and (1/√T) variations offset one another exactly. In a standard CMOS process where polysilicon resistors can be controlled to within �100 ppm/°C, which is typical, the linear variations of V GS163 (T) with T (see Appendix 1) may produce a low-TC (∼PTAT) current source I ¼ V GS163 (T)/R poly (T). Alternatively, if thin film resistors R tf with TC's on the order of �100 ppm/°C are available, then the output voltage produced by Figures 2 and 3 may be used directly (via buffering) to generate a low TC current I ¼ (V ref / R tf ). Moreover, as Toledo et al [19] report that the phenomena of Figure 1a,b may occur in the moderate inversion regime for certain processes, lower current/power stages may be achievable with our method, should it prove applicable to this region, to the extent allowed by the encroachment of leakage currents (see section 6 below).

| JUNCTION LEAKAGE CURRENT CONSIDERATIONS
The leakage currents of concern are those flowing across the side walls and bottoms of drain, source, and well junctions, and those (distributed) flowing from inverted channels into underlying wells. Figure 3 in [17] shows the details of the aforementioned leakage current components for an n-channel MOSFET in a p-well CMOS process. The magnitude of each component of these leakage currents is proportional to the area of the junction under consideration and to the temperature-dependent leakage current density for the junction which, in turn, is a function of the doping profile across the junction. The leakage current component flowing from the substrate into the well of a device enclosed therein is typically large, relatively to the former components, owing to the larger area of the enclosing well. It is thus good practice, under these circumstances, to allow the latter component to flow out of the well through a path other than the source of the enclosed MOSFET, that is to avoid a zero source to body potential, V SB ¼ 0, if possible. In the circuit of Figure 3, for example, this would entail tying the bodies of MREF2, MX and MTRIODE to ground if the attendant "body effects" can be tolerated. Any overall performance degradation resulting from these higher order effects will be process-parameter dependent, hence best assessed by process-specific simulations.

| Voltage dependence
Generation-recombination and diffusion currents are observed in standard CMOS processes below and above, respectively, a certain process-specific temperature, typically in the vicinity of 125°C. While the former exhibit well-known junction, reversebias, current density voltage variations, diffusion currents in MOSFETs also exhibit overall voltage variations, albeit through the effect of the modulation of the depletion region's volume of a junction, rather than of its current density. These effects give rise to additional small-signal conductances which degrade the gain-bandwidth performance of analogue stages, as modelled in Figure 15 of [16].

| Geometry dependence
The leakage current flowing across the reverse biased drain (or source) junction of a given MOSFET is proportional to its area, hence to W, the drawn channel width of the device. The ratio of leakage to channel (bias) current is thus proportional to W/(W/L), hence to L, which is minimized in devices with minimum channel lengths L and drain/source junction areas.

| Matching and temperature dependences
Extensive measurements of the leakage currents of n and p channel MOSFETs of identical geometries under identical reverse biasing conditions indicate that the matching between the drain/body leakage currents of these dissimilar devices (n þ p and p þ n junctions respectively) is of the order of �1% at 250°C and �10% at 300°C. These results may be reasonably regarded as worst case conditions for the matching between identical devices. Moreover, as diffusion leakage currents are typically dominant in this temperature range, the leakage current of a given junction at 163°C will be two to three orders of magnitude lower than at 250°C where its density is approximately 1 nA/µm 2 . Since the channel (bias) currents in Figures 2 and 3 are in the range of 15-30 µA, these currents can be expected to remain several orders of magnitude higher than the leakage currents associated with their junctions, even at 163°C, thereby justifying our neglect thereof at the outset of Section 4. In circuits where MOSFETs operate in the sub-threshold region (e.g. sub-µA currents) and in low current BGRs, the strong temperature variations of diffusion leakage currents near/above 125°C render some form of calibration and/or trimming imperative, as corroborated by multiple recent reports [2,4,6,10,12,14] (also see Table A1, Appendix 2). The implementation of the foregoing considerations in conjunction with those set forth in [16] has yielded key analogue CMOS building blocks (e.g. OPAMPs, switched capacitors) operated successfully up to at least 250°C.

| POWER SUPPLY REJECTION (PSR) AND NOISE CONSIDERATIONS
Power supply variations influence the foregoing circuits because of the channel length modulation effect, which was omitted in Equation (1) since it is weakly dependent on temperature [16]. The PSR at the output of Figure 3 may be improved by using longer channels for the mirror devices, and/or 'Wilson' or cascode mirrors in their stead, in the same manner as for topologically similar, basic 'V TH -R', circuits where it is limited to 30 dB approximately. The trade-offs entailed by such measures include headroom and dynamic range of output conductance values observed in standard processes. Further PSR improvements (60 dB or better) may be achieved by means of differential feedback schemes documented in the extant literature [15,20], and/or by combinations with voltage regulators [21]. The noise power, thermal or (1/f ), at the output of the (resistor-less) stages of Figures 2 and 3 is a function of process fabrication details and device dimensions; while its specifications are application dependent, it is expected to be no worse than in references with on-chip resistors, whose capacitive coupling to the substrate is a contributing factor.

| PROCESS AND POWER SUPPLY VOLTAGE SCALING
The values of the voltages developed by the foregoing stages are essentially derived from q o ¼ V TH (T o ) -p o T o . Since the magnitudes of both V TH (T o ) and p o decrease with increasing effective surface concentration and decreasing oxide thickness, the magnitude of q o has decreased with process downscaling in tandem with the value of the power supply voltage. Indeed the magnitude of the ratio |p o /q o | ≈ 1.3 � 10 À 3 (°K) À 1 has remained nearly constant across process generations spanning several decades, as have the relative variations ∆V TH (T)/ V TH (T o ) ¼ (p o ∆T)/V TH (T o ) ≈ �20% over [-55°C,þ163°C], with T o ¼ 54°C. Since q (V SB ) ≈ q o þ γ√V SB , γ being the weakly temperature dependent body effect coefficient [16], a measure of control over the value of q o is available, should it be required, by applying a non-zero source-body, reverse-bias, potential V SB to a given device. Moreover, as higher channel to junction leakage current ratios entail shorter channels, hence larger bias currents [16], trade-offs between power consumption, PSR, and upper operating thermal limit may ensue.  Other effects of process downscaling, such as gate-induced leakage currents (GIDL), drain-induced barrier lowering (DIBL), short channel and other thin oxide (<≈20 Å) induced high field effects in CMOS processes near to and below 50 nm are of ongoing concern for low power, high-speed, mixed analogue/digital systems. As such, their detailed characterization and modelling are key to their mitigation in a given process, the more so the lower the system's power allowance. As the stages considered in Figures 2 and 3 operate statically in strong inversion however, with approximately one third or less of the supply voltage across any given transistor's terminal pairs, junction leakage currents are expected therein to remain dominant over the aforementioned non-ideal effects, barring contrary evidence.

| CONCLUSION
We have presented an analysis of the dominant effects of temperature on the triode and saturation characteristics of silicon MOSFETs and shown how they may be combined to develop simple, MOSFET-only, low TC voltages and currents over [-55°C, þ163°C], provided non-minimum power consumption is tolerable. As the method relies essentially on devices of the same polarity, it dispenses with the delicate task of offsetting the thermal variations of disparate elements underlying most traditional references. The design principles thereby elicited offer the prospects of reduced circuit complexity and higher yields over wide temperature ranges, as the downscaling of standard commercial silicon CMOS processes (wherein extended temperature operation is not a primary objective) continues unabated, and as other technologies, such as SiC, mature. Analytical results and simulations are in uniform, quantitative, agreement.