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Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

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© IEE
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Reasons for current trade-off of test data volume for scan power dissipation in system-on-chip (SOC) testing is investigated. The conflict between the existing compression method and scan power minimisation technique is understood and it is proved that by using a new compression method this trade-off is unnecessary. When the new compression method is combined with scan latch reordering savings of up to 97% in peak power and 99% in average power, as well as compression ratios of up to 95% are possible.

Inspec keywords: automatic testing; integrated circuit testing; boundary scan testing; application specific integrated circuits; logic testing; data compression

Other keywords: peak power; scan latch reordering; system-on-chip testing; scan power dissipation; compression ratios; average power; test data volume; power minimisation technique; compression method

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Computer-aided logic design; Electronic engineering computing; Digital circuit design, modelling and testing; Automatic test systems

References

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      • Zorian, Y.: `A distributed BIST control scheme for complex VLSI devices', Proc. 11th IEEE VLSI Test Symp., 1993, Atlantic City, NJ, USA, p. 4–9.
    2. 2)
      • V. Dabholkar , S. Chakravarty , I. Pomeranz , S.M. Reddy . Techniques for minimizing power dissipation in scan and combinationalcircuits during test application. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 12 , 1325 - 1333
    3. 3)
      • N. Nicolici , B.M. Al-Hashimi , A.C. Williams . Minimisation of power dissipation during test applicationin full scan sequential circuits using primary input freezing. IEE Proc., Comput. Digit. Tech. , 5 , 313 - 322
    4. 4)
      • Chandra, A., Chakrabarty, K.: `Combining low-power scan testing and test datacompression for system-on-a-chip', Proc. IEEE/ACM Design Automation Conf. (DAC), 2001, New Orleans, USA, p. 166–169.
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