Anomalous enhancement of the sheet carrier density beyond the classic limit on a SrTiO3 surface

Electrostatic carrier accumulation on an insulating (100) surface of SrTiO3 by fabricating a field effect transistor with Parylene-C (6 nm)/HfO2 (20 nm) bilayer gate insulator has revealed a mystifying phenomenon: sheet carrier density is about 10 times as large as ( is the sheet capacitance of the gate insulator, VG is the gate voltage, and e is the elementary charge). The channel is so clean to exhibit small subthreshod swing of 170 mV/decade and large mobility of 11 cm2/Vs for of 1 × 1014 cm−2 at room temperature. Since does not depend on either VG nor time duration, beyond is solely ascribed to negative charge compressibility of the carriers, which was in general considered as due to exchange interactions among electrons in the small limit. However, the observed is too large to be naively understood by the framework. Alternative ideas are proposed in this work.


Supplementary Material
Anomalous enhancement of the sheet carrier density beyond the classic limit on a SrTiO 3 surface.

SAMPLE FABRICATION
Step and terrace (100) surfaces of 10 × 10 × 0.5 mm 3 insulating SrTiO 3 single crystals having a miscut angle of less than 0.03 • (Shinkosha Co., Ltd.) was used for the channel of our fieldeffect transistor (FET). First of all, the pristine surface of the SrTiO 3 single crystal was coated with a 3 nm Parylene-C layer using the Specialty Coating Systems LabCoater2 (model PDS2010). The Parylene-C film was formed according to the Gorham method: [1] the dimer was vaporised at 135 • C, decomposed into the monomer in the furnace heated to 690 • C, and then deposited at room temperature on the surface of SrTiO 3 placed in a deposition chamber evacuated to less than 5 mTorr. The thickness was checked briefly by the Filmetrics F20-UV film thickness monitor. Some samples were further examined by the transmission electron microscopy (TEM).
The Ultratech UTS-1700 stepper was used for the projection photolithography of the electrode pattern. To facilitate the electric contacts between the source/drain electrodes and the SrTiO 3 surface, Parylene-C film was selectively etched by ozone plasma under ultraviolet radiation. [2] We used 10 nm-thick Al or Ti metal for source/drain electrodes. The Al metal was evaporated by resistive heating of alumina crucible, while the Ti metal by electron beam heating (evaporation rates are 1 nm/s for Al and 0.1 nm/s for Ti). All the FET properties shown in the study do not depend on whether the source/drain electrodes may be Al or Ti. With the Shin-Etsu Chemical SIPR-9684-1.5 photoresist which forms an undercut structure, we could avoid the burr formation [3], even though all the source/drain electrodes were formed by the lift-off method.
After the electrode fabrication, a 3 nm-thick second layer of Parylene-C was deposited to cover the whole area. Then, a 20 nm-thick HfO 2 layer was deposited by Picosun SUNALE R-100B atomic layer deposition (ALD) system. Hf[N(CH 3 ) 2 ] 4 [tetrakis(dimethylamido)hafnium or TDMAH] was used as the hafnium metal precursor, which was preheated to 130 • C and was delivered to the reaction chamber, in which the sample was heated to 120 • C. Deionized water was used as the oxygen source for the 169-cycle ALD deposition. The thickness of HfO 2 film was 20 nm, which was estimated by the KLA-Tencor AlphaStep D-100 surface profiler, and some samples were more precisely examined by TEM. The gate electrodes were 5/500 nm Ti/Au (evaporation rate was 0.1 nm/s for Ti and 5 nm/s for Au) deposited by the e-beam evaporator.
The FET shown in Fig. 2c of the main text has the channel length L of either 2, 4, 9, or 20 µm, and the channel width W = 4L. The FET shown in Fig. 2d of the main text has L of either 20 or 50 µm, and W of either 4 or 10 µm, respectively. We also fabricated parallel plate capacitors of 100×100, 60×60, and 20×20 µm 2 square electrodes to evaluate the dielectric properties of the gate insulator.

CROSS SECTION IMAGING
TEM and STEM imaging was carried out to investigate the cross-section of the channel of the multi-terminal sample shown in Fig. 2d of the main text. JEOL JEM-2100F equipped with bright field (BF) detectors and energy dispersive x-ray analyser with an accelerating voltage of 200 kV was used for the measurements. Slices for the TEM/STEM observations were prepared using a focused ion beam (FIB) system, JEOL JEM-9310FIB, operating at 5 kV and 30 kV.
TEM image in Fig. 3a of the main text specifies that each layer of SrTiO 3 , Parylene-C, and HfO 2 is clearly distinguished. Total thickness of the bilaminar Parylene-C layer is around 6 nm. Although the devices were prepared by the standard lift-off method, scanning tunnelling electron microscope (STEM) near the edge of an Al sourcedrain electrode (Fig. 3b in the main text) showed that the edge has no such a burr to affect the device performance. [3] Furthermore, the energydispersive x-ray spectroscopy mappings for the Hf and Sr atoms ( Fig. 3b and Fig. 3c in the main text, respectively) indicate that the mixture of atoms in each layer was almost negligible, providing a premise for evaluating our bilayer gate insulator.

CUT-OFF GATE VOLTAGE AND SUBTHRESHOLD SWING
All the current-voltage (I SD -V G and I SD -V SD ) measurements were performed using the Agilent Technology E5287A high-resolution source/monitor unit modules equipped on the E5270B precision measurement mainframe. For the measurements in air at room temperature, we used the Karl Süss probe station.  . The solid lines represent the least-square fit to a model (log 10 ISD ∝ VG /S) with the subthreshold swing S. Cut-off gate voltage V O G below which ISD becomes smaller than the noise level of 100 fA is defined in this way. Due to the contribution of the contact resistance, S increases by decreasing the channel length L. By subtracting the contribution of the contact resistance, as discussed in the main text, we obtained S of 171 mV/decade, which are not much different from the rough estimation here. Inset shows ISD-VG plots for different VSD. When we decrease VSD, the subthreshold region, where logISD ∝ VG, becomes smaller.
For a sufficiently reliable comparison of the I SD -V G data of different devices, we defined an effective is the cut-off gate voltage below which I SD becomes smaller than the noise level of 100 fA. Open circles in Fig. S1 are I SD -V G plots for V SD = 1 V for four three-terminal FET devices with the channel length of L = 2, 4, 9, and 20 µm, and the channel width of W = 4L. Then, I SD -V G data were fitted by log 10

CAPACITANCE OF GATE INSULATOR
Agilent 4155C semiconductor parameter analyser was used for the quasi-static capacitance measurements, while a combination of the Solartron 1296 Dielectric Interface and SI 1260 impedance/gain-phase analyser was used for the ac capacitance measurements. We fabricated Ti(10 nm)/Parylene-C(3 nm)/-HfO 2 (20 nm)/Ti(5 nm)/Au(500 nm) parallel plate capacitors, and measured quasi-static capacitance C exp at a constant bias of 1 V. It should be noticed that Parylene-C for this capacitance measurement is half as thick as that in the bilayer gate insulator of our FET. As shown in Fig. S2, C exp is proportional to the area A, and is well fitted by C O +A C ins with the parasitic capacitance C O of 4.6 pF and the sheet capacitance C ins of 0.47 µF/cm 2 . This value of C ins = 0.47 µF/cm 2 does not depend on the applied voltage. For comparison, given that the dielectric constants of HfO 2 and Parylene-C are 20 and 3.15, respectively, a serial connection of HfO 2 (20 nm) and Parylene-C(3 nm) gives C ins of 0.45 µF/cm 2 : very good agreement with the experimental value.
Then, in order to decompose the contributions of HfO 2 and Parylene-C layers, we measured the frequency ω dependence of C exp for a capacitor with A = 100 × 100 µm 2 between 1 Hz and 1 MHz while applying a constant bias of 1 V. The results are simulated by the models shown in Fig. S3. C Hf and C P denote the sheet capacitance of HfO 2 and Parylene-C layers, respectively, as well as R Hf and R P do the resistance. Total impedance Z(ω), where ω ≡ 2πf and f is the frequency of the applied ac bias, is expressed as a sum of Z Hf (ω), Z P (ω), and Z ps (ω), which are the impedance of HfO 2 Parylene-C and parasitic contribution, respectively. That is, where C ps and R ps are the parasitic capacitance and resistance, as well as τ P ≡ R P C P , τ Hf ≡ R Hf C Hf , and τ ps ≡ R ps C ps . Total capacitance C(ω) of the double layer is given by the imaginary part of Z(ω) as where ψ P ≡ ln (ωτ P ) , ψ Hf ≡ ln (ω τ Hf ) , and ψ Hf ≡ ln (ωτ Hf ). It is worth noting here that each component of 1/C ϕ (ω) behaves as tanh(ψ ϕ ), where ϕ denotes either Hf, P or ps, as schematically shown in Fig. S3a. When we plot 1/C ϕ (ω) as a function of log 10 ω, the slope at ψ ϕ = 0, i.e., at ω = 1/τ ϕ , is given by independent of R ϕ , where e is the base of natural logarithm. This means the width of the slope at ω = 1/τ ϕ is fixed to log 10 e, and the slow increase of measured 1/C ϕ (ω) as a function of log 10 ω cannot be explained by this naive model. This is clearly seen in Fig. S3b. Therefore, we assumed either HfO 2 or Parylene-C layer has a gradient of resistance along the thickness. Here the layer is divided into N sublayers, and each sublayer has a capacitance of NC α with a parallel resistance of R α,j (j = 1, 2, ..., N). For simplicity, the slow increase of the measured 1/C α (ω) is supposed to be proportional to log 10 ω between ω 1 and ω N . In other words, log 10 R α,j changes linearly from log 10 (1/NC α ω 1 ) to log 10 (1/NC α ω N ) (Fig. S3c). A schematic picture of the model is depicted in the inset of Fig. S3d, and the solid line of Fig. S3d demonstrates that the model can fit the measured capacitance fairly well. The values of the parameters used in the fittings are summarised in Table S1.
From the values of C α = 79.6 pF and C β = 95.3 pF obtained from the fitting, it is reasonable to consider the subscript α denotes Parylene-C while β denotes HfO 2 . Then, the dielectric constant of our HfO 2 layer becomes about 21.5, and TABLE S1. Values of the parameters used for the fitting of ac capacitance C(ω) to an equivalent circuit model shown in Fig. S3b and Fig. S3d. CP, CHf, and Cps stand for the capacitances of Parylene-C HfO2 and some parasitic contribution, respectively, while RP, RHf, and Rps are their resistances which are set parallel to the capacitors. For the fitting in Fig. S3d, we assumed that the linear change of 1/C(ω) in the region where log 10 ω between log 10 ω1 and log 10 ωN is due to the linear change of log 10 RP,j from log 10 RP,1 to log 10 RP,N, where j = 1, ..., N is the index of the N sublayers within the 3 nm Parylene-CṪhat is, RP,1 = 1/N CP ω1 and RP,N = 1/N CP ωN   The parallel resistance of the 3 nm Parylene-C layer has a variation from 10 12 Ω down to 10 5 Ω (Fig. S3c). In our naive model, we assumed the resistance may change in the film; instead, it is also possible to assume the capacitance may have a variation. [4] In reality, we think both the capacitance and the resistance may change.
Since our main objective in this study was to utilise the ultra-thin Parylene-C for a passivation layer, and it was successfully confirmed. Therefore, we leave the mechanism of the resistance/capacitance variation of the ultra-thin Parylene-C film for future studies. It should be noted in passing that the high frequency limit of the capacitance C ∞ without the parasitic contribution is This value is in reasonable agreement with 0.47 µF/cm 2 obtained by the quasi-static measurement described in the main text.

HALL EFFECT MEASUREMENTS
Hall effect measurements were carried out using the Agilent Technology E5287A high-resolution source/monitor unit modules equipped on the E5270B precision measurement mainframe. The  temperature and the magnetic field control were done by using the Quantum Design physical properties measurement system (PPMS), where the sample was mounted on the Multi-Function Probe with Al wires attached to the electrode pads of the device by an ultrasonic bonding. The voltage difference ∆V between the voltage probes V 2 and V 5 (Fig. 2d of the main text) perpendicular to the channel current I SD was measured in the magnetic field B applied perpendicular to the channel surface. The jagged solid line (red) in Fig. S4a corresponds to the ∆V = V 5 − V 2 for V G = 2.8 V and V SD = 0.5 V (left axis) and the smooth solid line (blue) corresponds to the magnetic field B (right axis), plotted against the time elapsed. Field independent contribution as indicated by the dashed line (green) in Fig. S4a, was subtracted from ∆V to obtain V H plotted against B in Fig. S4b.
In general, I SD is fixed during Hall effect measurements, however, in our measurement, it was not tractable because the current is not a proper valuable for the measurement of the highly resistive channel. Thus, we fixed V SD instead of I SD Despite the change of I SD from time to time, our Hall resistance R xy = V H / I SD (Fig. S4c) showed an almost linear dependence of B for V G in the range of 1-3 V. Hall coefficient R H = V H / I SD B was then obtained directly from the slope of the R xy -B plot by a least-squares linear fitting of the data. The sheet carrier density n is deduced from n = 1/e R H .
The multi-terminal device used for the measurement of Fig. S4a-c underwent an electric breakdown for V G above 3 V, so we repeated the same measurement for another multi-terminal device. The results are shown in Fig. S4d-f. The data were more scattered for this sample, because the electric contact either of the V 2 or V 5 probe might not be good. However, the magnitude of the data were not so different from the previous data set. Since we have applied V G up to 6.4 V for this device, n derived from these data is used in the main text.

HYSTERESIS
The channel current I SD did not show hysteresis if the applied V G was below the threshold voltage V th . The definition of V th is described in the main text. Figure S5 shows an example of I SD -V G characteristics measured for the multi-terminal device shown in Fig. 2d of the main text. When we increase V G , at V G ≃ 5.5 V, log 10 I SD vs. V G curve shows a deviation from a linear behaviour. Thus, we can assume the threshold voltage V th is around 5.5 V. Interestingly, for V G < 5 V, there appears no hysteresis in the I SD -V G characteristics as depicted by solid circles connected by solid lines (green) of Fig. S5, but for V G > 5 V, large hysteresis appears.  (Fig. 2d of the main text). Solid circles (red) were obtained by changing VG from 0 V to 6 V and then to 0 V with the sweeping rate of 20 min/V (10 min waiting time for every 0.5 V step of VG). Solid circles connected by solid lines (green) stand for the same ISD-VG but VG was changed from 0 to 5 V. If the maximum VG is below the threshold voltage V th of around 5.5 V, no hysteresis appears. ISD-VG curve of the same device for the VG sweeping rate of 30 min/V (3 min waiting time for every 0.1 V step of VG) is depicted by the opaque circles (blue). It seems that ISD increased about a decade, or rather that VG decreased about 0.5 V.
It should be noted that this V th , which is eventually identical to the threshold for the appearance of the hysteresis, is much larger than V G at which the negative capacitance becomes dominant (see Fig. 3a in the main text). In other word, the observed negative capacitance, i.e., the enhancement of n above C ins V G /e, does not necessary accompany the hysteresis, which is generally attributed to an appearance of ferroelectricity in gate insulator. Indeed, as shown in the inset of Fig. 4a of the main text, the capacitance of our Parylene-C/HfO 2 gate insulator does not change more than 2 % even for the application of V G = 8 V for about an hour.
Since the SrTiO 3 single crystal of 0.5 mm thick used in this work was a good insulator, we were necessary to apply V G for sufficiently long time (about an hour) in order to accumulate the thermal carriers from the bulk substrate to the channel surface. Therefore, the longer time we take for increasing V G , the larger I SD we observe. The opaque circles (blue) in Fig. S5 correspond to I SD as a function of V G obtained by varing V G in 50 % longer time. The I SD -V G curve shifted to smaller V G direction (about 0.5 V) and to larger I SD direction (about a decade). The shape of the I SD -V G hysteresis does not change much (for applying V G smaller than V th , no hysteresis appears in this case as well), and the result of the Hall effect measurement is not sensitive to I SD . However, we believe the origin of the hysteresis is by and large related to the unusual enhancement of n , and should be unravelled by further experiments.

MOBILITY
Mobility µ of the carriers is given by where e is the elementary charge and σ is the sheet conductance (without magnetic field B) defined as σ ≡ (I SD /W )/(V SD /L). For our multiterminal FET device (Fig. 2d of the main text), and ∆L is the distance between V 3 and V 1 probes, i.e., 12 µm. During the Hall effect experiments, we measured both n and σ ; the values of σ for B = 0 are plotted against n as shown in Fig. S6. The solid line (green) is the least-squares linear fit, which gives µ = 10.9 cm 2 /Vs at room temperature.
In general, the field-effect mobility µ FE defined as gives a good measure to evaluate the quality of the channel. Actually, if both C and ∆V are independent of V G , the above expression of µ FE becomes a well-know equation: But, this is not a valid equation for our FET, because both C and ∆V depends significantly on V G in our case. Nevertheless, in order to have a  brief comparison of µ FE in the subthreshold region of our three-terminal FETs, we may substitute log 10 I SD = V G /S to Eq. S1 with the subthreshold swing S = 172 mV/decade, ∆L = L = 20 µm, W = 80 µm, ∆V = V SD = 1 V, and C = 0.28 µF/cm 2 . Then, we obtain µ FE = 1.9 × 10 7 I SD cm 2 /Vs. Since the channel current I SD can reach to 10 −7 A or larger values, µ FE of our three-terminal FET can be in the range of 1-10 cm 2 /Vs. This is consistent to the carrier mobility µ = 10.9 cm 2 /Vs deduced from the σ = n eµ relationship. The observed value of µ ≃ 11 cm 2 /Vs is much larger than the values reported for other SrTiO 3 FETs, [5][6][7][8] corroborating the comparatively good quality channel of our FET. In addition, as a pilot work, we reported µ FE ∼ 10 cm 2 /Vs using Ta 2 O 5 /Parylene-C bilayer on SrTiO 3 (Ref. 9). Both the thickness of Parylene-C ( 60 nm) and the channel area ( 0.16 mm 2 ) were one to four orders larger than those of the present work, hence the results are not simply compared. However, the results also support that the Parylene-C passivation of the SrTiO 3 surface is indeed significantly effective.

INHOMOGENEITY OF THE CHANNEL
Here we describe a phenomenological inhomogeneity model of the channel capacitance. Fig. S7a shows the n (open circles) and 1/ C STO (blue solid lines), both of which are same as in Fig. 4a in the main text. We have decomposed 1/ C STO in solid line (blue) into the dotted line (green) and the dashed line (purple); the former behaves C STO → 20 µF/cm 2 and the latter does C STO → −30 µF/cm 2 , respectively, for V G → ∞ (Inset of Fig. S7a). We have assumed here the channel is a parallel connection of the two capacitors, C STO = (1 − ξ) C + +ξ C − , where C − is the sheet capacitance of the domain schematically depicted as purple circles in Fig. S7b, and C + is that of the background. ξ is determined to fit to 1/ C STO for each value of V G . In fact, the set of C + and C − can be arbitrary chosen, though either of them should be negative. Here, C − = −30 µF/cm 2 gives ∆µ ≃ 24 meV for ∆ n ≃ 5×10 13 cm −2 (4 ≲ V G ≲ 6), and C + = 20 µF/cm 2 gives the thickness of 14 nm for the dielectric constant 310 of SrTiO 3 . Those values are more realistic than ∆µ ≃ −26 eV deduced from C STO = −0.31 µF/cm 2 that we discussed above.
We think 1/ C STO may go to zero for V G → ∞, but we could not measure n for such large V G ; hence, in this work, we assume C STO → −0.31 µF/cm 2 , leading to ξ = 40 % for V G → ∞. The domains with the negative capacitance must be metallic, while the domains with the positive The domain-formation is schematically depicted. Top: each circle (pink) corresponds to a metallic island with C STO = C − while the background (green) is less conductive with C STO = C + . Bottom: by increasing VG, metallic domains become larger and finally the current path (solid line in black) is formed. c, ISD and IG as well as ∆V ≡ V3 − V1 normalised by VSD plotted against VG. In general, ∆V is expected to increase monotonously as a function of VG, but the sudden decrease of ∆V while increasing VG suggests the formation of the metallic path in the channel.
capacitance cannot be regarded as metallic, because C + = 20 µF/cm 2 is not large enough. Hence, ξ → 40 % for V G → ∞ means the source and drain electrodes are connected by a metallic path of connected C − regions in the C + background at a particular V G . At that V G , the potential distribution in the channel should be decreased rapidly. [9] This is indeed observed as shown in Fig. S7c; an evidence that the inhomogeneity plays a significant role in our FET. However, if there exists such an inhomogeneity in the channel, what did we actually measure by the Hall effect? The problem of the Hall coefficient of inhomogeneous two-dimensional systems was intensively discussed in 1980s. A well-known example of the calculation of Hall coefficients of twodimensional metal/insulator inhomogeneous system was given by D. Stroud and D. J. Bergman [10]. They concluded that the Hall coefficient of the 2D metal/insulator inhomogeneous system does not depend on the volume fraction of the metallic/insulating domains and is equal to the Hall coefficient of the whole homogeneous metallic plane. According to this calculation, the Hall coefficient observed by our measurement should be equal to that of the metallic domains, even if there is an inhomogeneity. This means the metallic domains have C STO = −0.31 µF/cm 2 and ∆µ ≃ −26 eV, which is too large and would not be simply accepted.
There has been no theoretical model of Hall coefficient of the inhomogeneous two-dimensional system with negative capacitance. We hope our observation shown in this work will motivate further studies and substantiating results will be obtained in the future works.