Introduction

Scientists have been interested in renewable energy sources such as photovoltaic (PV) to produce electricity because they appeared to be the most efficient and effective solution to the environmental problems that the world faces today. The unregulated low-level DC output voltage from these sources is considered the biggest and the most important challenge that requires to be boosted to a regulated higher level using power electronic conditioning. The power electronic interface specification is dependent not only on the renewable energy supply but also on its effects on the power-system operation1. To obtain the voltage step-up function, a conventional non-isolated DC/DC boost converter was used2 because of its simple structure, simple control, and low cost. But it provided a limited practical gain because of their parasitic elements and must be operated at an extreme duty cycle in order to obtain high voltage gain. That causes a high-semiconductors voltage stress, diode reverse recovery problems, and high switching loss which decrease the system performance and efficiency. In3, cascaded boost converter has been successful in solving some of the problems appeared with conventional boost converter as it can attain a reasonable high voltage gain without working at extreme duty cycle, and the voltage stress through the switches remains lower than the voltage across the load. But, it has higher losses, lower efficiency, and electromagnetic interference problems. In switched-capacitor-based converters4,5 and switched capacitor/switched inductor-based converters6,7,8,9 high-voltage gain with small duty cycle, small voltage stress across the switches can be attained, and these converters can be used in a wide range of power. However, they have some problems such as higher losses, lower efficiency, electromagnetic interference problems, and reverse recovery problem.

The use of high-frequency transformers can increase the voltage gain as well as isolation, and then, full-bridge-based topologies can be used10, but with limited power capability, higher losses, lower efficiency, and higher cost. Full-bridge, half-bridge, fly back, forward, and push–pull converters are used at various voltage and power levels11,12,13,14 where isolation is needed. However, they suffer from numerous restrictions which reduce their efficiency, reduce performance in high step-up applications, and make the system more complicated and bulkier. They have also a limited range of increasing the voltage level besides higher voltage stress. Also, a massive turn-off voltage spikes in the power switch is generated due to the leakage inductance, which results in additional voltage stress on the components that require a snubber circuit to clamp the switch voltage resulting in a bigger size and more expensive. A high gain DC/DC converter utilizing coupled inductor and voltage multiplier cell that achieves high gain at a small duty ratio, and low voltage stress across the semiconductor components is presented in15. However, it is a hard switching circuit that shortens the life of its components, furthermore, the voltage multiplier cell makes the system bulky and more expensive. Magnetically coupled inductors topologies are presented in16,17,18 which increase the output voltage gain of the converter with transfer energy stored in coupled inductance and decrease the normalized voltage stress across the semiconductors. However, a clamping circuit is needed to prevent switching spikes and recover the leakage energy due to the leakage inductance which produces voltage spikes and ringing.

Recently, several DC/DC converters are presented such as a high voltage gain quasi-Z-source DC/DC converter19 that gives a high voltage gain at the low duty cycle and low voltage stress on the semiconductors. However, it works with hard switching making more losses that affect the system performance and efficiency, and it has a limited gain as it is used only for duty cycles less than 0.3. In20, a single switch DC/DC converter with non-coupled inductors is used that achieves high voltage gain with high efficiency. The major drawback is it has a large number of passive components that make the system bulkier and more expensive. A high voltage gain p-type DC/DC converter is presented in21 that has the advantages of high gain with small duty cycle, continuous input current, common ground, and low voltage stress on semiconductors devices. However, it operates with hard switching and requires a high number of components that making the system larger and more expensive. To improve the voltage gain, a single switch three-Z-network converter is presented in22. Although a high voltage gain is achieved, it has a large number of passive components which increase the losses and reduce the efficiency. An impedance network DC/DC boost converter is used in23 that reaches a high voltage gain with a small number of diodes and small duty cycle that avoids instability caused by saturation of its inductors. But, the main drawback of the converter is the lower efficiency. In24, a step-up DC/DC converter with switched capacitor cells is presented. The converter provides high voltage gain at low duty ratios, low voltage stress on the switches and, switched capacitors, and it can be expanded. However, it has a large number of active and passive components that makes the converter size larger and more expensive.

A single power switch high gain DC/DC converter with advantages of continuous input current, a small number of active components, and low voltage stress across the power switch and diodes is proposed in25. But, it is limited power and has a large number of passive components. A non-isolated high gain DC/DC converter for dc micro grid applications with a single switch is presented in26, with the advantage of simple control, and low voltage stress across the semiconductor devices. Even so, it operates with hard switching and has a large number of passive components. A transformer-less DC/DC converter based on a coupled inductor and switched capacitor–boosting techniques that increase the voltage gain with a low duty cycle is presented in27. Although the voltage stresses across the active components are reduced, it operates with hard switching, has large losses and large number of elements, and hence large size and high expensive. A switched-inductor double power switches high gain DC/DC converter (SL-DS-DC) with higher voltage gain is presented in28. However, it has more passive and active components which make the system bulkier and more expensive. A simple control scheme to improve the performance of a quadratic boost converter is presented in29. This scheme provides a faster transient response and better noise immunity, but it has a large number of passive components, high losses because of hard switching, low efficiency, large size, and more expensive. High gain-switched boost DC/DC converters contain switched capacitor/switched inductor cells are presented in30. The converters have advantages such as high voltage gain at non-extreme duty cycle, low voltage stresses across the switches and output diode, and they can be expanded to give higher voltage gain. To provide higher gain, more cells should be added but this makes the system bulkier and is more expensive. In31, a transformer-less high step-up DC/DC converter consisting of an active switched-inductor with quasi-Z-source circuit is offered. High voltage gain at the low duty cycle and high efficiency are achieved. The main drawback is the semiconductors’ components increased by increasing the switched-capacitor cells. A double boost-fly back converter is introduced in32, the static gain is increased with the reduction of input current ripple where a combination between two conventional boost-fly back converters with input-parallel and floating output is done. However, if the converter operates with a duty cycle less than 0.5, the input current will be discontinuous with greater ripple. Also, with the increased number of fly back cells more sensors are needed which makes the system bulkier and more expensive.

In this paper, a new design of a non-isolated high-voltage gain DC/DC boost converter operating with a reasonable duty cycle by integrating dual boost converter with switched inductor structure is presented. The proposed converter operates with soft-switching (zero current switching (ZCS) mode for all switches and diodes. High voltage gain, low switching stress, small switching losses, and high efficiency are achieved. The operating modes, steady-state analysis, and design guidelines of the proposed circuit are discussed. Experimental results for the open and closed loops are conducted to verify the validity of the proposed circuit.

Description and operating modes

The proposed converter is composed of two similar converters connected to the same source as shown in Fig. 1. Each converter has two inductors, one capacitor, four diodes, and one switch. The four inductors have the same magnitude. The two switches are controlled in 180° phase delay to each other simultaneously. The proposed converter works in four modes as presented in Fig. 2. The key operating waveforms of the proposed converter are displayed in Fig. 3.

Figure 1
figure 1

Proposed DC/DC converter.

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Figure 2
figure 2

Operating modes of proposed converter. (a) Operating mode 1. (b) Operating mode 2. (c) Operating mode 3. (d) Operating mode 4.

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Figure 3
figure 3

Operating waveforms of the proposed converter at D = 0.4.

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Mode 1

In this mode, i.e. (0 ≤ t ≤ t1), the switch SW1 turns on, the switch SW2 turns off, the diodes D3, D4, D5, and D7 are reversed biased and the diodes D1, D2, D6, and D8 are forward biased. The first switched inductors L1 and L2 are connected in parallel with each other and being charged through the input voltage source (VS) and the current through them increases. The current through the second switched inductors L3 and L4, which connected in series with each other, decreases and the voltage across them becomes VS − VC2 that charges the capacitor C2 with input source VS. However, the capacitor C1 discharges through the load. It is noted that Vs is in series with both the output capacitors where the output load voltage (Vo) is VC1 + VC2 − VS.

The voltage and current equations related to this mode are;

$$ {\text{V}}_{{\text{S}}} = {\text{V}}_{{{\text{L1}}}} = {\text{V}}_{{{\text{L2}}}} ;{\text{V}}_{{{\text{C2}}}} = {\text{V}}_{{\text{S}}} + {\text{V}}_{{{\text{L3}}}} + {\text{V}}_{{{\text{L4}}}} ;\;{\text{V}}_{{\text{o}}} = {\text{V}}_{{{\text{C1}}}} + {\text{V}}_{{{\text{L3}}}} + {\text{V}}_{{{\text{L4}}}} = {\text{V}}_{{{\text{C1}}}} + {\text{V}}_{{{\text{C2}}}} {-}{\text{V}}_{{\text{S}}} $$
(1)
$$ {\text{i}}_{{{\text{S1}}}} = {\text{i}}_{{{\text{L1}}}} + {\text{i}}_{{{\text{L2}}}} ;\;{\text{i}}_{{{\text{L3}}}} = {\text{i}}_{{{\text{L4}}}} = {\text{i}}_{{{\text{C2}}}} + {\text{i}}_{{\text{o}}} ;\;{\text{i}}_{{\text{o}}} = {\text{i}}_{{{\text{C1}}}} . $$
(2)

Mode 2

During this mode, i.e. (t1 ≤ t ≤ t2), the switch SW1 is still turn on, the switch SW2 is still turn off, the diodes D3, D4, D5, D6, D7, and D8 are reversed biased and the diodes D1 and D2 are forward biased. The first switched inductors L1 and L2 are still connected in parallel with each other and being charged through VS and the current through them still increasing. The current through the second switched inductors L3 and L4 becomes zero as the diodes D6 and D8 are reversed biased. The capacitors C1 and C2 discharged through the load, and VS is in series with them.

The voltage and current equations related to this mode are:

$$ {\text{V}}_{{\text{S}}} = {\text{V}}_{{{\text{L1}}}} = {\text{V}}_{{{\text{L2}}}} ;\;{\text{V}}_{{\text{o}}} = {\text{V}}_{{{\text{C1}}}} + {\text{V}}_{{{\text{C2}}}} {-}{\text{V}}_{{\text{S}}} $$
(3)
$$ {\text{i}}_{{{\text{L3}}}} = {\text{i}}_{{{\text{L4}}}} = 0;\;{\text{i}}_{{{\text{S1}}}} = {\text{i}}_{{{\text{L1}}}} + {\text{i}}_{{{\text{L2}}}} ;\;{\text{i}}_{{\text{o}}} = {\text{i}}_{{{\text{C1}}}} = {\text{i}}_{{{\text{C2}}}} . $$
(4)

Mode 3

In this mode, i.e. (t2 ≤ t ≤ t3), both switches SW1 and SW2 turn off. The diodes D1, D2, D4, and D5 are reversed biased and the diodes D3, D6, D7, and D8 are forward biased. The first switched inductors L1 and L2 are connected in series with each other, and the voltage across them is VS − VC1. Also, the current through them decreases and charges the capacitor C1 with input voltage source VS as diode D7 is forward biased. The second switched inductors L3 and L4 are connected in series with each other, and the voltage across them is VS − VC2. Also, the current through them decreases and charges the capacitor C2 with input voltage source VS as diode D8 is forward biased. Both the output capacitors are charged, and their voltage increases. They are in series with VS.

The voltage and current equations related to this mode are;

$$ {\text{V}}_{{{\text{L1}}}} + {\text{V}}_{{{\text{L2}}}} = \left( { - {\text{V}}_{{{\text{C1}}}} + {\text{V}}_{{\text{S}}} } \right);\;{\text{V}}_{{{\text{L3}}}} + {\text{V}}_{{{\text{L4}}}} = \left( { - {\text{V}}_{{{\text{C2}}}} + {\text{V}}_{{\text{S}}} } \right);\;{\text{V}}_{{\text{o}}} = {\text{V}}_{{{\text{C1}}}} + {\text{V}}_{{{\text{C2}}}} {-}{\text{V}}_{{\text{S}}} $$
(5)
$$ {\text{i}}_{{1}} = {\text{i}}_{{3}} + {\text{i}}_{{4}} ;\;{\text{i}}_{{3}} = {\text{i}}_{{2}} = {\text{i}}_{{{\text{C2}}}} ;\;{\text{i}}_{{4}} = {\text{i}}_{{{\text{C1}}}} + {\text{i}}_{{\text{o}}} ;\;{\text{i}}_{{1}} = {\text{i}}_{{{\text{C1}}}} + {\text{i}}_{{{\text{C}}2}} + {\text{i}}_{{\text{o}}} . $$
(6)

Mode 4

In this mode, i.e. (t3 ≤ t ≤ TS), the switch SW1 is still turn off and the switch SW2 is still turn on. The diodes D1, D2, D3, D6, D7, and D8 are reversed biased, and the diodes D4 and D5 are forward biased. The current through the first switched inductor L1 and L2 becomes zero as the diodes D3 and D7 are reversed biased. The second switched inductors L3 and L4 are still connected in parallel with each other and being charged through VS, and the current through them still increasing. The capacitors C1 and C2 discharged through the load, and Vs is in series with both the output capacitors.

The voltage and current equations related to this mode are;

$$ {\text{V}}_{{\text{o}}} = {\text{V}}_{{{\text{C}}1}} + {\text{V}}_{{{\text{C}}2}} {-}{\text{V}}_{{\text{S}}} $$
(7)
$$ {\text{i}}_{{{\text{L1}}}} = {\text{i}}_{{{\text{L2}}}} = 0;\;{\text{i}}_{{{\text{S2}}}} = {\text{i}}_{{{\text{L3}}}} + {\text{i}}_{{{\text{L4}}}} ;\;{\text{i}}_{{\text{o}}} = {\text{i}}_{{{\text{C1}}}} = {\text{i}}_{{{\text{C2}}}} . $$
(8)

Derivation of voltage gain

For the analysis point of view, the power losses are ignored. For the reason that both converters are boost type, it is assumed that the capacitor voltages VC1 and VC2 are larger than the input voltage VS. Also, both converters have equal duty cycles, the same value of inductances, and the output voltage for each converter has the same average value.

$$ {\text{D}}_{{1}} = {\text{D}}_{{2}} = {\text{D}};\;{\text{L}}_{{1}} = {\text{L}}_{{2}} = {\text{L}};\;{\text{V}}_{{{\text{C1}}}} = {\text{V}}_{{{\text{C2}}}} = {\text{V}}_{{\text{C}}} . $$
(9)

During the on-state for one converter, the switch SW is closed. Therefore, the input voltage VS appears across the switched inductors. As a result, a change in the current ΔiL flows through the switched inductors during a time period Δt by the formula: ΔiL = (1/Leq1) VS Δt.

$$ \Delta_{{{\text{iL}}}} = (1/{\text{L}}_{{{\text{eq}}1}} ){\text{V}}_{{\text{S}}} \Delta {\text{t}}{.} $$

where Leq1 is the equivalent inductance of the switched inductors during the on-state, and it is equal to L/2 as the two inductors are connected in parallel.

At the end of the on-state, the increase of iL is:

$$ \Delta {\text{i}}_{{{\text{L}} - {\text{on}}}} = (1/{\text{L}}_{{{\text{eq}}1}} )\int\limits_{0}^{{{\text{DT}}}} {{\text{V}}_{{{\text{in}}}} } \Delta {\text{t}} = (2/{\text{L}}){\text{V}}_{{\text{S}}} ({\text{DT}} - 0) $$
$$ \Delta {\text{i}}_{{\text{L - on}}} = \left( {2{\text{V}}_{{\text{S}}} /{\text{L}}} \right){\text{DT}}{.} $$
(10)

Alternatively, the switch SW is open during the off-state. Thus, the inductor current flows through the load. If zero voltage drops in the diode is considered, and the capacitor is large enough for its voltage to stay constant, the evolution of iL is: VS − VC = L (diL/ dt).

Then, the change of iL during the off-period is:

$$ \Delta {\text{i}}_{{\text{L - off}}} = (1/{\text{L}}_{{{\text{eq}}2}} )\int\limits_{{{\text{T}}_{{{\text{on}}}} }}^{{\text{T}}} {{\text{V}}_{{{\text{in}}}} } \Delta {\text{t}} $$

where Leq2 is the equivalent inductance of the switched inductors during the off-state, and it is equal to 2L as the two inductors are connected in series.

$$ \Delta {\text{i}}_{{\text{L - off}}} = (1/2{\text{L}})\left[ {\int\limits_{{{\text{T}}_{{{\text{on}}}} }}^{{{\text{t}}_{1} }} {( - {\text{V}}_{{{\text{C}}1}} + {\text{V}}_{{\text{S}}} )} \Delta {\text{t}} + \int\limits_{{{\text{t}}_{1} }}^{{\text{T}}} {( - {\text{V}}_{{{\text{SW}}1}} + {\text{V}}_{{\text{S}}} )\Delta {\text{t}}} } \right] $$

and t1 = (D + 0.2) T

$$ \Delta i_{{\text{L - off}}} = ({\text{T}}/2{\text{L}})[(2 + 14{\text{D}}){\text{V}}_{{\text{S}}} - (2 - 0.5{\text{D}}){\text{V}}_{{{\text{C}}1}} ]. $$
(11)

On the basis that the converter works in steady-state conditions, the amount of stored energy in each of its components has to be the same at the beginning and at the ending of the commutation cycle. Particularly, the stored energy in the inductor is given by:

$$ E = 0.{5}\;{\text{L}}\;{\text{i}}^{{2}} . $$

Therefore, the inductor current has to be the same at the start and end of the commutation cycle. This means the overall change in the current (the sum of the changes) is zero:

$$ \Delta {\text{i}}_{{\text{L - on}}} + \Delta {\text{i}}_{{\text{L - off}}} = 0 $$

Substituting ΔiL-on and ΔiL-off by their expressions yields:

$$ \frac{{{\text{V}}_{C1} }}{{{\text{V}}_{{\text{S}}} }} = \frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}} $$

Each module is a separate boost converter with switched inductors. Therefore, the voltage across the output capacitors C1 and C2 can be expressed as:

$$ {\text{V}}_{C1} = {\text{V}}_{{{\text{C}}2}} = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} . $$
(12)

As clarified through the explanation of the different modes of operation, the two output capacitors are always in series with the input voltage source. Then, the output voltage can be given by:

$$ {\text{V}}_{{\text{o}}} = {\text{V}}_{{{\text{C1}}}} + {\text{V}}_{{{\text{C2}}}} {-}{\text{V}}_{{\text{S}}} . $$
(13)

From (12) and (13), the voltage gain of the proposed converter can be calculated by:

$$ {\text{G}} = \frac{{{\text{V}}_{{\text{o}}} }}{{{\text{V}}_{{\text{S}}} }} = \frac{{1 + 18.25{\text{D}}}}{{1 - 0.25{\text{D}}}}. $$
(14)

Design consideration

In this part, the main converter components are chosen using analytical relations derived from the converter operation. The design of inductors and capacitors depends on both the voltage across them and the current flowing through them.

Inductor Design

In case of D < 0.5, the inductors and input currents at t = T/2 can be obtained by;

$$ {\text{i}}_{4} \left( {\frac{{\text{T}}}{2}} \right) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{i}}_{{\text{o}}} + \frac{{\Delta {\text{i}}_{{\text{L}}} }}{2} - \frac{{\Delta {\text{i}}_{{\text{L}}} }}{{1 - {\text{D}}}}(0.5 - {\text{D}});\;{\text{i}}_{2} \left( \frac{T}{2} \right) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{i}}_{{\text{o}}} - \frac{{\Delta {\text{i}}_{{\text{L}}} }}{2};\;{\text{i}}_{1} \left( {\frac{{\text{T}}}{2}} \right) = \left( {\frac{{1 + 18.25{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{i}}_{{\text{o}}} - \frac{{\Delta {\text{i}}_{1} }}{2}. $$
(15)

The input current can be obtained by:

$$ {\text{i}}_{{1}} = {\text{i}}_{{4}} + {\text{i}}_{{2}} {-}{\text{i}}_{{\text{o}}} . $$
(16)

Using (15)–(16), the input current ripple can be expressed as:

$$ \Delta {\text{i}}_{1} = \frac{{2(0.5 - {\text{D}})}}{{1 - {\text{D}}}}\Delta {\text{i}}_{{\text{L}}} . $$
(17)

The inductor current ripple can be expressed as:

$$ \Delta {\text{i}}_{{\text{L}}} = \frac{{({\text{V}}_{{\text{C}}} - {\text{V}}_{{\text{S}}} )(1 - {\text{D}})}}{{{\text{L}}_{{\text{eq - on}}} }}{\text{T}}. $$
(18)

From (17) and (18) the inductance can be obtained by:

$$ {\text{L}} = \frac{{4\left( {{\text{V}}_{{\text{C}}} - {\text{V}}_{{\text{S}}} } \right)\left( {0.5 - {\text{D}}} \right)}}{{{\text{f}}_{{\text{S}}} \;\Delta {\text{i}}_{1} }} $$
(19)

where fS is the switching frequency.

In a similar way in case of D > 0.5, the inductors and input currents at t = T/2 can be obtained by,

$$ {\text{i}}_{4} \left( {\frac{{\text{T}}}{2}} \right) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{i}}_{{\text{o}}} + \frac{{\Delta {\text{i}}_{{\text{L}}} }}{2} - \frac{{\Delta {\text{i}}_{{\text{L}}} }}{{1 - {\text{D}}}}({\text{D}} - 0.5);\;{\text{i}}_{2} \left( {\frac{{\text{T}}}{2}} \right) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{i}}_{{\text{o}}} - \frac{{\Delta {\text{i}}_{{\text{L}}} }}{2};\;{\text{i}}_{1} \left( {\frac{{\text{T}}}{2}} \right) = \left( {\frac{{1 + 18.25{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{i}}_{o} - \frac{{\Delta {\text{i}}_{1} }}{2}. $$
(20)

Using (16) and (20), the input current ripple can be expressed as:

$$ \Delta {\text{i}}_{1} = \frac{{2({\text{D}} - 0.5)}}{{1 - {\text{D}}}}\Delta {\text{i}}_{{\text{L}}} . $$
(21)

The inductor current ripple can be expressed as:

$$ \Delta {\text{i}}_{{\text{L}}} = \frac{{{\text{V}}_{{\text{S}}} (1 - {\text{D}})}}{{{\text{L}}_{{\text{eq - on}}} }}{\text{T}}{.} $$
(22)

From (21) and (22) the inductance can be obtained by:

$$ {\text{L}} = \frac{{4{\text{V}}_{{\text{S}}} ({\text{D}} - 0.5)}}{{{\text{f}}_{{\text{S}}} \;\Delta {\text{i}}_{1} }}. $$
(23)

Finally, the larger value of the two calculated from (19) to (23) is chosen.

Capacitor Design

In case of D > 0.5, the capacitors and output voltages at t = D.T can be obtained by,

$$ \begin{aligned} & {\text{V}}_{{{\text{C}}1}} ({\text{DT}}) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} - \frac{{\Delta {\text{V}}_{{\text{C}}} }}{2};\;{\text{V}}_{{{\text{C}}2}} ({\text{DT}}) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} + \frac{{\Delta {\text{V}}_{{\text{C}}} }}{2} - \frac{{\Delta {\text{V}}_{{\text{C}}} }}{{\text{D}}}({\text{D}} - 0.5); \\ & {\text{V}}_{{\text{o}}} ({\text{DT}}) = \left( {\frac{{1 + 18.25{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} - \frac{{\Delta {\text{V}}_{{\text{o}}} }}{2}. \\ \end{aligned} $$
(24)

Using (13) and (24), the output voltage ripple can be expressed as:

$$ \Delta {\text{V}}_{{\text{o}}} = \frac{{2\left( {{\text{D}} - 0.5} \right)}}{{\text{D}}}\Delta {\text{V}}_{{\text{C}}} . $$
(25)

The capacitor voltage ripple can be calculated by:

$$ \Delta {\text{V}}_{{\text{C}}} = \frac{{{\text{D}}\;{\text{i}}_{{\text{o}}} }}{{{\text{f}}_{{\text{S}}} \;{\text{C}}}}. $$
(26)

From (25) and (26), the capacitance can be obtained by:

$$ {\text{C}} = \frac{{2({\text{D}} - 0.5){\text{i}}_{{\text{o}}} }}{{{\text{f}}_{{\text{S}}} \;\Delta {\text{V}}_{{\text{o}}} }}. $$
(27)

In a similar way, in case of D < 0.5, capacitor and output voltages at t = D.T can be obtained by,

$$ \begin{aligned} & {\text{V}}_{{{\text{C}}1}} ({\text{DT}}) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} - \frac{{\Delta {\text{V}}_{{\text{C}}} }}{2};\;{\text{V}}_{{{\text{C}}2}} ({\text{DT}}) = \left( {\frac{{1 + 9{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} + \frac{{\Delta {\text{V}}_{{\text{C}}} }}{2} - \frac{{\Delta {\text{V}}_{{\text{C}}} }}{{\text{D}}}(0.5 - {\text{D}}); \\ & {\text{V}}_{{\text{o}}} ({\text{DT}}) = \left( {\frac{{1 + 18.25{\text{D}}}}{{1 - 0.25{\text{D}}}}} \right){\text{V}}_{{\text{S}}} - \frac{{\Delta {\text{V}}_{{\text{o}}} }}{2}. \\ \end{aligned} $$
(28)

Using (13) and (28), the output voltage ripple can be expressed as:

$$ \Delta {\text{V}}_{{\text{o}}} = \frac{{2(0.5 - {\text{D}})}}{{\text{D}}}\Delta {\text{V}}_{{\text{C}}} . $$
(29)

The capacitor voltage ripple can be expressed as:

$$ \Delta {\text{V}}_{{\text{C}}} = \frac{{{\text{D}}\;{\text{i}}_{{\text{o}}} }}{{{\text{f}}_{{\text{S}}} \;{\text{C}}}}. $$

The capacitance can be obtained by:

$$ {\text{C}} = \frac{{2(0.5 - {\text{D}}){\text{i}}_{{\text{o}}} }}{{{\text{f}}_{{\text{S}}} \;\Delta {\text{V}}_{{\text{o}}} }}. $$
(30)

Finally, the larger value of the two calculated from (27) and (30) is chosen.

Converter power losses and efficiency

In this section, the converter losses are analyzed by calculating the switching losses and conduction losses. The power losses of each device in the proposed converter are estimated, then the total power losses are investigated. Then, the converter efficiency is determined. The proposed converter model with the parasitic components is shown in Fig. 4. For the calculation of conduction loss in the converter, all diodes are considered with cut in voltages VD1, VD2, VD3, VD4, VD5, VD6, VD7 and VD8. Also, the internal resistances are rD1, rD2, rD3, rD4, rD5, rD6, rD7, and rD8. In a Similar way, all inductors and capacitors are also considered with a lumped DC resistance and an equivalent series resistance, respectively. They can be represented as rL1, rL2, rL3, rL4 and rC1, rC2, respectively. Both conduction and switching losses are considered for switch with on-state resistance taken as rsw1, rsw2 for both switches.

Figure 4
figure 4

Equivalent model for the proposed circuit with parasitic elements.

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The switches losses

The practical power switch has conduction and switching losses. Assume that the two switches (SW1 and SW2) have the same rms value of current and on-state resistance.

$$ i_{{S{1}}} = i_{{S{2}}} = i_{S} \;{\text{and}}\;r_{{SW{1}}} = r_{{SW{2}}} = {\text{r}}_{SW} $$

The loss of the switching SW1 is the sum of the conduction and switching losses and can be written as:

$$ P_{loss - total(SW1)} = P_{loss - conduction(SW1)} + P_{loss - switching(SW1)} $$
(31)

where the switching loss of SW1 can be expressed as:

$$ P_{loss - conduction(SW1)} = i_{Srms}^{2} *r_{SW} $$
$$ P_{loss - conduction(SW1)} = \frac{{V_{o}^{2} (1 + 18.25D)^{2} D}}{{4R^{2} (1 - 0.25D)^{2} }}r_{SW} . $$
(32)

The switching loss (Ploss-switching) of the power switch SW1 can be determined by:

$$ P_{loss - switching(SW1)} = P_{loss - switching(SW1) - on} + P_{loss - switching(SW1) - off} $$
$$ P_{loss - switching(SW1)} = \frac{{t_{on} *V_{SW1} *i_{SW - on} *f_{S} }}{2} + \frac{{t_{off} *V_{SW1} *i_{SW - off} *f_{S} }}{2} $$
$$ P_{loss - switching(SW1)} = \frac{{(t_{rt} + t_{ft} )*V_{SW1} *i_{SW1 - avg} *f_{S} }}{2} $$
(33)

where trt and tft is the rise time and fall time of the switch, respectively.

Since the switches operate at ZCS during the turn-on transition period, the switching loss can be expressed as:

$$ P_{loss - switching(SW1)} = \frac{{t_{ft} *V_{SW} *i_{SW - avg} *f_{S} }}{2} $$
$$ P_{loss - switching(SW1)} = \frac{{t_{ft} *V_{o}^{2} (1 + 9D)D*f_{S} }}{4R(1 - 0.25D)}. $$
(34)

Then, the switching loss of SW1 is:

$$ P_{loss - total(SW1)} = \frac{{V_{o}^{2} (1 + 18.25D)^{2} D*r_{SW} }}{{4R^{2} (1 - 0.25D)^{2} }} + \frac{{t_{ft} *V_{o}^{2} (1 + 9D)D*f_{S} }}{4R(1 - 0.25D)} $$
(35)

and the total switching loss can be expressed as:

$$ P_{loss - total(Switches)} = P_{loss - total(SW1)} + P_{loss - total(SW2)} $$
$$ P_{loss - total(Switches)} = \frac{{V_{o}^{2} (1 + 18.25D)^{2} D*r_{SW} }}{{2R^{2} (1 - 0.25D)^{2} }} + \frac{{t_{ft} *V_{o}^{2} (1 + 9D)D*f_{S} }}{2R(1 - 0.25D)}. $$
(36)

The diodes losses

The diodes are assumed to have the same cut in voltages and equivalent series resistance,

$$ \begin{aligned} & V_{{D{1}}} = V_{{D{2}}} = V_{{D{3}}} = V_{{D{4}}} = V_{{D{5}}} = V_{{D{6}}} = V_{{D{7}}} = V_{{D{8}}} = V_{D} \\ & r_{D1} = r_{D2} = r_{D3} = r_{D4} = r_{D5} = r_{D6} = r_{D7} = r_{D8} = r_{D} \\ & i_{D1avg} = i_{D2avg} = i_{D4avg} = i_{D5avg} = i_{Davg} \\ & i_{D1rms} = i_{D2rms} = i_{D4rms} = i_{D5rms} = i_{Drms} \\ & i_{D3avg} = i_{D6avg} = i_{D7avg} = i_{D8avg} = i_{Davg1} \\ & i_{D3rms} = i_{D6rms} = i_{D7rms} = i_{D8rms} = i_{Drms1} . \\ \end{aligned} $$

The total diodes losses can be expressed as:

$$ P_{loss - total(Diodes)} = \sum\limits_{i = 1}^{8} {P_{loss - Di} } $$
(37)

where

$$ P_{loss - D1} = P_{loss - D2} = P_{loss - D4} = P_{loss - D5} = V_{D} *i_{Davg} + i_{Drms}^{2} *r_{D} $$
$$ P_{loss - D1} = P_{loss - D2} = P_{loss - D4} = P_{loss - D5} = \frac{{V_{D} *V_{o} (1 + 18.25D)D}}{4R(1 - 0.25D)} + \frac{{V_{o}^{2} (1 + 18.25D)^{2} D}}{{16R^{2} (1 - 0.25D)^{2} }}*r_{D} $$
$$ P_{loss - D1} = P_{loss - D2} = P_{loss - D4} = P_{loss - D5} = \frac{{V_{o} (1 + 18.25D)D}}{4R(1 - 0.25D)}\left( {V_{D} + \frac{{V_{o} (1 + 18.25D)}}{4R(1 - 0.25D)}*r_{D} } \right) $$
(38)

and,

$$ P_{loss - D3} = P_{loss - D6} = P_{loss - D7} = P_{loss - D8} = V_{D} *i_{Davg1} + i_{Drms1}^{2} *r_{D} $$
$$ P_{loss - D3} = P_{loss - D6} = P_{loss - D7} = P_{loss - D8} = \frac{{V_{D} *V_{o} (1 + 18.25D)D}}{2R(1 - 0.25D)} + \frac{{V_{o}^{2} (1 + 18.25D)^{2} D}}{{4R^{2} (1 - 0.25D)^{2} }}*r_{D} $$
$$ P_{loss - D3} = P_{loss - D6} = P_{loss - D7} = P_{loss - D8} = \frac{{V_{o} (1 + 18.25D)D}}{4R(1 - 0.25D)}\left( {2V_{D} + \frac{{V_{o} (1 + 18.25D)}}{R(1 - 0.25D)}*r_{D} } \right). $$
(39)

Then, the total power loss in the diodes can be determined as:

$$ P_{loss - total(Diodes)} = \frac{{V_{o} (1 + 18.25D)D}}{R(1 - 0.25D)}\left( {3V_{D} + \frac{{5V_{o} (1 + 18.25D)}}{4R(1 - 0.25D)}*r_{D} } \right). $$
(40)

The capacitors losses

The proposed converter contains two capacitors. The total power loss due to the two capacitors is given by:

$$ P_{loss - total(Capacitors)} = \sum\limits_{i = 1}^{2} {P_{loss - Ci} } = i_{C1rms}^{2} *r_{C1} + i_{C2rms}^{2} *r_{C2} . $$

The two capacitors are assumed have the same equivalent series resistance, then:

$$ P_{loss - total(Capacitors)} = i_{C1rms}^{2} *r_{C1} + i_{C2rms}^{2} *r_{C2} = 2i_{Crms}^{2} *r_{C} . $$
(41)

The rms value of current through the capacitor can be estimated using the expression:

$$ i_{C1rms} = i_{C2rms} = i_{Crms} = \frac{{V_{o} }}{R}\left( {D + \frac{(1 - 0.25D)(1 - D)}{{(1 + 18.25D)}}} \right). $$
(42)

Then total power loss due to the two capacitors is given by:

$$ P_{loss - total(Capacitors)} = \frac{{2V_{o}^{2} }}{{R^{2} }}\left( {\frac{{0.25(1 + 18.25D)^{2} D}}{{(1 - 0.25D)^{2} }} + \frac{{17(1 - D)D^{2} }}{{(1 - 0.25D)^{2} }} + 0.8(1 - D)} \right)*r_{C} $$
(43)

The inductors losses

The inductors loss can be expressed as

$$ P_{loss - total(Inductors)} = \sum\limits_{i = 1}^{4} {P_{loss - Li} } = \sum\limits_{i = 1}^{4} {i_{Lirms}^{2} *r_{Li} } $$
$$ P_{loss - total(Inductors)} = i_{L1rms}^{2} *r_{L1} + i_{L2rms}^{2} *r_{L2} + i_{L3rms}^{2} *r_{L3} + i_{L4rms}^{2} *r_{L4} $$
(44)

If the inductors are assumed to have the same internal resistance rL1 = rL2 = rL3 = rL4 = rL, and have the same rms value of the inductor currents.

$$ i_{L1rms} = i_{L2rms} = i_{L3rms} = i_{L4rms} = i_{Lrms} $$
$$ P_{loss - total(Inductors)} = i_{Lrms}^{2} (r_{L1} + r_{L2} + r_{L3} + r_{L4} ) $$
$$ P_{loss - total(Inductors)} = 4i_{Lrms}^{2} r_{L} . $$
(45)

Using the equations in the “Description and operating modes” section, the rms value of the inductor current can be noticed

$$ i_{Lrms} = \frac{{V_{O} (1 + 18.25D)}}{4R(1 - 0.25D)}(0.4 + 0.6D). $$
(46)

Then, substituting in Eq. (45), the total power loss in the inductors can be stated as

$$ P_{loss - total(Inductors)} = (\frac{{V_{O}^{2} (1 + 18.25D)^{2} (0.4 + 0.6D)^{2} }}{{4R^{2} (1 - 0.25D)^{2} }}r_{L} . $$
(47)

Substituting from Eqs. (36), (40), (43), and (47) into the below equation, the total converter loss can be obtained.

The expression for total losses is as follows:

$$ P_{loss - total} = P_{loss - total(Switches)} + P_{loss - total(Diodes)} + P_{loss - total(Capacitors)} + P_{loss - total(Inductors)} . $$
(48)

Finally, the efficiency (ɳ) of the proposed converter can now be determined as:

$$ \eta = \frac{{P_{O} }}{{P_{O} + P_{loss - total} }} $$
(49)

where Po is the output power.

State space representation

This section presents the state space modelling of the proposed converter. The state variables in the proposed converter are selected as the inductor currents (iL1(t), iL2(t)), the capacitor voltages (vC1(t), vC2(t)), and the output voltage (vCo(t)). The input variables are chosen as the input voltage (Vs(t)) and the input current (i1(t)). The equivalent circuits showing the converter behavior of the four modes of operation are used as given in Fig. 2. The corresponding state space differential equations are obtained from these equivalent circuits. Kirchhoff’s voltage and current laws are applied for this purpose.

From equivalent circuit of Fig. 2a, the differential equations for operation mode 1 are derived as,

$$ \left\{ {\begin{array}{*{20}l} {L_{1} \frac{{di_{L1} (t)}}{dt} = V_{S} } \hfill \\ {L_{2} \frac{{di_{L2} (t)}}{dt} = V_{S} } \hfill \\ {i_{C1} (t) = C_{1} \frac{{dv_{C1} (t)}}{dt} = \frac{vo(t)}{R}} \hfill \\ {i_{C2} (t) = C_{2} \frac{{dv_{C2} (t)}}{dt} = - i_{L1} (t) - i_{L2} (t) + i_{1} (t)} \hfill \\ {\frac{{dv_{o} (t)}}{dt} = \frac{vo(t)}{{RC_{1} }} - \frac{{i_{L1} (t)}}{{C_{2} }} - \frac{{i_{L2} (t)}}{{C_{2} }} + \frac{{i_{1} (t)}}{{C_{2} }}} \hfill \\ \end{array} } \right.. $$
(50)

From equivalent circuit of Fig. 2b, the differential equations for operation mode 2 are derived as,

$$ \left\{ {\begin{array}{*{20}l} {L_{1} \frac{{di_{L1} (t)}}{dt} = V_{S} } \hfill \\ {L_{2} \frac{{di_{L2} (t)}}{dt} = V_{S} } \hfill \\ {i_{C1} (t) = C_{1} \frac{{dv_{C1} (t)}}{dt} = \frac{{v_{o} (t)}}{R}} \hfill \\ {i_{C2} (t) = C_{2} \frac{{dv_{C2} (t)}}{dt} = \frac{{v_{o} (t)}}{R}} \hfill \\ {\frac{{dv_{o} (t)}}{dt} = \frac{{v_{o} (t)}}{{RC_{1} }} + \frac{{v{}_{o}(t)}}{{RC_{2} }}} \hfill \\ \end{array} .} \right. $$
(51)

From equivalent circuit of Fig. 2, the differential equations for operation mode 3 are derived as,

$$ \left\{ {\begin{array}{*{20}l} {L_{1} \frac{{di_{L1} (t)}}{dt} = - \frac{{v_{C1} (t)}}{2} + \frac{{V_{S} }}{2}} \hfill \\ {L_{2} \frac{{di_{L2} (t)}}{dt} = - \frac{{v_{C1} (t)}}{2} + \frac{{V_{S} }}{2}} \hfill \\ {i_{C1} (t) = C_{1} \frac{{dv_{C1} (t)}}{dt} = i_{L1} (t) - \frac{{v_{o} (t)}}{R}} \hfill \\ {i_{C2} (t) = C_{2} \frac{{dv_{C2} (t)}}{dt} = i_{1} (t) - i_{L1} (t)} \hfill \\ {\frac{{dv_{o} (t)}}{dt} = \frac{{i_{L1} (t)}}{{C_{1} }} - \frac{{v_{o} (t)}}{{RC_{1} }} - \frac{{i_{L1} (t)}}{{C_{2} }} + \frac{{i_{1} (t)}}{{C_{2} }}} \hfill \\ \end{array} } \right.. $$
(52)

From equivalent circuit of Fig. 2d, the differential equations for operation mode 4 are derived as,

$$ \left\{ {\begin{array}{*{20}l} {L_{1} \frac{{di_{L1} (t)}}{dt} = 0} \hfill \\ {L_{2} \frac{{di_{L2} (t)}}{dt} = 0} \hfill \\ {i_{C1} (t) = C_{1} \frac{{dv_{C1} (t)}}{dt} = \frac{{v_{o} (t)}}{R}} \hfill \\ {i_{C2} (t) = C_{2} \frac{{dv_{C2} (t)}}{dt} = \frac{{v_{o} (t)}}{R}} \hfill \\ {\frac{{dv_{o} (t)}}{dt} = \frac{{v_{o} (t)}}{{RC_{1} }} + \frac{{v_{o} (t)}}{{RC_{2} }}} \hfill \\ \end{array} } \right.. $$
(53)

To derive the transfer function of the proposed converter from the duty ratio to the output voltage, the previous differential equations are used.

The average state space model can be written as:

$$ \begin{aligned} & \dot{x}(t) = Ax(t) + Bu(t) \\ & y(t) = Cx(t) \\ \end{aligned} $$
(54)

where the coefficient matrices A, B, and C are given by:

$$ \begin{aligned} & [A] = A_{1} d_{1} + A_{2} d_{2} + A_{3} d_{3} + A_{4} d_{4} \\ & [B] = B_{1} d_{1} + B_{2} d_{2} + B_{3} d_{3} + B_{4} d_{4} \\ & d = d_{1} + d_{2} + d_{3} + d_{4} = 1 \\ \end{aligned} $$
(55)

where

$$ \begin{aligned} & d_{1} = \left( {d - 0.5} \right) \\ & d_{2} = \left( {1 - d} \right) \\ & d_{3} = \left( {d - 0.5} \right) \\ & d_{4} = \left( {1 - d} \right). \\ \end{aligned} $$
(56)

State space modeling of the proposed DC-DC converter is written as:

$$ \begin{aligned} \left[ {\begin{array}{*{20}c} {\dot{i}_{L1} (t)} \\ {\dot{i}_{L2} (t)} \\ {\dot{v}_{C1} (t)} \\ {\dot{v}_{C2} (t)} \\ {\dot{v}_{O} (t)} \\ \end{array} } \right] & = \left[ {\begin{array}{*{20}c} 0 & 0 & {\frac{ - 1}{{L_{1} }}\left( {\frac{2d - 1}{4}} \right)} & 0 & 0 \\ 0 & 0 & {\frac{ - 1}{{L_{1} }}\left( {\frac{2d - 1}{4}} \right)} & 0 & 0 \\ {\frac{1}{{C_{1} }}\left( {\frac{2d - 1}{2}} \right)} & 0 & 0 & 0 & {\frac{2}{{RC_{1} }}\left( {1 - d} \right)} \\ {\frac{ - 1}{{C_{2} }}\left( {2d - 1} \right)} & {\frac{ - 1}{{C_{2} }}\left( {2d - 1} \right)} & 0 & 0 & {\frac{2}{{RC_{2} }}\left( {1 - d} \right)} \\ {\left( {2d - 1} \right)\left( {\frac{ - 1}{{C_{2} }} + \frac{1}{{2C_{1} }}} \right)} & {\frac{ - 1}{{C_{2} }}\left( {2d - 1} \right)} & 0 & 0 & {\left( {1 - d} \right)\left( {\frac{1}{{RC_{1} }} + \frac{1}{{RC_{2} }}} \right)} \\ \end{array} } \right]\left[ \begin{gathered} i_{L1} (t) \hfill \\ i_{L2} (t) \hfill \\ v_{C1} (t) \hfill \\ v_{C2} (t) \hfill \\ v_{O} (t) \hfill \\ \end{gathered} \right] \\ & \quad + \;\left[ {\begin{array}{*{20}c} {\frac{1}{{L_{1} }}\left( {\frac{1 + 2d}{4}} \right)} & 0 \\ {\frac{1}{{L_{2} }}\left( {\frac{1 + 2d}{4}} \right)} & 0 \\ 0 & 0 \\ 0 & {\frac{1}{{C_{2} }}\left( {2d - 1} \right)} \\ 0 & {\frac{1}{{C_{2} }}\left( {2d - 1} \right)} \\ \end{array} } \right]\left[ \begin{gathered} V_{S} (t) \hfill \\ i_{1} (t) \hfill \\ \end{gathered} \right] \\ \end{aligned} $$
(57)
$$ y(t) = v_{o} (t) = \left[ {\begin{array}{*{20}c} 0 & 0 & 0 & 0 & 1 \\ \end{array} } \right]\left[ \begin{gathered} i_{L1} (t) \hfill \\ i_{L2} (t) \hfill \\ v_{C1} (t) \hfill \\ v_{C2} (t) \hfill \\ v_{O} (t) \hfill \\ \end{gathered} \right]. $$
(58)

Experimental results

To prove the validity of the proposed converter, it is tested on the laboratory hardware platform as shown in Fig. 5. The schematic diagram of the experimental system is shown in Fig. 6. For experimental analysis, the converter parameters are listed in Table 1.

Figure 5
figure 5

Experimental set up of the proposed converter.

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Figure 6
figure 6

A schematic diagram of the experimental system.

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Table 1 Converter component specifications for experimental test.
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Open loop performance

Figures 7, 8, 9 and 10 show the experimental waveforms of the proposed converter at duty cycle 0.4. These figures include the resulted waveforms of the gate signal of switches SW1 and SW2, the input and output voltages, the input current, the voltage across the capacitors, and the voltage-current of the switches, diodes, and inductors. Figure 7a shows the gate pulses of SW1 and SW2. The input voltage supplied from PV is shown in Fig. 7b and equal to 24 V. It can be seen from Fig. 7c that the output voltage equals to 226 V which gives a gain of 9.4. This performance proves that the proposed converter gives a high voltage gain at reasonable duty cycle. Figure 7d shows the continuous input current waveform. As shown in Fig. 7e,f, both the voltage of the capacitors is equal and has an average value of 125 V that is equal to 55.3% of output voltage. That ensures a low voltage stress of the capacitors, and it also achieves the Eq. (7). As shown from Fig. 8a,b, the maximum voltage across each switch (SW1 or SW2) is almost equal to 57.5% of the output voltage which shows a low voltage stress for all switches. Furthermore, all switches operate in soft switching mode (ZCS) that decrease the switching losses of the switches. Moreover, from Fig. 9, the absolute maximum voltages across diodes D1, D2, D3, D4, D5, and D6 and across diodes D7 and D8 are almost equal to 39.8% and 53.1% of the output voltage, respectively which show a low voltage stress for all diodes. Also, all diodes operate in soft switching mode (ZCS) that decrease the diodes losses.

Figure 7
figure 7

Experimental waveforms of the proposed converter. Part I. (a) Gate signals of switches, (b) Input voltage, Vs, (c) Output voltage, Vo, (d) Input current, Is, (e) Voltage of capacitor C1, and (f) Voltage of capacitor C2.

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Figure 8
figure 8

Experimental waveforms of the proposed converter. Part II. (a) Voltage–Current of switch SW1, and (b) Voltage–Current of switch SW2.

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Figure 9
figure 9

Experimental waveforms of the proposed converter. Part III. (a) Voltage–Current of diode D1, (b) Voltage–Current of diode D2, (c) Voltage–Current of diode D3, (d) Voltage–Current of diode D4, (e) Voltage–Current of diode D5, (f) Voltage–Current of diode D6, (g) Voltage–Current of diode D7, and (f) Voltage–Current of diode D8.

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Figure 10
figure 10

Experimental waveforms of the proposed converter. Part IV. (a) Voltage–Current of inductor L1, (b) Voltage–Current of inductor L2, (c) Voltage–Current of inductor L3, and (d) Voltage–Current of inductor L4.

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The inductor current (iL) is discontinuous as seen in Fig. 10 which shows that the converter is operating in DCM as mentioned before. Figure 11 shows the experimental measured efficiency of the proposed converter, in which it ascertains a high efficiency of the proposed topology. The maximum overall efficiency equals 93% measured at 120 W load. Figure 12 shows the voltage gain versus duty cycle of the theoretical equation, simulation results, and experimental results. It can be concluded that the experimental results are in good agreement with the theoretical analysis (Equation-14), and simulation results. From the previous experimental results, the proposed converter provides a high voltage gain with a low duty cycle, and it has small voltage stress of all semiconductor devices. Furthermore, a continuous input current is attained which a desirable feature of the DC/DC converter is making it suitable for PV applications. Therefore, it has low switching losses without any additional circuits. Also, it has components with a low nominal rating that makes the proposed converter small size, low price, and high overall efficiency. The aforementioned advantages make the proposed converter suitable for numerous industrial applications.

Figure 11
figure 11

Experimental measured efficiency of the proposed converter.

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Figure 12
figure 12

Voltage gain versus duty cycle of the proposed converter.

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Closed loop performance

To examine the performance of the proposed converter under closed-loop control, the OWON TDS8204 oscilloscope and DSP1104 are used to record the results. PI controller is also used for control. The parameters for the PI controller are KP = 0.38 and KI = 200. A schematic diagram of the circuit that is used to control the output voltage of the proposed circuit is shown in Fig. 13. First, the proposed converter is tested by changing the reference voltage (increased/decreased) by 100 V. It can be seen from Fig. 14 that the output voltage of the proposed converter responds to the step change (increase/decrease) of the reference voltage and changes from 100 to 200 V and then from 200 to 100 V according to the value of reference voltage. Also, the transient period is found very small and less than 200 ms. Second, the proposed converter is tested by changing the input voltage source (increase/decrease) by 4 V. It can be seen from Figs. 15 and 16 that the output voltage value is remaining constant at the reference voltage value of 150 V. Also, the overshoot value is less than 7.5 V, and it is equal to 5% of the output voltage. Finally, the proposed converter is tested for variation in load values. The response to the step change (increase/decrease) in load is shown in Fig. 17. The converter is operating at 65% of full load. At first, the load increased by 35% of full load value to make the converter operate at full load, and then the load decreased by 35% of full load value to make the converter operate at 65% of the full load again. It is evident from the figure that the proposed converter operates at constant output voltage under load changes.

Figure 13
figure 13

A schematic diagram of the control circuit used.

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Figure 14
figure 14

Experimental step change (increase/decrease) in reference voltage.

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Figure 15
figure 15

Experimental response to step increasing in input voltage.

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Figure 16
figure 16

Experimental response to step decreasing in input voltage.

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Figure 17
figure 17

Experimental response to step change (increase/decrease) in load value.

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Comparison of the proposed converter with recent converters

The proposed converter is compared with SL-Boost, single-active switch, non-inverting, SL-DS-DC, cascaded boost, SC/SL-SBC, double boost fly back, and ZSC converters. For a valid comparison, coupled inductor turns ratio (n) of the double boost-fly back converter was set to unity. The comparison results are presented in Table 2. The voltage gain comparison is presented in Fig. 18. It is clear that the proposed converter can operate with a wide range of duty cycle while the SL-DS-DC, and SC/SL-SBC converters operate only up to 0.3 duty cycle, and ZSC operates up to 0.5 duty cycle. Furthermore, the proposed converter has a higher gain at most of the duty cycle in comparison with SL-boost, single-active switch, cascaded boost, SC/SL-SBC, double boost fly back, and ZSC converters except SL-DS-DC converter that have the highest gain up to 0.3 only and the non-inverting converter. For the number of passive and active components, the proposed converter shows a modest number of active and passive components in comparison with SL-boost, single-active switch, non-inverting, SL-DS-DC, double boost fly back, and SC/L-SBC converters except cascaded boost and ZSC converters that have the lower components counts. However, they (cascaded boost and ZSC converters) operate at a larger duty cycle which may produce saturation problems in the inductor current or core. All the converters operate in continuous input current except the SL-boost, and ZSC converters. Also, the double boost fly back converter presents a discontinuous input current if it operates at a duty cycle of less than 0.5. The current ripple is low and within the allowed limit for all converters except the ZSC converter. Also, all converters operate with hard switching except the proposed converter that operates in soft switching for all semiconductor devices which makes lower losses and higher efficiency at higher gains. The switch voltage stress comparison is shown in Fig. 19. The proposed converter has a lower maximum switch voltage stress if it compared with all the converters except the single-active switch converter which has the smallest switch voltage stress. A lower switch voltage stress makes the losses lower and selecting a low nominal rating of switches that makes the converter small size, low price, and high overall efficiency. The capacitor voltage stress comparison is shown in Fig. 20. The proposed converter has a lower capacitor voltage stress if it compared with single-active switch, SL-DS-DC, SC/SL-SBC, and ZSC converters. A lower capacitor voltage stress gives a benefit of choosing a low nominal rating of capacitors that makes the converter smaller in size, and hence lower price. The output diode voltage stress is compared as shown in Fig. 21. The diode voltage stress of the proposed converter is lower than all the converters except the single-active switch converter. Lower voltage stress of output diode makes the nominal rating of diode much lower which affects the converter size and price. The efficiency of the proposed converter is reasonable compared to the other converters except for the cascaded boost converter which has the highest efficiency. However, the cascaded boost converter cannot accomplish a higher gain due to parasitic. Alternatively, a single-active switch converter has low voltage gain although it has similar elements count as the proposed converter. Theoretically, the converter power density depends on the number of semiconductor devices and the volume of the passive components. As known, the volume of passive components is proportional to the energy stored in them. So, if the stored energy is computed, then the volume of the passive components can be estimated. The total energy stored for the inductor is calculated by

$$ E_{L} = 0.5*L*({\text{i}}_{{L{ - }av}} )^{2} $$

where iL-av is average current through the inductor L, and the total energy stored for the capacitor is given as

$$ {\text{E}}_{{\text{C}}} = 0.{5}*C*\left( {V_{{\text{C}}} } \right)^{{2}} $$

where VC is voltage through the capacitor C.

Table 2 Comparison of proposed converter with recent converters.
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Figure 18
figure 18

Voltage gain comparison.

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Figure 19
figure 19

Switch voltage stress comparison.

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Figure 20
figure 20

Capacitor voltage stress comparison.

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Figure 21
figure 21

Output diode voltage stress comparison.

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While evaluating the energy stored in the inductor, it is assumed that the frequency and ripple currents are the same for all the compared converters. Furthermore, the energy stored in the capacitor is computed for a similar value of capacitances.

For voltage gain, G = 5, the total energy stored in the inductor and capacitor for all the converters is recorded in Table 2. It is obvious that the total energy stored, i.e., volume required is modest in the proposed topology (38). The double boost flyback converter is the smallest (27), however it has minimal voltage gain. The quantity of energy stored in inductors and capacitors that mentioned in Table 2 is made to be unitless.

Based on the previous various performance parameters and characteristics comparison, the proposed converter gives a high voltage gain at a low duty cycle. It has a modest number of semiconductor devices with low voltage stress and hence small nominal voltage rating, and lower losses making the converter smaller in size, higher efficiency, and has a good performance. According to these comparisons, the proposed converter is considered a strong competitor to the other converters.

Conclusion

In this paper, a new non-isolated high voltage gain DC/DC converter by integrating a dual boost converter with a switched inductor structure is proposed. The proposed converter operates with a modest duty cycle (less than 0.5) with a continuous input current. The converter operates with a soft switching (ZCS) for all diodes and switches which plays an important role in reducing the losses. A wide operating range of the duty cycle is available. An equal current sharing among boost inductors makes it easy to control. Also, the proposed converter offers high efficiency due to the low switching losses, lower voltage stress for all passive and active components, and the lack of reverse recovery loss on diodes. It requires a small inductor, and a small nominal rating for all semiconductor devices which reduces the size, weight, and price of the proposed converter. These features make the converter a good choice for many applications such as PV, x-ray, fuel cells, etc. Moreover, the description, operating modes in DCM, design guidelines, and open and closed-loop performance are presented. Besides, a comparative analysis with recent converters is presented. The converter is examined at various power ratings for efficiency analysis and maximum efficiency of 93% is achieved. Experimental results in open and closed-loop prove the good performance of the proposed converter.