A nanoscale photonic thermal transistor for sub-second heat flow switching

Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VOx)-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.


Supplementary Note 2. Fabrication of gate device
The fabrication process for the gate device is illustrated in Supplementary Figure 2. A p-doped double-bonded silicon-on-insulator (SOI) wafer (Ultrasil LLC) with a 20 ± 1 μm-thick top layer, 40 ± 1 μm-thick middle layer, 400 ± 5 μm-thick substrate, and two 1 μm-thick buried oxide layers (BOX) is chosen (Step 1).The specified resistivity of both the top and middle layers is < 0.02 Ω cm.BOX layers are used as etch stops to fabricate the suspended gate device.The top device layer is patterned and etched to form a 16 µm-tall mesa using a deep reactive ion etching (DRIE) process (Step 2).The ~4 μm-tall silicon serpentine structure is then patterned using standard lithographic techniques and etched using DRIE (Step 3).Next, a 200 nm-thick gold layer is deposited to form electrical contacts and patterns formed using a lift-off process (step 4).Note that Ti/Pt (10/30 nm) are deposited (not illustrated in step 4) underneath the Au for better contact.The device beams and the structure are patterned and etched from the top using the DRIE process (Step 5).The Si handle layer, two BOX layers, and Si middle layer are etched away from the back side of the device to release the suspended beam structure using the DRIE processes (Step 6).Subsequently, a layer of Al2O3 with a thickness of 10 nm was deposited onto the gate device using atomic layer deposition, serving the purpose of creating an electrically insulating layer (Step 7).Finally, a 150 nm-thick VOx is deposited on the mesa as a phase transition material, followed by annealing at 350 ℃ for 5 min under an N2 atmosphere (Step 8).Supplementary Figure 2. Fabrication process for the gate device.

Supplementary Note 3. Deposition of vanadium oxide (VOx) thin film
In this study, we grew a VOx thin film on a gate device by physical vapor deposition (PVD) using a DC-pulsed magnetron sputtering process in a LAB18 sputtering system (Kurt J. Lesker Company) using a 99.9% pure vanadium target with a diameter of 3 inches and a thickness of 0.125 inches.The substrate temperature was maintained at room temperature.In the process, the DC power was set to 180 W, and both argon and oxygen were introduced into the chamber at flow rates of 48.5 sccm and 1.5 sccm, respectively.The sputtering rate of the VOx thin film was determined to be approximately 5 nm/min by measuring the thickness of the as-deposited film.Subsequently, the sputtered VOx thin film underwent annealing at 350 ℃ for 5 minutes under an N2 ambient environment using the Jetfirst 150 RTP tool.
To evaluate the resistance of the VOx thin film, a 150 nm-thick film was deposited on a silicon substrate.The resistance of the VOx film was measured during the heating and cooling process, and the results are presented in Supplementary Figure 3.The observed hysteresis during the phase transition is attributed to the strain, doping, and lattice defects inside the deposited VOx thin film 2 .Supplementary Figure 3. Resistance characteristics of a VOx film deposited on a bare Si as a function of the substrate temperature.

Supplementary Note 4. Effect of Si thickness on gate device in the SCUFF-EM model.
To support the choice of a 10 µm-thick Si gate for the radiative conductance and Poynting flux calculations presented in Figures 2d and 4 of the main manuscript, we examined the effect of the gate thickness on our SCUFF-EM calculations.We began by creating models with three different gate thicknesses: 5 µm, 10 µm, and 15 µm, all made from doped Si, while maintaining the source and drain SiN membranes at 80 µm long, 60 µm wide, 250 nm thick, and separated by 20 µm.All three gates were coated with 150 nm of VOx on all sides.The three cases are schematically shown in Supplementary Figures 4a−c below.
We then computed the radiative conductance between the source and drain membranes.The gap of the gate to the source and drain SiN membranes was calculated for gap sizes (d) ranging from d = 1 µm to d = 25 µm, with the VOx layer covering the whole surface of Si gate.Supplementary Figure 4d and Supplementary Figure 4e display the results of the gap-dependent radiative conductance at three different gate thicknesses when VOx layer is in the insulating and metallic phases, respectively.Results indicate that the radiative conductance is independent of the Si gate thickness, specifically within the range of 5 µm to 15 µm.This implies that the VOx layer at the bottom of the gate plays little to no role in the heat flow between source and drain when the Si thickness of the gate is 5-15 µm.Consequently, choosing a 10 µm thick Si gate with VOx covered on all sides serves as a representative model for our experiments.Note that, in our experiments, only the top surface of the Si gate is covered by the VOx thin film.We have excluded the consideration of the VOx film on the sides in this argument, as we believe it plays a negligible role in the heat flow.

Supplementary Note 5. Electrical characteristics of the source and drain devices
To characterize the thermal properties of the source and drain devices, we employed two half-Wheatstone bridges, as shown in Supplementary Figure 5a.An alternating current (IAC) was applied to the half-Wheatstone bridge.A potentiometer, Rmat, was connected in series with the Pt serpentine line integrated into the device (RS for source and RD for drain) to balance the circuit.To characterize the thermal conductance of the source and drain devices, we used two-stage amplification with a gain of 1 for all three instrumentation amplifiers (AD524) to achieve a good common mode rejection.The output of the circuit was continuously monitored during the experiment using a lock-in amplifier (SR 830, Stanford Research System).
We first characterized the electrical properties of the Pt resistance thermometer integrated into the source device.The source was placed on the cold finger of the cryostat (Janis ST-100), whose temperature was controlled by the Lakeshore 335 temperature controller under a vacuum level of less than 10 -3 Torr.At each temperature, the resistance of the Pt serpentine was measured by applying an alternating current (IAC = 1 µA) through the serpentine at a frequency of 101 Hz using a Keithley 6221 current source, ensuring negligible self-heating.At the same frequency (101 Hz), the voltage (Vf) across the Pt resistance thermometer (PRT) was measured using a four-probe scheme with an SR830 lock-in amplifier to determine the resistance.The measured resistance within the temperature range of 299 K to 310 K is shown in Supplementary Figure 5b, and the measured slope (dR/dT) was found to be 29.50 ± 0.138 Ω/K with good linearity for small temperature differences.The corresponding TCR was calculated as 1.75×10 -3 K -1 using the expression: α =(1/R)×dR/dT (measured resistance of the source device is ~16.857kΩ at 25 ℃).
Next, we measured (Gbeams) the thermal conductance of the source device using a 3ω-measurement method by applying a sinusoidal current with a fixed frequency of 1 Hz to the platinum resistor of the source device.The current amplitude (IAC) is adjusted in steps (using Keithley 6221), ranging from 6 µA to 12 µA, to generate a temperature modulation at 2 Hz.To measure the temperature change, the corresponding V3f was measured using an SR830 lock-in amplifier while various IAC were applied.The resulting temperature change (∆T2f) of the source device is calculated using the following equation: Supplementary Figure 5c illustrates the power dissipation at the PRT (Q2f=IAC 2 R/2) as a function of temperature rise on the source.A clear linear correlation is observed in the examined temperature range.The slope of this line corresponds to the beam thermal conductance of the source device, which is measured to be 250 ± 3 nW/K.For the drain device, electrical characteristics are almost identical to those of the source device since they were fabricated under the exact same procedure.Using the same method employed for measuring the beam thermal conductance of the source device, the measured beam conductance of the drain is determined to be 249 ± 2 nW/K.We note that Gbeams is almost identical to GTh when the gap size between the gate device and the top device is large but these two quantities differ from each other for smaller gaps.

Figure 4 .
Demonstration of gate thickness independence for SCUFF-EM calculations.a, Schematic of the model used in the calculations.b, Same as case a, but with the doped Si gate thickness changed to 10 µm.c, Same as case a but with the doped Si gate thickness changed to 15 µm.d, Radiative conductance calculation for cases a, b, and c with VOx in the insulating phase.e, Same as d, but with VOx in metallic phase.

Figure 5 .
Characterization of the electrical and thermal properties of the source device.a, Schematic of the electronic circuit used to measure temperature changes by monitoring resistance change.b, The measured temperature dependence of the integrated Pt resistor near room temperature.c, The relationship between temperature rise on the source device and the power dissipation, produced by the Pt heater, is illustrated.The measured beam conductance is represented by the slope of the red solid line.Supplementary Figure 7. Illustrations from FEM simulations were performed to estimate Gblackbody.a, Top view of the suspended device geometry as modeled in COMSOL.SiN membrane is dark green, Pt is light gray.b, Discretization mesh on the suspended membrane structures.c, The complete geometry used in the simulation, including the VOx-covered substrate of the gate, is shown in purple.d, Computed surface temperatures of the source membrane and drain membrane.