Abstract
Software based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper we propose an efficient methodology for processor core self-testing based on the knowledge of its instruction set architecture and register transfer level description and we demonstrate it on a processor core benchmark. We also demonstrate that our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while the same fault coverage is achieved with an order of magnitude smaller test application time compared with a recently published structural methodology for processor core self-testing.
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Kranitis, N., Paschalis, A., Gizopoulos, D. et al. Instruction-Based Self-Testing of Processor Cores. Journal of Electronic Testing 19, 103–112 (2003). https://doi.org/10.1023/A:1022873120308
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DOI: https://doi.org/10.1023/A:1022873120308