Skip to main content
SpringerLink
Log in

Limitations of the MOS Resistive Circuit in MOSFET-C Implementation: Bandwidth, Noise, Offset and Non-Linearity

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

Significant departures between predicted behaviour and actual performance are observed in opamp based structures containing the so-called MOS Resistive Circuit. In this paper we demonstrate that the usual description of this cell by a simple model of two tunable resistors is not adequate enough to properly describe the MRC operation. A more complete, still simple model is proposed and shown to work by means of some examples. The model is used to characterise and predict the effects that the limited gain and offset of the opamp induces in the MRC operation, increasing the distortion, the expected noise and the output DC offset, and reducing the bandwidth of the system. Finally we give some design guidelines for the optimum application of the MRC.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Czarnul, Z., “Novel MOS resistive circuit for synthesis of fully integrated continuous-time filters.” IEEE Transactions on Circuits and Systems CAS-33(7), pp. 718-721, 1986.

    Google Scholar 

  2. Ismail, M., Smith, S. V. and Beale, R. G., “A new MOSEFT-C universal filter structure for VLSI.” IEEE J. Solid-State Circuits SC-23(1), pp. 183-194, February 1988.

    Google Scholar 

  3. Geiger, R. L., Allen, P. L. and Strader, N. R., VLSI Design Techniques for Analog and Digital Circuits. McGraw Hill Publishing Company, ISBN 0-07-023253-9, 1990.

  4. Czarnul, Z., Fang, S. C. and Tsividis, Y., “Conversion of certain RC-active networks to MOSFET-C integrated structures.” In Proceedings of the 29th Midwest Symposium on Circuits and Systems, pp. 196-199, 1987.

  5. Ismail, M., Smith, S. V. and Beale, R. G., “A new MOSFET-C universal filter structure for VLSI.” IEEE Journal of Solid-State Circuits SC-23(1), pp. 183-194, 1988.

    Google Scholar 

  6. Han, G. and Sanchez-Sinencio, E., “CMOS transconductance multipliers: A tutorial.” IEEE Transactions on Circuits and Systems II 45(12), 1998.

  7. Osa, J. I., Porta, S. and Carlosena, A., “The most resistive model for the MOS resistive circuit.” IEEE International Symposium on Circuits and Systems, Monterey, CA, 1998.

  8. Toth, L., Efthivoulidis, G., Gopinathan, V. and Tsividis, Y., “General results for resistive noise in active RC and MOSFETC filters.” IEEE Transactions on Circuits and Systems-II CAS-42(12), pp. 785-793, 1995.

    Google Scholar 

  9. Papananos, Y., Georgantas, T. and Tsividis, Y., “Design considerations and implementation of very low frequency continuoustime CMOS monolithic filters.” IEE Proceedings on Circuits, Devices and Systems 144(2), pp. 68-74, 1997.

    Google Scholar 

  10. Carlosena, A. and Cabral, E., “Novel transimpedance filter for instrumentation.” IEEE Trans. on Instrumentation and Measurement 46(4), pp. 862-867, November 1997.

    Google Scholar 

  11. Osa, J. I. and Carlosena, A., “MOSFET-C sinusoidal oscillator with variable frequency and amplitude.” IEEE International Symposium on Circuits and Systems, May 2000, Geneve, Switzerland.

  12. Osa, J. I., Carlosena, A. and López-Martín, A. J., “Phase locked loop design for on-chip tuning applications.” Electronics Letters 36(8), 699-701, April 2000. 252 Osa and Carlosena

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Dpto: Ingeniería Eléctrica y Electrónica, Universidad Pública de Navarra., Campus Arrosadía s/n, 31006, Pamplona, Spain

    Juan. I. Osa & Alfonso Carlosena

Authors
  1. Juan. I. Osa
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Alfonso Carlosena
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Osa, J.I., Carlosena, A. Limitations of the MOS Resistive Circuit in MOSFET-C Implementation: Bandwidth, Noise, Offset and Non-Linearity. Analog Integrated Circuits and Signal Processing 28, 239–252 (2001). https://doi.org/10.1023/A:1011251910102

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1011251910102

Search

Navigation