Skip to main content
Log in

A Methodology to Implement Real-Time Applications onto Reconfigurable Circuits

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

This paper presents an extension of the AAA rapid prototyping methodology for the optimized implementation of real-time applications onto reconfigurable circuits. This extension is based on an unified model of factorized data dependence graphs as well to specify the application algorihtm, as to deduce the possible implementations onto reconfigurable hardware. This is formalized in terms of graphs transformations. This seamless transformation flow has been implemented in a CAD software tool called SynDEx-IC.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. A. F. Dias, M. Akil, Y. Sorel, and C. Lavarenne. Vers la synthèse automatique de circuits ‡ partir de graphes algorithmiques factorisés. Conf. AAA'2000, Inria Rocquencourt, Janvier 2000.

  2. A. F. Dias, C. Lavarenne, M. Akil, and Y. Sorel. Optimized implementation of real-time image processing algorithms on field programmable gate arrays. In Proc. of the 4th Intl. Conference on Signal Processing, Beijing, Oct. 1998.

  3. S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. In Proceedings of IEEe, 85(3), 1997.

  4. T. Grandpierre, C. Lavarenne, and Y. Sorel. Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors. CODES'99 7th Intl. Workshop on Hardware/Software Co-Design, Rome, May 1999.

  5. T. Grandpierre and Y. Sorel. From algorithm and architecture specifications to automatic generation of distributed real-time executives: A seamless flow of graphs transformations. First ACM& IEEE Intl. Conference on formal methods and models for codesign. MEMOCODE'03, Mont Saint-Michel, France, june 2003.

  6. S. Gupta, N. Dutt, R. Gupta, and A. Nicolau. SPARK, high-level synthesis framework for applying parallelizing compiler transformations. Intl. Conf. on VLSI Design, January 2003, Mumbai, India.

  7. R. lauwereins, M. Engels, M. Ad, and J. Peperstraete. Grape-II: A system-level prototyping environment for DSP applications. IEEE Computer, 28(2):35–43, 1995.

    Google Scholar 

  8. P. Lieverse, P. van detr Wolf, Ed Deprettere, and K. Vissers. A methodology for architecture exploration of heterogeneous signal processing systems. In Proc. 1999 IEEE Worshop on Signal Processing Systems (SiP'99).

  9. C. A. Mead and L. A. Conway. Introduction to VLSI Systems. s.l.: Ed. Addison-Wesley, 1980.

  10. M. Meerwein, C. Baumgartner, and W. Glauert. Linking codeisgn and reuse in embedded systems design. In Proceeding of the 8 Intl Workshop on Hardware/Software Codesign (CODES/CASHE), San Diego, California, USA, 3–5 May 2000.

  11. R. Vodisek, M. Akil, S. Gailhard, and A. Zemva. Automatic Generation of VHDL code for SynDEx v6 software. Electro technical and Computer Science conference, Portoroz, Slovenia, september 2001.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kaouane, L., Akil, M., Grandpierre, T. et al. A Methodology to Implement Real-Time Applications onto Reconfigurable Circuits. The Journal of Supercomputing 30, 283–301 (2004). https://doi.org/10.1023/B:SUPE.0000045213.82276.8e

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/B:SUPE.0000045213.82276.8e

Navigation