Skip to main content
SpringerLink
Log in

Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of high-level language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixed-point DSPs. The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases. In contrast to earlier works, mainly based on heuristics, our approach is constraint-based. An initial set of constraints on code generation are prescribed by the given processor model. Further constraints arise during code generation based on decisions concerning code selection, register allocation, and scheduling. Whenever possible, decisions are postponed until sufficient information about a good decision has been collected. The constraints are active in the "background" and guarantee local satisfiability at any point of time during code generation. This mechanism permits to simultaneously cope with special-purpose registers and instruction level parallelism. We describe the detailed integration of code generation phases. The implementation is based on the constraint logic programming (CLP) language ECLiPSe. For a standard DSP, we show that the quality of generated code comes close to hand-written assembly code. Since the input processor model can be edited by the user, also retargetability of the code generation technique is achieved within a certain processor class.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Wolfgang Ambrosch, Anton Ertl, Felix Beer, and Andreas Krall. Dependence conscious register allocation. In Juergen Gutknecht, editor, Programming Languages and System Architectures, volume 782, pages 125-136. LNCS Series, Springer-Verlag, Zurich, Switzerland, March 1994.

    Google Scholar 

  2. Alfred V. Aho, Mahadevan Ganapathi, and Steven W. K. Tjiang. Code generation using tree matching and dynamic programming. ACM Transactions on Programming Languages and Systems, 11(4):491-516, October 1989.

    Article  Google Scholar 

  3. Alfred V. Aho and S. C. Johnson. Optimal code generation for expression trees. Journal of the ACM, 23(3):488-501, 1976.

    Article  MATH  MathSciNet  Google Scholar 

  4. Guido Araujo and Sharad Malik. Optimal code generation for embedded memory non-homogeneous register architectures. In Intl. Symp. on System Synthesis ISSS'95, 1995.

  5. Guido Araujo, Sharad Malik, and Mike Tien-Chien Lee. Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. In 33rd Design Automation Conference (DAC). 1996.

  6. Alfred V. Aho, R. Sethi, and J.D. Ullman. Compilers: Principles, Techniques and Tools. Addison-Wesley, New York, 1986.

    Google Scholar 

  7. Preston Briggs, Keith D. Cooper, and Linda Torczon. Improvements to graph coloring register allocation. ACM Transactions on Programming Languages and Systems, 16(3):428-455, May 1994.

    Article  Google Scholar 

  8. A. Balachandran, D.M. Dhamdere, and S. Biswas. Efficient Retargetable Code Generation Using Bottom-Up Tree Pattern Matching. Comput. Lang. vol. 15,no. 3, 1990.

  9. David G. Bradlee, Susan J. Eggers, and Robert R. Henry. Integrating register allocation and instruction scheduling for RISCs. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 122-131, Santa Clara, California, 1991.

  10. David A. Berson, Rajiv Gupta, and Mary Lou Soffa. Resource spackling: A framework for integrating register allocation in local and global schedulers. Working Conf. on Parallel Architectures and Compilation Techniques, August 1994.

  11. David G. Bradlee, Robert R. Henry, and Susan J. Eggers. The Marion system for retargetable instruction scheduling. SIGPLAN Notices, 26(6):229-240, June 1991. Proceedings of the ACM SIGPLAN '91 Conference on Programming Language Design and Implementation.

    Article  Google Scholar 

  12. David G. Bradlee. Retargetable instruction scheduling for pipelined processors. PhD Thesis 91-08-07, Dept. of Computer Science, Univ. of Washington, 1991.

  13. Thomas S. Brasier and Phillip H. Sweany. Craig: A practical framework for combining instruction scheduling and register assignment. In PACT'95, Limassol, Cypros, 1995.

  14. G.J. Chaitin, M.A. Auslander, A.K. Chandra, J. Cocke, M.E. Hopkins, and P.W. Markenstein. Register allocation via coloring. Computer Languages, 6(1):47-57, January 1981.

    Article  Google Scholar 

  15. Ron Cytron, Jeanne Ferrante, Barry K. Rosen, Mark N. Wegman, and Kenneth F. Zadeck. Efficiently computing the static single assignment and the control dependence graph. ACM Transactions on Programming Languages and Systems, 13(4):451-490, October 1991.

    Article  Google Scholar 

  16. Analog Devices. ADSP-2101 User's Manual. Analog Devices, 1991.

  17. J.R. Ellis. Bulldog: A compiler for vliw architectures. The MIT Press, Cambridge, Mass., 1986.

    Google Scholar 

  18. Helmut Emmelmann, Friedrich-Wilhelm Schröer, and Rudolf Landwehr. BEG — A generator for efficient back ends. SIGPLAN Notices, 24(7):227-237, July 1989. Proceedings of the ACM SIGPLAN '89 Conference on Programming Language Design and Implementation.

    Article  Google Scholar 

  19. Andreas Fauth, G. Hommel, A. Knoll, and C Mueller. Global code selection for directed acyclic graphs. In Peter A. Fritzson, editor, Compiler Construction, volume 786 of LNCS, pages 128-141. Springer-Verlag, Eddinburgh, U.K., April 1994. 5'th International Conference, CC'94.

    Google Scholar 

  20. C. Fraser, R. Henry, and Todd A. Proebsting. Engineering a Simple, Efficient Code-Generator Generator. ACM Letters on Programming Languages and Systems, 1(3):213-226, September 1992.

    Article  Google Scholar 

  21. C. Fraser, R. Henry, and Todd A. Proebsting. BURG — fast optimal instruction selection and tree parsing. SIGPLAN Notices, 27(4):68-76, April 1992.

    Article  Google Scholar 

  22. Stefan M. Freudenberger and John C. Ruttenberg. “Phase Ordering of Register Allocation and Instruction Scheduling”. In Robert Giegerich and Susan L. Graham, editors, “Code Generation — Concepts, Tools, Techniques”, Proceedings of the International Workshop on Code Generation, Dagstuhl, Germany, 20–24 May 1991, Workshops in Computing, pages 146-172. Springer-Verlag, 1991. ISBN 3-540-19757-5 and 3-387-19757-5.

  23. Christian Ferdinand, Helmut Seidl, and Reinhard Wilhelm. Tree automata for code selection. Acta Informatica,Springer-Verlag, pages 741-760, 1994.

  24. C.H. Gebotys. An Efficient Model for DSP Code Generation:Performance, Code Size, Estimated Energy. In 10th International Symposium on System Synthesis (ISSS). 1997.

  25. Mahadevan Ganapathi, C.N. Fisher, and J.L. Hennessy. Retargetable compiler code generation. Computing Surveys, 14(4), October 1982.

  26. J. Goodman and W. Hsu. Code scheduling and register allocation. In Proceedings of the ACM SIGPLAN '88 Conference on Programming Language Design and Implementation, 1988.

  27. S.L. Graham and R.S. Glanville. A new method for compiler code generation. Conference Record of the Fifth Annual ACM Symposium on Principles of Programming Languages, pages 231-240, 1977.

  28. R. Hartmann. Combined scheduling and data routing for programmable asic systems. In Proceedings of EDAC'92, pages 486-490, March 1992.

  29. Werner Heinrich. Formal Desciption of Parallel Computer Architectures as a Basis of Optimizing Code Generation. PhD thesis, TU Munich, 1993.

  30. R. Henry. Algorithms for Table-Driven Code Generators Using Tree Pattern Matching. Technical Report 89-02-03, Computer Science Department, University of Washington, Seattle, WA 98195 USA, 1989.

    Google Scholar 

  31. R. Henry. Encoding Optimal Pattern Selection in a Table-Driven Bottom-Up Tree Pattern Matcher. Technical Report 89-02-04, Computer Science Department, University of Washington, Seattle, WA 98195 USA, 1989.

    Google Scholar 

  32. R. Henry. Performance of Table-Driven Code Generators Using Tree Pattern Matching. Technical Report 89-02-02, Computer Science Department, University of Washington, Seattle, WA 98195 USA, 1989.

    Google Scholar 

  33. Pascal Van Hentenryck. Constraint Satisfaction in Logic Programming. The MIT Press, 1989.

  34. Silvina Hanono, George Hadjiyiannis, and Srinivas Devadas. Aviv: A Retargetable Code Generator Using ISDL. In Proc. 34th DAC'97, 1997.

  35. Dirk Lanner, Marco Cornero, Gert Goossens, and Hugo De Man. Data routing: a paradigm for efficient data-path synthesis and code generation. In Proc. 7th IEEE/ACM Int. Symp. on High-Level Synthesis, May 1994.

  36. Stan Liao, Srinivas Devadas, Kurt Kreuzer, and Steve Tjiang. Instruction Selection Using Binate Covering for Code Size Optimization. International Conference on CAD (ICCAD), 1995.

  37. Rainer Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997.

  38. R. Leupers and P. Marwedel. Algorithms for Address Assignment in DSP Code Generation. ICCAD, 1996.

  39. R. Leupers and P. Marwedel. Time-Constrained Code Compaction for DSPs. IEEE Transactions on VLSI Systems, vol. 5,no. 1, 1997.

  40. R. Leupers and P. Marwedel. Retargetable code generation based on structural processor descriptions. In Design Automation for Embedded Systems, vol. 3,no. 1, 1998.

  41. S. Moon and K. Ebcioglu. An efficient resource constraint global scheduling technique for superscalar and vliw processors. In MICRO, December 1992.

  42. Peter Marwedel and Gert Goossens, editors. Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995.

  43. Kim Marriott and Peter J. Stuckey. Programming with Constraints: An Introduction. The MIT Press, 1998.

  44. Bart Mesmann, Adwin H. Timmer, Jef L. van Meerbergen, and G. Jess Jochen A. Constraint Analysis for DSP Code Geberation. In Proc ISSS'97, 1997.

  45. Steven S. Muchnik. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.

  46. Steven Novack and Alexandru Nicolau. Trailblazing: A hierarchical approach to percolation scheduling. Technical Report TR-92-56, Irvine University, August 1993.

  47. Steven Novack and Alexandru Nicolau. Mutation scheduling: A unified approach to compiling for fine-grain parallelism. In K. Pingali, U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua, editors, Languages and Compilers for Parallel Computing, volume 892 of LNCS, pages 16-30. Springer-Verlag, Ithaca,NY,USA, August 1994.

    Google Scholar 

  48. Cindy Norris and L. Pollok. A scheduler-sensitive global register allocator. In Proceedings of Supercomputing '93, 1993.

  49. Cindy Norris and L. Pollok. Register allocation over the program dependence graph. SIGPLAN Notices, 1994. Proceedings of the ACM SIGPLAN '94 Conference on Programming Language Design and Implementation.

  50. Cindy Norris and L. Pollok. Register allocation sensitive region scheduling. In International Conference on Parallel Architectures and Compilation Techniques (PACT'95), 1995.

  51. Alexandru Nicolau, R. Potasman, and H. Wang. Register allocation, renaming and their impact on parallelization. In Languages and Compilers for Parallel Computing, volume 589. LNCS Series, Springer-Verlag, 1991.

  52. IC Parc. Homepage. http://www.icparc.ic.ac.uk/eclipse/.

  53. P. Paulin, M. Cornero, and C. Liem. Trends in Embedded Systems Technology, in: M.G. Sami, G. De Micheli (eds.): Hardware/Software Codesign, An Industrial Perspective. Kluwer Academic Publishers, 1996.

  54. S.S Pinter. Register allocation with instruction scheduling. In Proceedings of the ACM SIGPLAN '93 Conference on Programming Language Design and Implementation, pages 248-257, 1993.

  55. Eduardo Pelegrí-Llopart and Susan L. Graham. Optimal code generation for expression trees: An application of BURS theory. In Conference Record of the Fifteenth Annual ACM Symposium on Principles of Programming Languages, pages 294-308, San Diego, California, January 1988.

  56. P. Paulin, C. Liem, T May, and S. Sutarwala. Flexware: A Flexible Firmware Developement Envirenment for Embedded Systems. In Marwedel and Goossens [42], chapter 4, pages 65-84.

  57. K. Rimey and P.N. Hilfinger. Lazy Data Routing and Greedy Scheduling. In MICRO, volume 21, pages 111-115. 1988.

    Google Scholar 

  58. Marino T.J. Strik, Adwin H. Timmer Jef van Meerbergen, Jochen A.G. Jess, and Stefan Note. Efficient Code Generation for In-House DSP Cores. In Proc. ED&TC'95, 1995.

  59. Adwin H. Timmer, Marino T.J. Strik, Jef L. van Meerbergen, and Jochen A.G. Jess. Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. In Proc. of 32nd DAC, 1995.

  60. S.R. Vegdahl. Local code generation and compaction in optimizing compilers. PhD thesis, Carnegie-Mellon University, Pittsburgh, 1982.

    Google Scholar 

  61. Mark Wallace. Constraint Programming. Contact address: IC-Parc, William Penney Laboratory, Imperial College, London SW7 2AZ, email:mgw@doc.ic.ac.uk, sep 1995. Publications at http://www.icparc.ic.ac.uk/.

  62. T. Wilson, G. Grewal, S Henshall, and D Banerjii. An ILP-Based Approach to Code Generation. In Marwedel and Goossens [42], chapter 6, pages 103-118.

  63. Mark Wallace, Stefano Novello, and Joachim Schimpf. ECLiPSe: A Platform for Constraint Logic Programming. Contact address: IC-Parc, William Penney Laboratory, Imperial College, London SW7 2AZ, email:mgw@doc.ic.ac.uk, aug 1997. Publications at http://www.icparc.ic.ac.uk/.

  64. Masyuki Yamaguchi, Nagisa Ishiura, and Takashi Kambe. Binding and Scheduling Algorithms for Highly Retargetable Compilation. In Proc. ASP-DAC'98, 1998.

  65. V. Zivojnovic, J.M. Velarde, C. Schlaeger, and H. Meyr. DSPStone — A DSP oriented Benchmarking Methodology. In ICSPAT. 1994.

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science 12, University of Dortmund, Germany

    Steven Bashford & Rainer Leupers

Authors
  1. Steven Bashford
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rainer Leupers
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Bashford, S., Leupers, R. Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Design Automation for Embedded Systems 4, 119–165 (1999). https://doi.org/10.1023/A:1008966522714

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008966522714

Search

Navigation