Abstract
Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems.
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References
D.W. Dobberpuhl, “A 200 mhz dual issue cmos microprocessor,” IEEE Journal of Solid State Circuits, Vol. 27, pp. 1555-1567, 1992.
H.B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison-Wesley Pub Co., Reading, MA, 1990.
Edward J. McCluskey, Logic Design Principles, Prentice Hall Series in Computer Engineering, New Jersey 07632, 1986.
J.J. Qian, Satyamurthy Pullela, and Lawrence T. Pillage, “Modeling the 'effective capacitance' of RC-interconnect,” IEEE Transactions on Computer Aided Design, pp. 1526-1535, Dec. 1994.
Lawrence T. Pillage and R.A. Rohrer, “A symptotic waveform evaluation for timing analysis,” IEEE Transactions on Computer Aided Design, pp. 352-366, April 1990.
H.B. Baloglu, J.T. Walker, and J.D. Meindl, “Symmetric high-speed interconnections for reduced clock skewin ULSI and WSI circuits,” in Proceedings of the IEEE ICCD, pp. 118-122, Oct. 1986.
Ren-Song Tsay, “Exact zero skew,” in IEEE International Conference on Computer Aided Design, pp. 336-339, Nov. 1991.
W.C. Elmore, “The transient response of damped linear networks with particular regard to wideband amplifiers,” Journal of Applied Physics, Vol. 19, No. 1, 1948.
D.W. Marquardt, “An algorithm or least squares estimation of non-linear parameters,” Journal of Society of Industrial and Applied Mathematics, Vol. 11, No. 2, pp. 431-441, June 1963.
D.D. Morrision, “Methods for non-linear least squares problems and convergene proofs, tracking programs and orbit determination,” in Proceedings of the Jet Propulsion Laboratory Seminar, pp. 1-9, 1960.
S.W. Director and R.A. Rohrer, “The generalized adjoint network sensitivities,” IEEE Transactions on Circuit Theory, Vol. CT-16, No. 3, 1969.
Noel Menezes, Ross Baldick, and Lawrence T. Pillage, “A sequential quadratic programming approah to concurrent gate and wire sizing,” in Proceedings of the International Conference on Computer Aided Design, pp. 144-151, Nov. 1995.
Curtis L. Ratzlaff, Nanda Gopal, and Lawrence T. Pillage, ”RICE: Rapid interconnect circuit evaluator,” in Proceedings of the 28th Design Automation Conference, pp. 555-560, 1991.
Satyamurthy Pullela, Noel Menezes, and Lawrence T. Pillage, ”Moment-sensitivity based wire sizing for skew reduction in on-chip clock nets,” IEEE Transactions on Computer Aided Design, (to be published).
Noel Menezes, Satyamurthy Pullela, Floren Dartu, and Lawrence T. Pillage, “RC-interconnect synthesis–A moments approach,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 418-425, 1994.
P. O'Brien and T.L. Savarino, “Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 512-515, 1989.
Satyamurthy Pullela, Noel Menezes, and Lawrence T Pillage, ”Reliable non-zero skew clock trees using wire width optimizatio,” in Proceedings of the 30th Design Automation Conference, pp. 165-170, June 1993.
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Ganguly, S., Lehther, D. & Pullela, S. Clock Distribution Methodology for PowerPC™ Microprocessors. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 16, 181–189 (1997). https://doi.org/10.1023/A:1007991007969
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DOI: https://doi.org/10.1023/A:1007991007969