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Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394

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Abstract

The IEEE 1394 high performance serial multimedia bus protocol allows several components to communicate with each other at high speed. In this paper we present a formal model and verification of a leader election algorithm that forms the core of the tree identify phase of the physical layer of the 1394 protocol.

We describe the algorithm formally in the I/O automata model of Lynch and Tuttle, and verify that for an arbitrary tree topology exactly one leader is elected. A large part of our verification has been checked mechanically with PVS, a verification system for higher-order logic.

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Authors and Affiliations

  1. Computing Science Institute, University of Nijmegen, P.O. Box 9010, 6500 GL, Nijmegen, The Netherlands

    Marco Devillers, David Griffioen & Judi Romijn

  2. CWI, P.O. Box 94079, 1090 GB, Amsterdam, The Netherlands

    David Griffioen

  3. CWI, P.O. Box 94079, 1090 GB, Amsterdam, The Netherlands

    Judi Romijn

  4. Computing Science Institute, University of Nijmegen, P.O. Box 9010, 6500 GL, Nijmegen, The Netherlands

    Frits Vaandrager

Authors
  1. Marco Devillers
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  2. David Griffioen
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  3. Judi Romijn
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  4. Frits Vaandrager
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Devillers, M., Griffioen, D., Romijn, J. et al. Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394. Formal Methods in System Design 16, 307–320 (2000). https://doi.org/10.1023/A:1008764923992

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