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Dynamic Power Supply Current Testing of CMOS SRAMs

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Abstract

We describe the design and implementation of a dynamic power supply current sensor which is used to detect SRAM faults such as disturb faults as well as logic cell faults. A formal study is presented to assess the parameters that influence the sensor design. The sensor detects faults by detecting abnormal levels of the power supply current. The sensor is embedded in the SRAM and offers on-chip detectability of faults. The sensor detects abnormal dynamic current levels that result from circuit defects. If two or more memory cells erroneously switch as a result of a write or read operation, the level of the dynamic power supply current is elevated. The sensor can detect this elevated value of the dynamic current. The dynamic power supply current sensor can supplement the observability associated with any test algorithm by using the sensor as a substitute for the read operations. This significantly reduces the test length and the additional observability enhances defect coverages.

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Authors
  1. Jian Liu
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  2. Rafic Z. Makki
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  3. Ayman Kayssi
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Liu, J., Makki, R.Z. & Kayssi, A. Dynamic Power Supply Current Testing of CMOS SRAMs. Journal of Electronic Testing 16, 499–511 (2000). https://doi.org/10.1023/A:1008324900917

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  • DOI: https://doi.org/10.1023/A:1008324900917

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