Skip to main content
SpringerLink
Log in

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The states of the flip-flops and the memory elements are observed and compared with the simulation results. If the chip contains multiple clock domains then these clock domains must be stopped simultaneously, otherwise some of the elements in one or more of the clock domains will capture old data/invalid data. The phenomenon of capturing invalid data is known as data invalidation. This paper describes the data invalidation problem in depth and presents a data invalidation detector circuit. An automated data invalidation analysis tool named DIAna is also presented. By means of experimental results for an industrial SOC, we show the amount of data invalidation that can occur during silicon debug.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. A. Crouch, M. Pressly, and J. Circello, “Testability Features of the MC68060 Microprocessor,” in Proc. IEEE International Test Conference (ITC), 1994, pp. 60-69.

  2. H. Hao and R. Avra, “Structured Design-for-Debug-the SuperSPARCTM-II Methodology and Implementation,” in Proc. IEEE International Test Conference (ITC), 1995, pp. 175-183.

  3. D. Josephson, S. Poehlman, and V. Govan, “Debug Methodology for the McKinley Processor,” in Proc. IEEE International Test Conference (ITC), 2001, pp. 451-460.

  4. M. Strik et al., “Heterogeneous Multi-Processor for Management of Real-Time Video and Graphics Streams,” in Proceedings IEEE International Solid-State Circuits Conference, 2000, pp. 244-245.

  5. G.J. van Rootselaar and B. Vermeulen, “Silicon Debug: Scan Chains Alone Are Not Enough,” in Proc. IEEE International Test Conference (ITC), 1999, pp. 892-902.

  6. B. Vermeulen, S. Oostdijk, and F. Bouwman, “Test and Debug Strategy of the PNX8525 NexperiaTM Digital Video Plateform System Chip,” in Proc. IEEE International Test Conference (ITC), 2001, pp. 121-130.

  7. B. Vermeulen and G.J. van Rootselaar, “Silicon Debug of a Co-Processor Array for Video Applications,” Digest of Papers of IEEE High Level Design Validation and TestWorkshop (HLDVT), 2000, pp. 47-52.

Download references

Author information

Authors and Affiliations

  1. Philips Research Laboratories, IC Design—Digital Design & Test, Prof. Holstlaan 4, M/S WAY-41, 5656 AA, Eindhoven, The Netherlands

    Sandeep Kumar Goel & Bart Vermeulen

Authors
  1. Sandeep Kumar Goel
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bart Vermeulen
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Goel, S.K., Vermeulen, B. Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. Journal of Electronic Testing 19, 407–416 (2003). https://doi.org/10.1023/A:1024639925852

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1024639925852

Search

Navigation