Skip to main content
SpringerLink
Log in

Design Procedure for Two-Stage CMOS Transconductance Operational Amplifiers: A Tutorial

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper deals with well-defined designcriteria for two-stage CMOS transconductance operational amplifiers. A novel and simple designprocedure is presented, which allows electricalparameters to be univocally related to the value ofeach circuit element and biasing value. Unlikeprevious methods, the proposed one is suited for apencil-and-paper design and yields accurateperformance optimization without introducingunnecessary circuit constraints. Bandwidthoptimization strategies are also discussed. SPICE simulations based on the proposed procedures aregiven which closely agree the expected results.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Gray, P., Wooley, D., and Brodersen, R., (Ed.), Analog MOS Integrated Circuits II, IEEE Press, 1989.

  2. Unbehauen, R. and Cichocki, A., MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems, Springer-Verlag, 1989.

  3. Geiger, R., Allen, P., and Strader, N., VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990.

  4. Soclof, S., Design and Applications of Analog Integrated Circuits, Prentice-Hall, 1991.

  5. Gray, P. and Meyer, R., Analysis and Design of Analog Integrated Circuits, 3rd ed., John Wiley & Sons, 1993.

  6. Gregorian, R. and Temes, G. C., Analog MOS Integrated Circuits for Signals Processing, John Wiley & Sons, 1986.

  7. Allen, P. and Holberg, D., CMOS Analog Circuit Design, Holt Rinehart and Winston Inc. 1987.

  8. Laker, K. and Sansen, W., Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.

  9. Gielen, G. and Sansen,W., Symbolic Analysis for Automated Design of Analog Integrated Circuits, Kluwer Academic Publisher, 1991.

  10. Yang, H. and Allstot, D., “Considerations for fast settling operational amplifiers.” IEEE Trans. on Circuits and Systems 37(3), pp. 326-334, March 1990.

    Article  Google Scholar 

  11. Huijsing, J., Hogervorst, R., and de Langen, K., “Low-power low-voltage VLSI operational amplifier cells. “IEEE Trans. on Circuits and Systems (part II) 42, pp. 841-852, November 1995.

    Google Scholar 

  12. Palmisano, G. and Palumbo, G., “A very efficient CMOS low voltage output stage.” IEE Electronics Letters 31(21), pp. 1830-1831, 1995.

    Article  Google Scholar 

  13. Palmisano, G., Palumbo, G., and Salerno, R., “CMOS output stages for low voltage power supply.” IEEE Trans. on CAS part II 47(2), pp. 96-104, February 2000.

    Google Scholar 

  14. Tsividis, Y., Operation and Modeling of the MOS Transistor, McGraw-Hill, 1988.

  15. Tsividis, Y. and Gray, P., “An integrated NMOS operational amplifier with internal compensation,” IEEE J. of Solid-State Circuits SC-11(6), pp. 748-754, December 1976.

    Article  Google Scholar 

  16. Smaradoiu, G., Hodges, D., Gray, P., and Landsburg, G., “CMOS pulse-code-modulation voice codec.” IEEE J. of Solid-State Circuits SC-13, pp. 504-510, August 1978.

    Article  Google Scholar 

  17. Ahuja, B. “An improved frequency compensation technique for CMOS operational amplifiers.” IEEE J. of Solid-State Circuits SC-18(6), pp. 629-633, December 1983.

    Article  MathSciNet  Google Scholar 

  18. Black Jr., W., Allstot, D., and Reed, R., “A high performance low power CMOS channel filter.” IEEE J. of Solid-State Circuits SC-15(6), pp. 929-938, December 1980.

    Article  Google Scholar 

  19. Palmisano, G. and Palumbo, G., “An optimized compensation strategy for two-stage CMOS OP AMPS.” IEEE Trans. on Circuits and Systems (part I) 42(3), pp. 178-182, March 1995.

    Article  Google Scholar 

  20. Palmisano, G. and Palumbo, G., “A compensation strategy for two-stage CMOS opamps based on current buffer.” IEEE Trans. on Circuits and Systems (part I) 44(3), pp. 257-262, March 1997.

    Article  Google Scholar 

  21. Palmisano, G. and Palumbo, G., “An accurate analysis of the frequency behavior of CMOS differential stages.” IEEE Trans. on Education 41(3), pp. 216-218, August 1998.

    Article  Google Scholar 

  22. Laker, K. and Sansen, W., Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.

  23. Palmisano, G. and Palumbo, G., “Simplified model of an amplifier with two poles and a pole-zero doublet.” ICECS 96, Rodos, pp. 124-127, October 1996.

  24. Palmisano, G. and Palumbo, G., “Analysis and compensation of two-pole amplifiers with a pole-zero doublet.” IEEE Trans. on CAS part I 46(7), pp. 864-868, July 1999.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Dipartimento Elettrico Elettronico e Sistemistico, Universita' di Catania, Viale Andrea Doria, 6, I-95125, Catania, Italy

    G. Palmisano, G. Palumbo & S. Pennisi

Authors
  1. G. Palmisano
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. Palumbo
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. S. Pennisi
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Palmisano, G., Palumbo, G. & Pennisi, S. Design Procedure for Two-Stage CMOS Transconductance Operational Amplifiers: A Tutorial. Analog Integrated Circuits and Signal Processing 27, 179–189 (2001). https://doi.org/10.1023/A:1011229119071

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1011229119071

Search

Navigation