Skip to main content
SpringerLink
Log in

Detection of Defects Using Fault Model Oriented Test Sequences

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper analyzes the possibilities and limitations of defect detection using fault model oriented test sequences. The analysis is conducted through the example of a short defect considering the static voltage test technique. Firstly, the problem of defect excitation and effect propagation is studied. It is shown that the effect can be either a defective effect or a defect-free effect depending on the value of unpredictable parameters. The concept of ‘Analog Detectability Interval’ (ADI) is used to represent the range of the unpredictable parameters creating a defective effect. It is demonstrated that the ADIs are pattern dependent. New concepts (‘Global ADI’, ‘Covered ADI’) are then proposed to optimize the defect detection taking into account the unpredictable parameters. Finally, the ability of a fault oriented test sequence to detect defect is discussed. In particular, it is shown that the test sequence generated to target the stuck-at faults can reasonably guarantee short defect detection till a limit given by the Analog Detectability Intervals.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. F.J. Fergusson and S.C. Shen, “Extraction and Simulation of Realistic CMOS Faults with Inductive Fault Analysis,” Proc. Int'l Test Conference, USA, 1988, pp. 475–484.

  2. W. Maly, P.K. Nag, and P. Nigh, “Testing Oriented Analysis of CMOS ICs with Opens,” Proc. Int'l Conference on Computer Aided Design (ICCAD), Nov. 1988, pp. 344–347.

  3. K. Baker and B. Verhelst, “IDDQ Testing Because 'Zero Defects isn't Enough,” Proc. Int'l Test Conference, Sept. 1990, p. 253.

  4. R.R. Fritzemeier, J.M. Soden, K.R. Treece, and C.F. Hawkins, “Increased CMOS IC Stuck-at Fault Coverage with Reduced IDDQ Test Sets,” Proc. Int'l Test Conference, Sept. 1990, pp. 427–435.

  5. J.M. Soden, R.R. Fritzemeier, and C.F. Hawkins, “Zero Defect or Zero Stuck-at Faults--CMOS IC Process Improvement with IDDQ,” Proc. Int'l Test Conference, Sept. 1990, pp. 255–256.

  6. J.M. Acken and S.D. Millman, “Fault Model Evolution for Diagnosis: Accuracy vs. Precision,” Proc. IEEE Custom Integreted Circuits Conference, 1992, pp. 13.4.1–13.4.4.

  7. R. Kapur, J. Park, and M.R. Mercer, “All Test for a Fault are not Equally Valuable for Defect Detection,” Proc. Int'l Test Conference, Baltimore, MD, USA, 1992, pp. 762–769.

  8. P.M. Maxwell and R.C. Aitken, “IDDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverages,” Journal of Electronic Testing: Theory and Applications, Vol. 3, No. 4, pp. 305–316, Nov. 1992.

    Google Scholar 

  9. P. Wiscombe, “A Comparison of Stuck-at Fault Coverage and IDDQ Testing on Defect Levels,” Proc. Int'l Test Conference, Oct. 1993, pp. 293–299.

  10. C.F. Hawkins, J.M. Soden, A.W. Righter, and J. Ferguson, “Defect Classes--An Overdue Paradigm for CMOS IC Testing,” Proc. Int'l Test Conference, USA, Oct. 1994, pp. 413–425.

  11. J. Park, M. Naivar, R. Kapur, M.R. Mercer, and T.W. Williams, “Limitations in Predicting Defect Level Based on Stuck-at Fault Coverage,” Proc. 12th IEEE VLSI Test Symposium, NJ, USA, April 1994, pp. 186–191.

  12. L.C. Wang, T.W. Williams, and M.R. Mercer, “Using Target Faults to Detect Non Target Defects,” Proc. Int'l Test Conference, USA, Oct. 1996, pp. 629–638.

  13. J.M. Acken, “Testing for Bridging Faults (Shorts) in CMOS Circuits,” Proc. 20th Design Automation Conference, Miami-Beach, FL, USA, June 1983, pp. 717–778.

  14. H. Hao and E.J. McCluskey, “Resistive Shorts within CMOS Gates,” Proc. Int'l Test Conference, Oct. 1991, pp. 292–301.

  15. M. Dalpasso, M. Favalli, P. Olivo, and B. Ricco, “Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs,” Proc. Int'l Test Conference, Sept. 1992, pp. 486–493.

  16. R. Rodriguez-Montanes, E. Bruls, and J. Figueras, “Bridge Defects Resistance Measurements in a CMOS Process,” Proc. Int'l Test Conference, Sept. 1992, pp. 892–899.

  17. M. Favalli, M. Dalpasso, P. Olivo, and B. Ricco, “Analysis of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs,” Proc. Int'l Test Conference, Oct. 1993, pp. 865–873.

  18. P.C. Maxwell and R.C. Acken, “Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Threshold,” Proc. Int'l Test Conference, Oct. 1993, pp. 63–72.

  19. H. Vierhaus, W. Meyer, and U. Glaser, “CMOS Bridges and Resistive Transistor Faults: IDDQ Versus Delay Effects,” Proc. Int'l Test Conference, Oct. 1993, pp. 83–91.

  20. M. Renovell, P. Huc, and Y. Bertrand, “CMOS Bridging Fault Modelling,” Proc. 12th IEEE VLSI Test Symposium, NJ, USA, April 1994, pp. 392–397.

  21. M. Renovell, P. Huc, and Y. Bertrand, “The Configuration Ratio: A Model for Simulating CMOS Intragate Bridge with Variable Logic Threshold,” Proc. 1st European Dependable Computing Conference, Berlin, Germany, Oct. 1994, pp. 165–177.

  22. M. Renovell, P. Huc, and Y. Bertrand, “A Unified Model for Inter-Gate and Intra-Gate CMOS Bridging Fault: The Configuration Ratio,” Proc. 3rd Asian Test Symposium, Nara, Japan, Nov. 1994, pp. 170–174.

  23. M. Renovell, P. Huc, and Y. Bertrand, “The Concept of Resistance Interval: A New Parametric Model for Realistic Resistive Bridging Fault,” Proc. 13th VLSI Test Symposium, NJ, USA, May 1995, pp. 184–189.

  24. Y. Liao and D.M.H. Walker, “Optimal Voltage Testing for Physically-Based Faults,” Proc. 14th VLSI Test Symposium, NJ, USA, May 1996, pp. 344–353.

  25. Y. Lino and D.M.H. Walker, “Fault Coverage Analysis for Physically-Based CMOS Bridging Fault at Different Power Supply Voltages,” Proc. Int'l Test Conference, USA, Oct. 1996, pp. 767–775.

  26. M. Renovell and Y. Bertrand, “Test Strategy Sensitivity to Defect Parameters,” Proc. Int'l Test Conference,Washington, DC, USA, Nov. 1997, pp. 607–616.

Download references

Author information

Authors and Affiliations

  1. Laboratoire d'Informatique Robotique Microélectronique de Montpellier LIRMM-UMII, Université de Montpellier II: Sciences et Techniques du Languedoc, UMR C5506 CNRS-161, rue Ada, 34392, Montpellier Cedex 5, France

    M. Renovell, F. Azaïs & Y. Bertrand

Authors
  1. M. Renovell
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. F. Azaïs
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Y. Bertrand
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Renovell, M., Azaïs, F. & Bertrand, Y. Detection of Defects Using Fault Model Oriented Test Sequences. Journal of Electronic Testing 14, 13–22 (1999). https://doi.org/10.1023/A:1008336919671

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008336919671

Search

Navigation