Origin of Anomalous Piezoresistive Effects in VLS Grown Si Nanowires

Although the various effects of strain on silicon are subject of intensive research since the 1950s the physical background of anomalous piezoresistive effects in Si nanowires (NWs) is still under debate. Recent investigations concur in that due to the high surface-to-volume ratio extrinsic surface related effects superimpose the intrinsic piezoresistive properties of nanostructures. To clarify this interplay of piezoresistive effects and stress related surface potential modifications, we explored a particular tensile straining device (TSD) with a monolithic embedded vapor–liquid–solid (VLS) grown Si NW. Integrating the suspended NW in a gate all around (GAA) field effect transistor (FET) configuration with a transparent gate stack enables optical and field modulated electrical characterization under high uniaxial tensile strain applied along the ⟨111⟩ Si NW growth direction. A model based on stress-induced carrier mobility change and surface charge modulation is proposed to interpret the actual piezoresistive behavior of Si NWs. By controlling the nature and density of surface states via passivation the “true” piezoresistance of the NWs is found to be comparable with that of bulk Si. This demonstrates the indispensability of application-specific NW surface conditioning and the modulation capability of Si NWs properties for sensor applications.

S train engineering has been widely explored to alter the band structure 1−5 in semiconductors and thereby elementary physical properties like the effective mass, 3,4 carrier mobility, 2 band alignment, 6,7 or electrical conductivity. 5 The benefit of mobility improvement has accomplished the step from basic research to industrial production of strained Si to enhance performance of CMOS devices. 8 The main limitation of strain engineering is founded in the maximum fraction strength of the respective material. For bulk Si the maximum yield stress that can be applied without causing damage to the crystal lattice is 3 GPa. 9 An increase of fracture strength for nanostructures has been proven for VLS grown single crystalline silicon NWs. The reason therefore is 2-fold, namely, a decrease of defect concentration as well as modifications of the fracture initiation mechanism. 10 By using a VLS growth process, such quasi-one-dimensional rods with a nearly defect free lattice structure can be synthesized with excellent control of chemical composition, geometry, and growth orientation. Such grown Si NWs with diameters below 200 nm have shown an increase of the fracture strain limit up to 12 ± 3 GPa 10 at near the same Young's module. 11 Anomalous piezoresistance observed in such Si NWs represents a further remarkable example of the effect of size on the physical properties of one of the most well studied semiconductors. The change in resistance due to an applied mechanical stress, being orders of magnitude larger than that of bulk Si is seen as a potential breakthrough of detecting motion in nanoelectromechanical systems. 12 However, because of the large surface-to-volume ratio of nanostructures, the electrical and optical properties of NWs are affected or even determined by dangling bonds, defects, or adsorbates. 13−17 As a result, the performance of nanodevices are expected to be strongly determined by surface states, ruling mainly the functionality of, e.g., highly sensitive sensors. 18−22 Thus, with respect to strain related investigations this requires an impeccable design of experiment, to distinguish whether an effect is mainly attributed to the intrinsic strain related effects or to surface state alterations. 14,23,24 To clarify this interplay of surface related effects and strain engineering in nanostructures, we explored a particular TSD with a suspended VLS grown Si NW integrated in a FET configuration, enabling combined electric field and strain modulation in individual NWs. Figure 1a shows the schematic of the 3-point straining module and Figure 1b the respective SEM image of an individual Si NW bridging the Si pads of a silicon-on-insulator device structure.
By combining well-known top down semiconductor processing techniques and epitaxial Si NW growth with control of the NW location and orientation we circumvent the problem of handling and positioning nanometer-sized objects that arise in the conventional pick-and-place approach. 25 The NW is monolithically integrated into the TSD through a self-aligned VLS growth process, which guarantees electrically reliable and mechanical robust contacts. 26,27 The SEM image in Figure 1b shows a detailed view of the ⟨111⟩-oriented Si NW bridging two insulated Si pads. To accomplish the GAA FET and further enable optical measurements in situ, a transparent gate stack was assembled with SiO 2 or Al 2 O 3 as dielectric and indium− tin−oxide (ITO) as the NW wrapped around gate. The TSD chip is aligned and glued firmly onto a steel plate, and electrical contacts are formed by aluminum wire bonding according to the schematic in Figure 1a. Thus, when the steel plate is subjected to 3-point bending, mainly uniaxial tensile stress is created along the suspended NW. Details of TSD design and processing, NW integration, and GAA formation are given in the Supporting Information.
As a feedback for process optimization, I/V characteristics were measured (i) for the as-grown NW, (ii) after removal of Au residuals from the NW surface with aqua regia and buffered hydrofluoric acid (BHF), and finally, (iii) after the deposition of the dielectrics. The I/V curves in Figure 2a show the effect of the chemical treatment as well as subsequent thermal oxidation on the electrical transport properties of the VLS grown Si NW in the TSD.
A characteristic I/V curve for an as-grown Si NW is shown in Figure 2a (black curve). By fitting the linear part near zero bias of nine NWs, a resistivity of 67 ± 8 kΩ cm is determined. Through linearization of the measured I/V curve this value represents an average of the resistivity over the bulk region and the space-charge region at the surface of the NW. For the TSD, electrical measurements are confined to 2-terminal measurements suffering from parasitic effects of the contact resistance. However, because of the low resistivity of the heavily p-doped contact regions the contact resistance was found to be negligible. Several NWs were measured in parallel to the processing steps to characterize the influence of each individual step. The measurement of the as-grown NWs was performed several days after NW synthesis and storage in ambient air; thus, we can expect that each NW is covered with a saturated native oxide of a thickness of about 2 nm. 14 After etching gold particles, decorating a Si NW after VLS growth, 28 with aqua regia and BHF, the TSD was immediately transferred to the electrical probe station. Because of BHF treatment, the native oxide is removed and the NW exhibits an H-terminated surface. 29,30 Compared to the as-grown Si NWs after the chemical treatment the NWs showed an improved conductivity. Finally the formation of the SiO 2 dielectrics via thermal oxidation leads to a further pronounced increase of the current by more than an order of magnitude. Covering a NW with

Nano Letters
Letter DOI: 10.1021/nl5044743 Nano Lett. 2015, 15, 1780−1785 Al 2 O 3 immediately after the gold removal leads in contrary to a slight decrease of the current. Thus, the I/V characteristic of the Al 2 O 3 coated NWs and the as-grown NWs appeared to be very similar.
According to the large surface-to-volume ratio, dangling bonds, surface defects, and adsorbates play a dominant role in the electrical characteristics of NWs. Previous reports suggested that adsorbates (mainly water and oxygen) can seriously influence the electrical properties of nanostructures by trapping carriers. 31−33 However, transferring our device into vacuum does not change the electrical characterization distinctly. According to our experimental results we thus propose that conductivity of VLS grown Si NWs is dominated by surface defects and dangling bonds. After the BHF dip the native oxide is removed and the NW has an H-terminated surface. The increase in conductance by more than an order of magnitude after thermal oxidation can thus be explained through the replacement of the native oxide with quite poor interface properties by a high quality thermal oxide. The SiO 2 layer formation by thermal oxidation isolates the device from the ambient and has been proven to be effective in passivating nanostructure surface defects. 34 As stated above the suspended NWs with the dielectric (SiO 2 or Al 2 O 3 ) and terminal ITO coating resembles a FET with a transparent wrapped around gate. This setup enables to measure the transfer characteristics of the field-modulated NW at various strain levels. Figure 2b shows the comparison of thus measured transfer characteristics for an unstrained NW with SiO 2 and Al 2 O 3 dielectrics as well as for an as-grown NW in four-probe backgate configuration (see Supporting Information). For the as-grown Si NW (black line) the current through the NW increases appreciably with increasing negative gate voltage, characteristic for a p-channel enhancement mode transistor. Even though the VLS synthesized Si NWs are not doped on purpose during growth, unintentional p-type doping usually occurs due to surface states and bulk impurities. 18,35 Surprisingly the Si NWs in the TSD with SiO 2 as dielectric exhibit the typical characteristics of an n-channel FET, i.e., the device is OFF for negative gate voltage. This inversion of the conduction type demonstrates that controlling surface charges can similarly achieve doping effects in NWs. Becuase of Schmidt et al., 14 the effective carrier concentration in NWs is strongly linked to the density of interface traps as well as to the fixed oxide charges (Q F ). For NWs with low doping concentration the polarity of fixed oxide charge of the surrounding dielectric material in combination with modification of surface states can even cause an inversion of the major carrier type in the NW. 15,24 Thus, using SiO 2 as dielectric, positive fixed oxide charges 36 in the range of Q F = +10 10 cm −2 changes the transfer characteristic into an n-type. Consequently for Al 2 O 3 as dielectric, which exhibits negative fixed oxide charges 36 in the range of Q F = −10 11 cm −2 , the Si NWs in the TSD device show p-type behavior (Figure 2b). Further for the as-grown NW in back gated configuration sweeping the gate voltage from negative to positive values and vice versa, we observe a pronounced hysteresis (see Figure 2b). This behavior is indicative of charge-trapping states originating from the large number of surface defects and dangling bonds. 37,38 Again, when the native oxide is replaced by the high quality thermal oxide, the transfer characteristic of the suspended NW shows much less hysteresis (see Figure 2b) indicating reduction of charge traps. 18,39 A prerequisite to investigate the interplay of such surface related effects and mechanical stress on the electronic properties of NWs requires the opportunity to modulate the transverse electric field and an accurate strain measurement. The particular TSD module with the transparent gate stack enables such electrical characterization of the wrapped around gate FET and to determine the actual strain of the Si NW using confocal μ-Raman spectroscopy (see Figure 1a). Application of stress to the NW causes a shift of the first order optical phonon peak of Si at 520.2 cm −1 linearly dependent on the strain. 40 These typical shifts to lower wave numbers of a strained NW integrated in the TSD and, for comparison, bulk Si are shown in Figure 3a. The inset shows the relationship between the Raman signal peak shift and thereof calculated strain values of the NW. The maximum peak shift of about 8 cm −1 shown for the highest strain level in the main plot of Figure 3a corresponds to a tensile strain of 2.4%. Details of strain The accurate strain measurement and subsequent I/V characterization enable us to measure changes in the resistivity due to strain and thus to determine the piezoresistive coefficients. The equation for the relative change of resistivity Δρ/ρ for a cylindrical piezoresistive NW is given by with υ the Poisson's ratio and ε ∥ the strain along the ⟨111⟩ growth direction of the Si NW. Dimensional changes of the NW caused by strain were neglected due to their small contribution. Figure 3b shows the strain induced relative change in resistivity for an as-grown Si NW as well as the Si NW in GAA FET configuration with Al 2 O 3 or SiO 2 as dielectric layer. For the as-grown NW covered with native oxide, we determined an anomalous behavior with an increase of the resistivity up to strain levels of about 0.3% followed by a strong decrease down to Δρ/ρ ≈ −80% for about 3% strain. 41 For the Al 2 O 3 coated Si NW the resistivity increases monotonically up to a maximum of Δρ/ρ ≈ +30% at a strain level of ε ∥ = 1%. Although Al 2 O 3 coated Si NW withstands higher loads before a sudden failure occurs, electrical characterization was limited due to the appearance of leakage currents in the gate dielectric for strain values >1%. With SiO 2 as dielectric the device appeared to be less prone to strain induced leakage. Contrary to the Al 2 O 3 for the SiO 2 coated NW we determined a decrease of the resistivity to Δρ/ρ ≈ −30% at a strain of ε ∥ = 2.4% limited by the mechanical robustness of the NWs. Assuming uniaxial strain the piezoresistive coefficients can be calculated according to ρ ρ π σ Δ = l with Δρ/ρ the relative change of resistivity, π l the longitudinal piezoresistive coefficient and σ the applied stress. This coefficient is dependent on crystal orientation as well as on doping concentration of the semiconductor. 42 Simulation results of ⟨111⟩ oriented Si show a piezoresistive coefficient for p-doped bulk Si in the range of π l = +94 × 10 −11 Pa −1 , while for n-type Si the piezoresistive coefficient has negative sign and is in the range of π l = −7.5 × 10 −11 Pa −1 . 42 Fitting the measurement data in the linear regime in Figure 3b leads to a longitudinal piezoresistive coefficient of π l = +26.7 × 10 −11 Pa −1 and π l = −8.8 × 10 −11 Pa −1 for a Si NW coated with Al 2 O 3 and SiO 2 , respectively. The dashed lines in Figure 3b show the calculated trend of p-doped (red dashed line) and ndoped (blue dashed line) bulk silicon. While the piezoresistive coefficient of the SiO 2 covered NW shows good agreement with the n-doped bulk value, for the Al 2 O 3 passivated Si NW the stress induced increase of the resistivity is less pronounced and tends to saturate at higher strain values. Nonetheless, qualitatively and in accordance with the transfer characteristic measurements the piezoresistive behavior of the Al 2 O 3 and SiO 2 covered Si NWs behave like n-type and p-type doped Si, respectively. Thus, for the passivated Si NWs no anomalous piezoresistance was observed, but taking into account surface related doping effects in nanostructures, 15 the true stressdependent conductance change is consistent with bulk Si piezoresistance.
Measuring the transconductance g m characteristics for the same NWs one can estimate the field mobility μ of the carriers as a function of strain according to g m = dI D /dV G = μCV D /L 2 , with L representing the active channel length and C the capacitance between the cylindrical NW and the gate contact. 43 Figure 4a shows the comparison of the change in relative resistivity and the corresponding relative change in field-effect mobility as a function of applied strain. For both, the SiO 2 as well as the Al 2 O 3 covered NW, the resistivity changes appear to be directly proportional to mobility modifications due to strain. Figure 4b shows the strain related change of the NW resistivity in absolute values for the as-grown and the Si NW FET with SiO 2 as dielectric for different gate voltages. The resistivity of the as-grown NW appears to be more than 35 times larger compared to the SiO 2 coated NW at gate bias of V gate = 0 V. The lower resistivity proves again the effectiveness of SiO 2 in surface state passivation. In accordance with Schmidt et al., we observed an increase of mobility as well as the effective carrier concentration of the wire and therefore a significant decrease of resistance. 24 However, more remarkably for the SiO 2 coated NW, even when the gate field modulates the density of charge carriers and thus the conductance in the channel over several decades, the influence of strain appears to be widely unaffected by the gate bias. Thus, again, the piezoresistivity of SiO 2 coated Si NWs, i.e., the increase in conductivity is mainly attributed to The issue still to be resolved concerns the origin of the anomalous piezoresistance of the VLS grown Si NWs. For the bare NW integrated in the TSD a positive piezoresistive coefficient of +36.3 × 10 −11 Pa −1 was calculated for strain values up to 0.3%, whereas for strain values up to 1% negative piezoresistivity was observed with π l = −50.3 × 10 −11 Pa −1 (Figure 3), more than 6 times higher than for n-doped bulk Si. For even higher strain up to 3% the piezoresistivity converges to values of bulk n-type doped Si. The quite low alteration of the piezoresistance of the passivated NWs indicates the origin of the anomalous piezoresistive effect of as-grown Si NWs to changes in surface charges during strain modulation. In accordance with Rowe, we thus determined stress induced modulation of the surface potential of the semiconductor as the origin of the anomalous piezoresistive behavior, which critically depend on the density and nature of the surface states. 44 Negative charges on the surface would cause surface band bending resulting in hole accumulation and thus induce the observed p-type behavior in as-grown Si NWs. The thus induced depletion region near the surface of the NW reduces also the conduction cross-sectional area. 15,16,45 As the Si NWs are thin, the depletion region occupies a great fraction of the cross-sectional area. Variations in the thickness of the depleted region occur via a stress-induced modulation of the surface potential barrier, 44 which leads to filling or depopulation of the trap states. Different surface states with their particular energy levels and density of states would result in different surface potentials due to Fermi level pinning at the surface states and thus modulate the depletion width. 46,47 Such variation of the depletion zone width would be most pronounced for intrinsic NWs. He and Yang observed large stress effects in NWs with high resistivity and small diameters, where the depletion width is approaching the NW diameter. 48 For the as-grown nominally intrinsic NWs at low strain levels this depleting effect is more pronounced due to the higher concentration of defect states compared to the passivated NWs overcompensating a possible mobility improvement due to strain. For highly stressed NWs one also has to take into account strain induced bandgap narrowing resulting in an increase of the charge carrier density. In good agreement, several groups reported on experimental and theoretical works that bandgap changes for Si NWs under uniaxial tensile strain can be as large as 60 and 100 meV per 1% axial strain. 4,7,49,50 Concluding, we have demonstrated that anomalous piezoresistance effects in VLS grown Si NWs are mainly determined by the filling or depopulation of surface states due to the stress induced modulation of the surface potential. By controlling the nature and density of these surface states via passivation, the intrinsic piezoresistance of the NWs is found to be a result of stress-induced carrier mobility change and comparable with that of bulk Si. This demonstrates the indispensability of application orientated surface conditioning to make use of nanostructure related strain effects and highlights the modulation capability of Si NWs for sensor applications, e.g., strain gauges.

* S Supporting Information
Device fabrication and NW synthesis, gate stack formation, strain determination, and calibration. This material is available free of charge via the Internet at http://pubs.acs.org.