Signatures of Gate-Driven Out-of-Equilibrium Superconductivity in Ta/InAs Nanowires

Understanding the microscopic origin of the gate-controlled supercurrent (GCS) in superconducting nanobridges is crucial for engineering superconducting switches suitable for a variety of electronic applications. The origin of GCS is controversial, and various mechanisms have been proposed to explain it. In this work, we have investigated the GCS in a Ta layer deposited on the surface of InAs nanowires. Comparison between switching current distributions at opposite gate polarities and between the gate dependence of two opposite side gates with different nanowire–gate spacings shows that the GCS is determined by the power dissipated by the gate leakage. We also found a substantial difference between the influence of the gate and elevated bath temperature on the magnetic field dependence of the supercurrent. Detailed analysis of the switching dynamics at high gate voltages shows that the device is driven into the multiple phase slips regime by high-energy fluctuations arising from the leakage current.


INTRODUCTION
Since superconducting circuits have the potential to realize electronics with short switching time and ultra-low power consumption, various architectures have been developed for integrating semiconductor technology with superconducting devices to reduce the high power consumption required for cooling the high-density semiconductor-based microchips [1][2][3].The cryotron [4], josephson cryotron [5], rapid single flux quantum (RSFQ) device [6], and nanocryotron (nTron) [1] were all developed as building blocks for superconducting switches, however, their scalability or even the difficulty of interfacing with CMOS electronics limited their applications.
In the recent years, suppression of supercurrent by applying a voltage to a gate electrode in the vicinity of superconducting metallic nanowire has attracted much attention as a promising building block for highly scalable superconducting switches .In some works, the effect is attributed to the large electric field (10 8  V/m) at the superconducting surface [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21], which distorts the superconducting state and leads to the quenching of the superconductivity [29][30][31][32][33].Other studies [22][23][24][25][26][27][28] reported a correlation between the gate controlled supercurrent (GCS) and the leakage current flowing between the gate and the superconducting device.Some of these studies suggest that the GCS results from ballistic injection of high-energy quasiparticles [24][25][26].In another work, the quenching of the supercurrent was at-tributed to the absorption of phonons emitted in the relaxation process of high-energy electrons injected from the gate electrode [28].In order to engineer efficient superconducting switches for future electronic applications, it is important to understand the dominant mechanism behind the CGS effect.
In this work, we have studied the GCS in a superconducting Ta shell deposited on the surface of InAs nanowires [34].We chose Ta because of its strong spinorbit interaction [35,36], so it is expected that the electric field has a strong influence on the superconducting state.We investigated the influence of the distance between the gate and the nanowire on the suppression of the supercurrent for the fabricated devices.Also, the magnetic field dependence of the supercurrent under the influence of the gate voltage and elevated temperatures was investigated.In addition, the switching current distribution at opposite gate polarities and at different current ramp speeds was studied.Furthermore, we give a detailed analysis for the switching dynamics at high gate voltages.Our findings contradict the proposed theoretical explanations based on electric fields or ballistic injection of high-energy electrons, and they are consistent with the nonequilibrium phonons picture as the origin of the GCS effect.

EXPERIMENTS A. Device outline and characterization
In our device configuration, we used InAs nanowires with a 20-nm-thick Ta shell layer deposited on only three facets of the nanowire [34].In order to investigate the impact of the gate on the supercurrent flowing in the Ta layer, four-terminal nanowire-based devices were fabricated with the configuration shown in Fig. 1a, b.The Ta/InAs nanowires (green/brown) were deposited on a doped Si wafer with a 290-nm-thick oxide layer.Four Ti/Al contacts (blue) with a thickness of 10/80 nm were fabricated for quasi-four terminal measurements.A two metallic Ti/Au side gates SG1 (orange) and SG2 (light blue) with a thickness of 7/33 nm were placed with unequal spacings and on opposite sides of the nanowire.This provides a possibility to study the GCS effect for the device with gates at different spacings.The results presented in this paper are based on measurements performed on three different devices, A, B and C with the same device geometry, but with different values of nanowire−gate spacing d in the range from 30 to 120 nm.The results in Fig. 1 were measured on device A, in Fig. 2 on device B, while the results in Fig. 3 and their analysis in Fig. 4 were performed on device C.
The current−voltage (I − V ) characteristics measured at 35 mK show a clear switching from the superconducting state to the normal state at the switching current I SW 1.17 µA (see blue curve in Fig. 1c).When the measurements are carried out in the opposite sweep direction (grey curve), the device shows a hysteretic behaviour and switches back to the superconducting state at two successive retrapping current values at 0.61 µA and 0.4 µA.This hysteretic behaviour can be attributed to large Joule heating dissipated in the resistive state [37].The GCS is investigated by measuring the dependence of I SW under the influence of gates SG1 (orange) and SG2 (light blue) with d of 65 and 115 nm, respectively.Fig. 1d shows I SW as a function of V sg for both gates, where each of the plotted curves has the same colour as the corresponding gate in Fig. 1a.The plot reveals that both gates completely switch the device to the normal state at almost the same critical gate voltage V sg,C ±13 V. Despite the nanowire−gate spacing for SG1 is about half that for SG2, SG2 still suppresses I SW at lower threshold gate voltage V th than SG1.Importantly, at V th , a correspondingly large increase in the gate leakage current I leak is observed for each of the gates (see Fig. 1e), which has also been reported elsewhere [22,23,25,26,28].

B. Magnetic field dependence
The dependence of the supercurrent in our device on the out-of-plane magnetic field B is shown in Fig. 2a, where the I − V curves are measured as a function of the B-field up to ±2 T. The white region represents the zero-resistance state, with a transition to and from the normal state (red and blue regions) at the switching and retrapping current values in the positive and negative bias current values, respectively.The magnitude of I SW shows a rapid suppression with increasing B-field below 100 mT and then slowly decreases with further increasing the magnetic field up to 2 T. The sharp decrease in the critical current below 100 mT coincides with the B C of the Al electrodes contacting the nanowire [23], therefore we believe that this decrease is a result of the Al contacts switching to normal state.Although the maximum Bfield in our setup (2 T) does not allow full suppression of the superconducting state in the Ta shell, based on the measured trend, B C is expected to be about 3.5 T, which is consistent with earlier findings on identical Ta/InAs nanowires [38].
The gate dependence of I SW under the influence of Bfield is shown in Fig. 2b.I SW is plotted as a function of V sg at different values of magnetic field up to 2 T. No significant change in V sg,C with increasing B-field was observed, which is in contrast to the dependence observed for Ti and Al nanostructures [7,23].Fig. 2c and d show the dependence of I SW on B-field under influence of temperature T and V sg , respectively.In the former case, I SW decreases with increasing T , as expected, accompanied by a suppression of B C , giving B C = 2 T at 800 mK and B C = 1.5 T at 900 mK.In the case of the gate control, I SW also decreases with increasing V sg , but surprisingly, no change in B C was observed.For a better comparison, Figs.2e shows a zoom in of the curves in both dependencies marked by the red rectangle and having almost the same magnitude of I SW (at B = 0 T).It can be clearly seen that the B C dependence behaves differently under the influence of temperature and gate voltage.While from 900 mK to 950 mK B C further decreases from 1.5 T to 1 T, I SW does not seem to be suppressed by the magnetic field in the case of the gate (see also the Supporting Information) in strong contradiction to other works [10,16,23].
Another remarkable difference between temperature and gate dependence is that I SW exhibits large fluctuations at finite gate voltages (see green curves in Fig. 2e).In order to investigate this effect, the switching current distribution (SCD) at finite temperatures and gate voltages is measured by ramping the current at constant speed from 0 to 3 µA for 10,000 times and recording the corresponding I SW value every time (see Methods).A comparison between the SCDs obtained at 600 mK and 3 V is shown in Fig. 2f.Despite the fact that both histograms have almost the same mean value I SW , the width of the histogram obtained under influence of the gate voltage is an order of magnitude larger than that obtained at elevated bath temperature.The large gate-induced broadening is consistent with Refs.14, 19, 22, 26, 28 and shows that the gate voltage induces an out-of-equilibrium state in the superconducting nanowire, which cannot be described with an effective temperature.
In the following, we will compare the SCDs measured at positive and negative gate polarity, as they are expected to behave differently for different microscopic origins of the GCS.The dependence of I SW on V sg of the device is shown in the inset of Fig. 3a, where the positive and negative gate polarities represented by the orange and blue curves, respectively.Fig. 3a shows the SCDs measured at the same |V sg | but with opposite polarities are paired and shifted along the y-axis for clarity.For simplicity, we made the measurements with the Al leads in the normal state, at B = 100 mT [23].There is a clear difference in the shape and I SW of SCDs paired at equal |V sg |.In addition, we also paired SCDs for opposite gate polarities and with approximately the same power dissipated at the gate P G = I leak •V sg as shown in Fig. 3b.Comparing Fig. 3a and b, one can conclude that the pairing at the same power gives a better match between SCDs with opposite polarities.We also found that the SCDs measured at positive polarity have a slightly smaller I SW than those measured at negative polarity at the same P G (see inset in Fig. 3b).
Assuming that the electric field E applied by the gate (Fig. 3c) is responsible for the suppression of I SW [29][30][31][32][33], its effect should not depend on the sign of E. Therefore, we expect the SCD obtained at a given voltage V sg to be identical to the SCD obtained at the same gate voltage with the opposite sign, -V sg .Since the measured SCDs do not match at opposite polarities (see Fig. 3a), our results contradict the electric field-based explanation.Another possible microscopic picture is that the CGS is caused by ballistic injection of high-energy quasiparticles, as shown in Fig. 3d.After injection of these electrons, their energy is released by relaxation, heating the side on which they end up.Therefore, for negative gate polarity (Fig. 3d), they heat the superconducting bridge, while for positive polarity they heat the gate electrode instead.Thus, a stronger suppression of superconductivity is expected for negative polarity.Therefore, at the same P G value, the mean value of the distribution is expected to be significantly smaller for negative polarity than for positive polarity.Comparing this prediction with the measured results in Fig. 3b, one can conclude that the experimental findings are just opposite, so that ballistic injection of electrons can also be excluded.
The most likely explanation for our results is the generation of phonons by series of relaxation events of the highenergy electrons in the substrate [28].The small shift between the I SW measured for the two polarities (see Fig. 3b) can be attributed to the short energy relaxation length of electrons in SiO 2 (≤ 3 nm) at high electric fields compared to nanowire−gate spacing (d = 30 nm) [39][40][41][42].Thus, at positive gate polarity, it is expected that the high-energy electrons will relax close to the nanowire (Fig. 3e, left panel) and the generated phonons can heat the superconducting nanowire more than at negative gate polarity (Fig. 3e, right panel).

D. Analysis of the switching dynamics
The standard deviation σ of SCDs measured under the influence of the gate is represented by the blue curve in Fig. 4a.For small values of |V sg |, where I leak is negligible, σ is independent of |V sg | and no significant change in the I SW of SCDs (green curve) was observed.Beyond V th at |V sg | = 2.7 V, σ increases with |V sg | because the fluctuations assisted by I leak become stronger and more frequent.This increases the probability of nanowire switching at small I SW values with a corresponding suppression in the I SW of the SCD.This increase in the width of the SCDs is analogous to the typical temperature dependence (see the Supporting Information) [14,19,43] associated with thermally-activated phase slips [44,45].However, the large width of the SCDs obtained under the influence of the gate indicates that the system is driven to a nonequilibrium state where the fluctuations are an order of magnitude larger than expected from the bath temperature.With further increasing |V sg |, σ decreases and the SCDs become more symmetric, as shown by their calculated skewness in Fig. 4b.This is analogous with the picture that the switching of the system is due to multiple phase slips (MPS) found at finite temperatures [43].
Interestingly, the SCD in Fig. 3a at V sg = 2.8 V (orange curve) shows two peaks, a sharp one at 1.57 µA and a broad one around 1.5 µA.This distribution looks like the sum of two overlapping probability distributions, similar to distributions shown in Refs.14, 22. Since the probability distribution in this transition region depends strongly on the ramp speed of the bias current ν I (see the Supporting Information), we could completely switch between the two distributions when the ramp speed was changed from 300 (at which the SCDs in Fig. 3 are measured) to 9.375 µA/s.For a more accurate evaluation, it is better to transform the measured probability distributions into the speed-independent escape rate Γ(I, T ) (see the Supporting Information) by the direct Kurkijärvi-Fulton-Dunkleberger (KFD) transformation [45][46][47]: where w is the bin size in the current axis of the measured probability distribution P (I, T ), and P (I k , T ) is the switching probability in the bias current interval [kw, (k + 1)w] with k ∈ [0, N ].Fig. 4c shows the logarithm of the calculated Γ(I N , T ) as a function of current for SCDs measured under the influence of V sg in the interval [-3.For V sg > -3 V, where I leak is negligible (the first three curves from the right), Γ L can be well fitted with an exponential curve (black solid line) given by with n = 1 and using α and A as fitting parameters.The switching dynamics in this region have been studied in detail in Ref. 22. On the other hand, for V sg ≤ -3 V Γ L deviates from the single exponential dependence described by Eq. 2. For example, the light green curve measured at -3.2 V can be fitted at large current values using Eq. 2 with n=1 (see black solid lines).Interestingly, the measured curve for I SW < 0.9 µA can be well fitted by adding extra higher order terms with n=2,3,. .., keeping the same values of the fitting parameters.Further increasing V sg (I leak ) requires more higher order terms to fit the escape rate dependence (e.g.orange curve) [43].
The value of α required to fit the escape rate dependence decreases sharply as V sg increases, and saturates at large values of V sg as shown in the inset of Fig. 3c.
The deviation of the escape rate dependence with current from a pure exponential at higher gate voltages is similar to elevated temperatures in Ref. 43.This can be attributed to the reduced impact for a single fluctuation event triggered by the leakage current, since the dissipation during the induced phase slip event is smaller at lower values of I SW [43,45].Thus, several coincident fluctuation events with corresponding induced multiple phase slips (MPS) are required to trigger the switching of the nanowire to the normal state [43,48,49].In this regime, at large bias current values, the dissipation of a single MPS event (n = 1) is sufficient to switch the nanowire into the resistive state.On the other hand, at lower current values, the dissipation of a single MPS event is reduced and higher orders (n = 2, 3, ...) of the MPS event are required to trigger the resistive switching of the nanowire [43].

COMPARISON WITH THE PROPOSED MICROSCOPIC PICTURES
In the following, we will compare our experimental results with the possible microscopic pictures.Starting from the two gates (Fig. 1d,e), despite SG2 has almost twice the nanowire−gate spacing of SG1, it suppresses the I SW at lower V th than SG1.This contradicts the electric field picture as a possible explanation for the origin of the GCS.On the other hand, I SW starts to be suppressed with the onset of leakage current between the nanowire and each of the gates (see the Supporting Information).In another cool-down, the influence of the two gates for the same device shows an opposite situation, as SG1 shows a stronger influence on I SW than SG2 (see the supporting information).This excludes any concerns arising from the quite large dielectric constant of the InAs nanowire between SG2 and the Ta shell (see Fig. 1a), which may lead to a larger influence of SG2 on I SW than SG1.Interestingly, we found that the influence of the two gates on I SW gives better matching with P G in the two cool-downs (see the Supporting Information).
Accepting that the leakage current plays a key role in the GCS, a simple explanation arises: that the leaking electrons increase the temperature of the superconducting nanowire.We have investigated for the first time the B-field dependence of superconducting nanowire with normal contacts, which allows efficient cooling of the superconducting nanowire.The B-field dependence at finite T and finite gate voltage was strictly different, indicating that the effect of leakage current cannot be described by simple hot electron regime induced by elevated bath temperature.The highly non-equilibrium state of the superconductor at finite gate voltage is further supported by the broad SCDs in our work and in previous results [14,19,22,26,28].Our detailed comparison of the SCDs for different gate polarities (Fig. 3) provided another important finding which is inconsistent with electric-field-induced suppression of superconductivity.Pairing of SCDs measured at opposite gate polarities at the same leakage current dissipation, P G , provided a better matching than at the same |V sg | (Fig. 3a,b).This reveals that the suppression of I SW depends not only on the energy of the injected electrons (eV sg ) or the rate of their injection (I leak /e), but on the power dissipated at the gate P G .Based on the I SW of the SCDs for the two polarities, the ballistic injection of electrons from the gate into the superconducting nanowire can be discarded.We conclude that the phonon-mediated excitation of the superconductor remains a microscopic picture consistent with the measured results.
Furthermore, we also noticed that the power dissipation at the gate required to fully suppress I SW , P G,C is comparable to the power dissipation that occurs when the device switches to the resistive state P n = I 2 SW •R n .For example, for device A, in the case of SG1 (the closer to the Ta shell), P G,C 1.5 nW (see the Supporting Information), while P n 1 nW (using R n = 780 Ω and I SW 1.17 µA).Finally, a very large leakage current was required to quench I SW when we investigated the GCS in similar Ta/InAs devices fabricated on a sapphire substrate (see the Supporting Information).These results indicate that the GCS depends mainly on the properties of the substrate and the leakage pathway between the gate and nanowire.

CONCLUSIONS
We investigated the origin of GCS in the Ta half-shell layer deposited on InAs nanowires by various measurements.Devices with small nanowire-gate spacing (specifically devices B and C) fully switch to the normal state below V sg = ±5 V, which makes them promising for integration into classical electronic circuits.When the wire is connected by electrodes in the normal state, the critical magnetic field B C is not suppressed under the influence of the gate as for elevated temperatures.Moreover, the comparison of the switching current distributions at opposite gate polarities, as well as the gate dependence of two opposite side gates at different nanowire-gate spacings show that the power dissipated at the gate P G is the relevant parameter for this effect.Analysis of the switching dynamics under strong gate influence shows a deviation in the escape rate dependence with the bias current from a pure exponential.This indicates that the device is driven into the MPS regime by the high energy fluctuations originating from the leakage current.Our findings contradict the microscopic pictures proposing electric fields or ballistic injection of high-energy electrons as the origin of the GCS effect, but they are consistent with the non-equilibrium superconducting state resulting from the absorption of phonons generated by the leakage current.

METHODS
InAs nanowires were grown by the VLS mechanism using Molecular Beam Epitaxy and the Ta shell was deposited in-situ under UHV using electron beam evaporation at a substrate temperature of about 25 • C. Based on the TEM characterization, the morphology of the Ta shells was continuous but granular on the InAs nanowires and was found to be non-crystalline [38].
The Ta/InAs nanowires were deposited on the top of a doped Si wafer with 290 nm thick SiO 2 layer by means of a hydraulic micromanipulator along with a high magnification optical microscope.The nanowire device was fabricated in two separate electron beam lithography (EBL) steps.In the first step, four Ti/Al contacts with a thick-ness of 10/80 nm were fabricated.Prior to the metal evaporation, Ta/InAs nanowires were exposed to Ar-ion plasma milling for 8 minutes at 50 W to remove any oxides on the top of the Ta shell.In the second step, two metallic gates of Ti/Au layers with a thickness of 7/33 nm were fabricated with unequal spacing and on opposite sides of the nanowire.The metallic gates were fabricated in a separate lithography step, since thin resist is used for precise alignment of the gates from the nanowire.
The I − V characteristics of the device were measured by a pure DC measurements using a quasi 4-probe method in which the current was injected through the nanowire via a pair of Al contacts by using a standard voltage source (Basel DAC SP 927) with series resistor of 1 MΩ, while the voltage was measured across the other pair with a differential voltage amplifierand a digital multimeter (Keithley 2001).The leakage current was recorded by measuring the voltage across a 10 MΩ preresistor connected to the gate and corrected according to the method reported in Ref. 23.
The SCD was measured using a NI-DAQ card (USB-6341), where a periodic current wave signal was engineered.This signal is composed of a positive linear ramp with an amplitude of 3 µA and a slope in the range from 9.375 to 300 µA/s followed by a 2.5 ms of zerocurrent plateau for cooling down the superconducting device.This signal is repeated 10,000 times, and I SW is extracted each time.All SCDs are measured at 0.1 T to switch the Al leads to the normal state.All measurements were carried out in a Leiden Cryogenics CF-400 top-loading cryo-free dilution refrigerator system with a base temperature of 30 mK.

II. MAGNETIC FIELD DEPENDENCE UNDER INFLUENCE OF THE GATE
In the main text (see Fig. 2e), we compared the B-field dependence of the supercurrent of device B at finite temperature and finite gate voltage (with similar I SW at B = 0 T).We found that B C decreases with increasing temperature, but not with increasing V sg .SFig. 2a,b shows some selected (I-V) curves at different B-field values ≥ 1 T at V sg = 3.5 V and 3.7 V, respectively, separated in the x-axis for clarity.the electron bath, in which case this could still be part of the TAPS regime.Since this will not play an important role in our analysis, we will refer to this regime as the QPS regime for simplicity.

SPEED
In this section, we discuss the dependence of SCDs on the current ramp speed ν I for device C in another cool-down in which the gate dependence of I SW is changed (V th and

V. COMPARISON BETWEEN THE INFLUENCE OF TWO OPPOSITE SIDE GATES FOR DEVICE A
Fig. 1d and e in the main text show the dependence of I SW on V sg and the corresponding I leak as a function of V sg for two opposite side gates (SG1 and SG2) for device A. From these data, a parametric curve is plotted between I SW and I leak for the two gates in SFig.5a.The plot shows that I SW is suppressed for both gates at the onset of I leak , despite it decreases at different V th .A larger I leak is required to switch the device to the normal state at negative gate polarity than at the opposite polarity.Plotting I SW as a function of P G as shown in SFig.5b, a better matching between the two curves is observed.We also noticed that for SG1, P G,C is around 1.5 nW which is comparable to the switching power of the device

VI. INVESTIGATION OF DEVICE A IN ANOTHER COOLDOWN
By Investigating device A in another cool-down, the gate dependence of I SW (see SFig. 6a) under the influence of SG1 (orange curve) and SG2 (light curve) gives an opposite situation to that obtained in the first cool-down (see Fig. 1d,e in the main text).In this cool-down,

VII. DUAL-GATE MEASUREMENT
In this section, we will examine the effect of the two opposite side gates on the suppression of I SW as well as on V sg,C .SFig. 7a shows I SW as a function of V sg2 at different values of V sg1 .For V sg2 = 0 V, I SW decreases as expected with increasing V sg1 , while with increasing V sg2 , the dependence of I SW on V sg2 looks quite similar for all values of V sg1 and no change in V sg2,C is observed.The independence V sg,C for one of the gates from the influence of the other has already been reported in Ref. ? , where the electric field was proposed as the origin of the gating effect.However, in our case a corresponding increase in the leakage current was observed as shown SFig.7b.

VIII. MEASUREMENTS ON DIFFERENT SUBSTRATE
We have investigated the GCS in another Ta/InAs nanowire device with the same device configurations but fabricated on a sapphire substrate.Despite I SW is not fully suppressed by V sg in the ±17 V window (see SFig. 8a), the corresponding I leak (see SFig. 8b) and thus P G is two orders of magnitude higher than for the devices fabricated on Si ++ /SiO 2 substrate shown in the main text.A possible reason could be that in case of a phonon mediated scenario the different type of the substrates allow different phonon generation.

FIG. 1 .
FIG. 1. Device geometry and gate dependence characterization (Device A). a A false-colored SEM image and b schematic of the side view of the nanowire device.c I − V characteristics of the device measured at 35 mK.As the bias current ramps from negative to positive values (blue arrow), the device switches to finite-resistance state at the switching current ISW= 1.17 µA.If the current ramps in the opposite direction (grey arrow), the device switches back to the superconducting state at two successive retrapping current values at 0.61 µA and 0.4 µA.d ISW as a function of Vsg (at magnetic field B = 0.1 T) applied to SG1 (orange curve) and SG2 (light blue curve) with nanowire−gate spacings of 65 and 115 nm, respectively.e The leakage current as a function of Vsg for both gates.

FIG. 2 .
FIG. 2. Magnetic field dependence and comparison between the GCS effect and effect of bath temperature (device B, d = 35 nm). a I − V curve as a function of out-of-plane magnetic field B up to ± 2 T. b ISW as a function of Vsg at various values of B-field up to 2 T. c ISW as a function of the B-field at various elevated temperatures and, d at various values of Vsg. e Magnification of the curves surrounded by the red rectangle in c and d. f Comparison between the SCDs measured at T = 600 mK (blue) and Vsg = 3 V (green).

FIG. 3 .
FIG. 3. SCD measurements and schematics for different proposed mechanisms of the GCS effect (device C, d = 30 nm). a SCDs measured at positive (orange) and negative (blue) gate polarity and paired at the same |Vsg|.The SCDs are normalized to their maximum counts and shifted on the y-axis for clarity.The inset shows ISW as a function of Vsg for the investigated device measured at 0.1 T. b SCDs measured at positive (orange) and negative (blue) gate polarity and paired at approximately the same PG.The inset shows the mean value of ISW of SCDs measured at both gate polarities as a function of PG. c Schematic diagram of the electric field E applied from the metallic gate N to the superconducting nanowire SC at positive gate polarity.The colored/uncolored parts represent occupied/unoccupied states.d Schematic diagram of the ballistic electron injection from the gate to the nanowire at negative gate polarity.The high-energy electron (red circle) tunnels through the potential barrier of the substrate S and relaxes to the lowest unoccupied state (close to the superconducting gap edge), releasing heat on the SC-side.e Schematic diagram of relaxation of high-energy electrons in the substrate when injected from the SC/N side to N/SC at positive/negative gate polarity in the left/right panels.In the case of positive gate polarity, the electrons relax close to the SC side (superconducting nanowire) so that it is heated more than in the case of negative gate polarity at the same PG.

FIG. 4 .
FIG. 4. Analysis of the switching dynamics under influence of Vsg (device C, d = 30 nm). a Standard deviation σ and mean value ISW as a function of |Vsg| for all SCDs measured at negative gate polarity in the blue and green curves, respectively.b The calculated skewness as a function of |Vsg| for SCDs measured with a step of 0.1 V in the interval [-3.5, -2.7 V] (surrounded by the vertical grey dotted lines in panel a) where a corresponding increase in I leak is observed.c Logarithm of escape rate Γ as a function of ISW (colored curves) for different values of Vsg from -3.5 V (orange curve) up to -2.7 V (purple curve) with a step of 0.1 V.The colored solid lines represent the fitting of different portions of these curves with an exponential of higher orders n of the slope α.The inset shows the variation of the slope α with increasing Vsg.
I. GATE DEPENDENCE OF THE SUPERCURRENT FOR DEVICES B AND C SFig. 1a and b show the I SW as a function of V sg for devices B and C, respectively.The gate dependence of the devices was investigated by using SG1 (the closest to Ta shell) at B = 0.1 T. Panels c and d show the corresponding I leak as a function of V sg .SFig. 1. a,b I SW as a function of V sg for devices B and C at B = 0.1 T and their corresponding leakage current in c,d, respectively.

SFig. 2 .
a Selected (I-V) curves at different B-field values ≥ 1 T at V sg = 3.5 V and b at V sg = 3.7 V. III.TEMPERATURE DEPENDENCE OF SCD The dependence of SCDs measured at elevated temperatures for device B is shown in SFig.3, in which SCDs measured at different temperatures at B = 0.1 T and normalized to their maximum count are plotted and separated on the y-axis for clarity.The corresponding standard deviation σ and mean value I SW are plotted as a function of temperature T in the top left and bottom right insets, respectively.The standard deviation σ follows the expected conventional dependence as a function of T (see Refs. ??), which can be divided into three distinct regions (different colored regions in the upper left inset) where the switching mechanism is attributed to quantum phase slips (QPS), thermally activated phase slips (TAPS), and multiple phase slips (MPS).Saturation of the width at the lowest temperatures can also originate from non-ideal thermalization of SFig. 3. Temperature dependence of SCDs for device C. In the top left, the standard deviation σ of the SCDs is plotted as a function of temperature.The colored regions represent the quantum phase slips (QPS) regime (light blue), the thermally activated phase slips (TAPS) regime (pink), and the multiple phase slips (MPS) regime (orange-red).In the bottom right inset, the I SW of the SCDs is plotted as a function of temperature T .

SFig. 5 .
a Parametric curve between I SW and I leak for SG1 (orange curve) and for SG2 (light blue) of device A. b I SW as a function of P G for both gates.The inset show a false colored SEM image for the investigated device with two opposite side gates colored same as their corresponding curves.

SFig. 7 .
a I SW and I leak as a function of V sg2 at different values of V sg1 for device A b The corresponding V sg versus I leak .
5, -2.7 V].As long as V sg is small, the SCDs have a sharp peak around I SW =1.57µA, resulting in a large escape rate around this value, which represents the escape rate due to quantum tunnelling or thermal escape Γ T .As the influence of the gate voltage sets in (see e.g., purple curve), a finite escape rate appears at lower I SW values, corresponding to the gate-assisted escape rate Γ L .The latter contribution becomes the dominant escape rate at higher gate voltages (see e.g., green curve).