Wafer-Scale Integration of Graphene-Based Photonic Devices

Graphene and related materials can lead to disruptive advances in next-generation photonics and optoelectronics. The challenge is to devise growth, transfer and fabrication protocols providing high (≥5000 cm2 V–1 s–1) mobility devices with reliable performance at the wafer scale. Here, we present a flow for the integration of graphene in photonics circuits. This relies on chemical vapor deposition (CVD) of single layer graphene (SLG) matrices comprising up to ∼12000 individual single crystals, grown to match the geometrical configuration of the devices in the photonic circuit. This is followed by a transfer approach which guarantees coverage over ∼80% of the device area, and integrity for up to 150 mm wafers, with room temperature mobility ∼5000 cm2 V–1 s–1. We use this process flow to demonstrate double SLG electro-absorption modulators with modulation efficiency ∼0.25, 0.45, 0.75, 1 dB V–1 for device lengths ∼30, 60, 90, 120 μm. The data rate is up to 20 Gbps. Encapsulation with single-layer hexagonal boron nitride (hBN) is used to protect SLG during plasma-enhanced CVD of Si3N4, ensuring reproducible device performance. The processes are compatible with full automation. This paves the way for large scale production of graphene-based photonic devices.

the fundamental mode, 59 have typical width ∼480 nm, when realized on 220 nm SOI. 60Si3N4 single mode WGs have larger width ∼1 µm, depending on Si3N4 thickness, 39 because of the lower refractive index (n=1.98for Si3N4 39 compared to 3.47 for Si at 1550 nm). 61The larger width of Si3N4 WGs contributes to simplify the technology, because it requires less stringent lithography resolution, and also reduce costs, making small (∼10,000 pieces/year) and medium (∼100,000-1,000,000 pieces/year) production volumes more affordable than in SOI or InP manufacturing lines. 31This means that the volume (i.e.number of chips) threshold to implement a product in a Si fab can be reduced by using Si3N4.This enables the cost-effectiveness of medium-volume products (∼10,000-100,000 chips per year), 2 thus opening medium-volume (e.g., long haul telecom optical systems) markets. 2 To reach a high technology-readiness level (TRL >8 i.e.System complete and qualified), 62 adequate for photonic device production, scalable techniques for SLG growth and transfer are needed.Chemical vapour deposition (CVD) on Cu yields SLG that, when encapsulated in hexagonal boron nitride (hBN), has electronic and structural quality (defect density, scattering time and µ) comparable to exfoliated SLG. 35,37,38,63There has been significant progress for SLG scalable growth on dielectrics, such as SiO2 64 and Al2O3, 65 and on CMOS-compatible Ge, [66][67][68] but with RT µ limited to ∼2000 cm 2 V -1 s -1 . 65Hence, as of 2020, the most common approach to obtain µ >5000 cm 2 V -1 s - 1 is to transfer SLG grown on Cu to the target substrate. 69The so-called "wet" transfer 70,71 typically involves chemical etching Cu to release SLG. 69,72Alternatively, SLG can be released from the growth substrate electrochemically 73,74 or by oxidizing Cu at the SLG interface. 75The released SLG is then directly picked up from the aqueous solution using the target wafer, with alignment accuracy ≥1 µm. 76t-transferred SLG has µ ∼10 3 cm 2 V -1 s -1 , 69 which can be improved by 2 orders of magnitude by hBN encapsulation. 37"Fully dry" transfer 35 is based on direct pick-up of SLG from Cu using exfoliated flakes of hBN or other layered materials (LMs), such as WSe2. 39In this approach, SLG is released from Cu and encapsulated without contact with water or solvents, 35 resulting in µ >3x10 5 cm 2 V -1 s -1 at RT. 39 Thus far, scalability is limited by the size of exfoliated hBN flakes (at present, up to ∼100 µm), 77 but CVD hBN or amorphous BN could be used in future to solve this.The "semi-dry" approach consists in SLG delamination from Cu in an aqueous solution either electrochemically 76 or by Cu oxidation, 78 followed by lamination on the target substrate in dry conditions.This yields µ as high as in "fully dry" transfer after hBN encapsulation, 38 while allowing scalability. 76re, we implement an aligned semi-dry transfer of SLG, based on electrochemical delamination in NaOH, and subsequent handling of a suspended polymer/SLG membrane using a frame.This approach avoids the contact of the target substrate with the aqueous solution, and enables deterministic placement of SLG single crystals (SC) with ∼1 µm precision in X and Y inplane, enabled by a transfer set-up equipped with micrometric actuators.We use a freestanding carrier membrane, comprising 2 polymer layers.This enables semi-dry transfer of large SLG matrices (up to ∼12000 SLG-SCs, limited to 40×40 mm 2 by the dimensions of the CVD sample enclosure) 79 with coverage >80% of the target photonics device area, and integrity in terms of SLG continuity, crucial for wafer-scale fabrication of photonic devices.We demonstrate wafer-scale fabrication of DSLG EAMs on Si3N4 WGs based on a stack of two SLGs separated by ∼17 nm Si3N4.
We report 30 EAMs, on 4 chips from the same wafer, with uniform performance ±10%, demonstrating wafer-scale scalability and reproducibility of the complete process.We use monolayer (1L) CVD-hBN as a SLG encapsulation layer, to protect SLG during Si3N4 deposition by plasma-enhanced CVD (PECVD).We get a contact resistance ∼500 Ω µm for EF >0.2 eV, allowing us to achieve a cutoff frequency, i.e. the frequency at which energy flowing through the system is reduced rather than passing through, 17 ~4 GHz for 120 µm EAMs, and ~12 GHz for 30 µm ones.The operation speed is ~20 Gb s -1 , the highest data-rate achieved to date in Si3N4 without using resonating devices.Higher speeds have only been demonstrated in Si3N4 with resonating devices, e.g.SLG on Si3N4 modulators working up to 22 Gb s -1 were reported on microring resonators, 56 while up to 40 Gb s -1 was demonstrated by using piezoelectric lead zirconate titanate (PZT) thin films on Si3N4 microring resonators. 80Due to the gapless nature of graphene, [1][2][3]81 graphene photonics can operate at any wavelength, unlike Refs., 56,80 which were limited to the specific resonant wavelength.

Results and Discussion
Our DSLG EAMs comprise two SLGs on a passive Si3N4 WG, separated by a ∼17 nm Si3N4 dielectric, Fig. 1a.Three factors ensure scalable fabrication with reproducibility.(i) Wafer-scale source material with crystal size comparable to that of single devices, to avoid grain boundaries.(ii) Semi-dry transfer with low impact on SLG cleanliness and electrical properties.(iii) SLG protection prior and during dielectric deposition.In Ref. 76 we addressed (i), by preparing SLG SC matrices.This approach is compatible with the requirements of integrated photonics, allowing tailored growth of SLG according to the geometry of the photonic circuits.The lateral dimensions of the SLG SCs can be tuned from tens to hundreds µm. 45,56,82The deterministic growth relies on pre-treating Cu by electropolishing, to reduce surface contaminations and improve surface flatness.Cu is then patterned with 5 µm Cr seeds at the desired SLG crystal locations.This is done by using optical lithography and thermal evaporation of 25 nm Cr.The growth is performed in a cold-wall CVD reactor (Aixtron BM Pro) at 1060 °C by using Ar annealing to maintain a low nucleation density (∼10 crystals per mm 2 ). 79Due to residual oxidation in Cu, SLG nucleation requires surface impurities, 83 ensuring that SLG SCs nucleate only at the Cr seeds locations.The matrices of SLG SCs grown on Cu need to be released from the growth substrate and transferred to the target wafer (e.g., a wafer containing WGs).To do so, we adapt our semi-dry transfer procedure, 76 and build a dedicated transfer tool.To facilitate handling, SLG is coated with a polymer carrier membrane and a semi-rigid Polydimethylsiloxane (PDMS) frame is attached to the Cu foil perimeter.The transfer itself consists of two stages: 1) wet SLG electrochemical delamination from the growth substrate and 2) dry SLG aligned lamination on the target substrate.After the SLG electrochemical release from Cu in NaOH (see Methods for details), the SLG/polymer membrane is rinsed several times in deionised (DI) water and dried in air.The freestanding membrane is supported by the PDMS frame and can be handled in dry conditions.The SLG SCs are attached to the membrane holder of the lamination tool, which allows angle adjustment with ∼0.1° precision of the membrane with respect to the target wafer.The latter is brought in close proximity (∼500 µm) to the membrane using a 4-axis micrometrical stage (X, Y, Z translation and Θ rotation).After aligning the SLG-SCs to the photonic structures, the target wafer is heated to ∼100 °C and brought into contact with SLG, resulting in adhesion with the target photonics chip over the whole membrane.The alignment is performed using a 12x zoom microscope lens attached to a Digital single-lens reflex (DSLR) camera.The PDMS frame is then detached from the sample, and placed in acetone for the polymer removal.During the delamination of SLG from Cu and alignment to the target substrate, the freestanding polymer-SLG membrane is supported by a semi-rigid frame attached to the perimeter of the sample, Fig. 1c.In Ref., 76 the frame was made from polyimide (Kapton) tape and bonded to the sample using an adhesive, with the risk of chemical reaction with the NaOH electrolyte, thus contaminating the transferred SLG.To mitigate this, here we use PDMS-based support frames, which can be bonded to flat surfaces without any adhesive, thus ensuring transfer cleanliness.An alternative could be to use a solid Polydimethylsiloxane (PDMS) stamp, 84 which may also handle SLG.However, PDMS is not compatible with the lamination temperature (105 °C), due to its large (∼3.1×10 −4 K −1 ) thermal expansion coefficient. 85SLG-SCs attached to a PDMS stamps can develop nm-sized cracks when heated to 100 °C.Our method also relies on a bi-layer carrier polymer comprising 1.5 µm poly(propylene carbonate) (PPC) and 100 nm PMMA, instead of the PMMA support of Ref. 76 The different glass transition temperatures, TG, of PPC (37 °C) 86 and PMMA (105 °C) 86 allow us to have a membrane with variable mechanical properties, which can be controlled with T. At ambient T, during delamination and SLG SC alignment, both polymers are kept<TG, thus providing a rigid support to the freestanding membrane and preventing SLG damage.When the SLG SCs are aligned to the required position on the target wafer, SLG can be laminated on the substrate by heating to ∼100 °C, well above the PPC TG.The relatively thick and viscous PPC layer compared to PMMA allows the membrane to attach to the wafer and conform to surface structures, such as metal contacts, while retaining the integrity due to the solid, yet thin (∼100 nm), PMMA layer, still below the PMMA TG. 87 Crucially, in the lamination stage, the target substrate does not come into contact with an aqueous solution, therefore the transfer can be repeated on different areas of the same wafer without risk of SLG delamination or increased contamination.This enables the growth of SLG on a smaller scale, with greater control of strain and doping, than that currently achievable 88,89 when performing growth and transfer on full 150 or 200 mm wafers.The target wafer can then be populated via several transfers, as shown schematically in Fig. 1b.Before each SLG transfer, photonics WGs are prepared by rinsing the chip in acetone and isopropanol, followed by a deep cleaning in a resist remover (AR-600 71) for 2 min.Following SLG transfer on the WGs, the fabrication of the DSLG stack is performed as follows.SLG is patterned and etched using electronbeam lithography (EBL) (Zeiss Ultra Plus) and reactive ion etching (RIE) (Sistec).The bottom SLG contacts are deposited via thermal evaporation of Ni/Au.A protective 1L-hBN film is transferred over the whole chip area using the semi-dry procedure described above.A 17 nm Si3N4 gate dielectric is deposited over the whole area.Si3N4 is chosen over other dielectrics, such as Al2O3, HfO2 or hBN, due its high breakdown field (>10 MV cm -1 ). 90PECVD can be used to deposit uniform Si3N4 with thickness <20 nm and Root Mean Square (RMS) roughness <0.5 nm. 90Top SLG SCs are then deposited using aligned semi-dry transfer.The top structure of the modulator is fabricated using identical methods to the bottom layer (see Methods for details).The SLG crystals are characterized throughout the fabrication process by Raman spectroscopy with a Renishaw InVia at 532 nm, laser power ∼1 mW and acquisition time ∼4s.Fig. 2b shows representative spectra of SLG on 285 nm SiO2/Si, before (black) and after Si3N4 deposition, with (orange) and without (dark cyan) capping of SLG with 1L-hBN (see sketch in Fig. 2a).The Raman signature of 1L-hBN is extremely weak indicating the low quality of the commercial 1L-hBN. 91The transferred SLG spectrum has a 2D peak with a single Lorentzian shape and with a full width at half-maximum FWHM(2D) ∼26.7 cm −1 , a signature of SLG. 92The G peak position, Pos(G), is ∼1583.7 cm −1 , with FWHM(G) ∼12.4 cm −1 .The 2D peak position, Pos(2D) is ∼2676 cm −1 , while the 2D to G peak intensity and area ratios, I(2D)/I(G) and A(2D)/A(G), are ∼3.1 and ∼6.8, respectively.No D peak is observed, indicating negligible defect concentration. 93,94After Si3N4 deposition, the Raman spectrum of exposed SLG (i.e.without 1L-hBN 5.The latter indicates the creation of Raman active defects, which also act as scattering centres for the charge carriers 95,96 (one order of magnitude µ decrease was reported in Ref. 95 when going from I(D)/I(G) ∼0.01 to I(D)/I(G) ∼0.5).Carrier scattering limits the performance of graphene EAMs, in terms of modulation efficiency (slope of the transmission variation as a function of applied voltage 17 ) and maximum extinction ratio (ER), 17 (i.e. the ratio between maximum and minimum of light transmission 17 ).The effect of defects on FWHM(G), 94 which remains almost unchanged after Si3N4 deposition, is likely compensated by the increased doping. 97The Raman data indicate that the Fermi level (EF) of SLG after transfer is ∼140 meV (hole doping). 98,99EF in the exposed SLG increases to ∼210 meV. 98,99e SLG spectra with hBN capping after Si3N4 deposition have Pos(G) ∼1.4×10 11 cm -2 (taking into account the finite doping (∼210 meV). 94,100Hence, capping with 1L-hBN limits the creation of Raman active defects, therefore contributing to preserve µ. 95,96 SLG SCs exposed to Si3N4 deposition present cracked areas with an average crack size ∼10 μm, as for the optical microscopy image in Fig. 2c (right inset).

e, FWHM(2D) as a function of Pos(G). (f) FWHM(G) as a function of Pos(G). (g) A(2D)/A(G) as a function of Pos(G).
SLG capping with 1L-hBN it is also used to protect SLG during PECVD (at 350°C) of Si3N4.

FWHM(G), together with decrease of I(2D)/I(G) and A(2D)/A(G), indicate an increase in EF upon
Si3N4 deposition. 98,99In addition, a considerable (2500 cps at 1 mW power excitation) photoluminescence background is observed after Si3N4 deposition, which we attribute to the introduction of defects in 1L-hBN. 106The broad band is peaked at 600 nm (inset, Fig. 3a) similar to defect related broad emission in 1L-hBN. 106Raman mapping is then performed on the SLG arrays at 10µm steps.
To monitor the uniformity of the Raman response throughout the fabrication of the DSLG, we map 48 SLG SCs, 24 bottom-layer (b1-4 arrays) and 24 top-layer (t1-4 arrays), on 4 different portions of a 150 mm wafer.Fig. 4

plots false-colour maps of I(D)/I(G), FWHM(2D), FWHM(G), A(2D)/A(G)
for the 4 assembly stages.Each map is taken with 10 µm steps.At a given stage, the Raman data do not show significant variations between SLG belonging to the same portion of the wafer.The same applies between SLG from different parts.This implies that the spread in points in Fig. 4b-e

(a-d) Maps of I(D)/I(G), FWHM(2D), FWHM(G), A(2D)/A(G). Raman mapping is performed at each assembly stage over bottom (b1-4) and top SLG arrays (t1-4).
I(D)/I(G), Fig. 4a, is negligible throughout the fabrication, except for b1-4 after Si3N4 deposition, where it is within 0.1 (0.25) for 59% (90%) of the crystals.FWHM(2D), Fig. 4b, progressively increases upon fabrication on b1-4, while it is comparable for b1-4 and t1-4 after transfer on SiO2 and Si3N4.FWHM(G) and A(2D)/A(G), Fig. 4c-d, are comparable for all SLG SCs, except for b1-4 after Si3N4 deposition, where they decrease due to EF >100meV.Thus, our wafer-scale Raman characterization reveals that the top-SLG in the DSLG is comparable to micro-mechanically exfoliated flakes in terms of doping, 98 strain 107 and strain fluctuations. 108,109The transfer of hBN has marginal effect on the properties of the bottom-SLG, however it plays a key role in preserving the structural integrity of the crystals and avoid the formation of Raman-active defects during Si3N4 deposition, thus avoiding µ degradation.The Raman analysis shows an increase in doping, strain and strain fluctuations in the bottom SLG after the PECVD process, however, the PECVD process results in an homogeneous dielectric layer, crucial for reproducible operation of DSLG modulators. 34 then investigate the electrical transport properties of the transferred SLG-SCs using back-gated multi-terminal devices, at RT and exposed to air.This allows us to monitor two key performance parameters for SLG integration in a photonic circuit: contact resistance (Rc) and µ.
To quantify Rc, we use transfer-length method (TLM) 110 devices, as in Figs.5a,b, defined by EBL, reactive-ion etching and thermal evaporation of metallic contacts.Ni/Au 7/60nm top contacts evaporated <10 -5 mbar provide the highest performing configuration in terms of yield (>80% of working devices) and RC when compared to Cr, Ti and Ni and to other contact geometries, such as one-dimensional side contacts. 111By measuring the two-terminal resistance over different channel lengths (l) we extrapolate the residual resistance at l = 0, which corresponds to 2 × Rc, 110 Fig. 5c.This procedure can be repeated for different EF, set by the back-gate voltage (VG), to obtain Rc as a function of EF, as for Fig. 5f, showing the statistical average over 56 devices and error bars as standard deviations.Rc remains <2500 Ω µm in the neutrality region, and is as ∼500 Ω µm for EF >0.2 eV, required in the operation of modulators at telecom wavelengths. 2The SLG EF must be set at energies larger than half of the photon energy in order to work at the edge of Pauli blocking. 42,43,112 1550 nm the photon energy is 0.8 eV, so that EF must be set slightly above 0.4 eV. 34These Rc are comparable to those previously reported for ultra-high µ >10 5 cm 2 V -1 s -1 devices. 111We get µ from 56 TLM structures as well as 36 Hall bars, in Figs.5d,f.The SLG resistivity, ρ, for the TLM devices is obtained from a linear fit of TLM channels (Fig. 5c) as a function of VG.The Hall bar ρ is derived from 4-terminal measurements, and fitted as for Ref. 113 In Fig. 5g, dashed lines indicate the average µ for both e and h, whereas the shaded areas represent the standard deviation.The average µ from Hall bars (∼4750 cm 2 V -1 s -1 for h and ∼4600 cm 2 V -1 s -1 for e) is higher than TLM (∼3600 and ∼3350 cm 2 V -1 s -1 , respectively).This could be caused by two factors.1) For each TLM, ρ is estimated from an average of 5 channels, with a total length of 75 µm, whereas the channel length in a Hall bar is 8 µm, comparable to that used in typical SLG transport measurements. 1132) Parasitic doping by the contacts has an effect in 2-terminal TLM measurements, 114,115 not present in 4-terminal Hall bar measuremnts. 116 with high (∼5900 cm 2 V -1 s -1 ), low (∼3500 cm 2 V -1 s -1 ) and average (∼4700 cm 2 V -1 s -1 ) mobility.
EAMs are based on the modulation of the surface optical conductivity at optical frequencies induced by electric field effect. 41,117SLG absorption is changed by moving EF above the Pauli blocking condition. 42,43,112This can be done by applying gating in a capacitor-like structure, with SLG one or both capacitor plates. 2 In our DSLG geometry, a reciprocal self-gating is obtained with VG, resulting in modulation of the surface carrier density, i.e. electro-absorption. 34The main advantages of this approach are the larger electro-absorption effect, due to the presence of two SLG, ∼twice that of SLG, 34 and the possibility to use undoped WGs, enabling integration onto any already existing platform, such as SOI for Si photonics or Si3N4 on Si. 34 Here we use a 150 mm Si3N4 photonic platform, with 260 nm Si3N4 on a 15 µm buried SiO2.The 1500 nm wide WG is designed to support a transverse-electric field (quasi-TE) mode at 1550 nm. 17The top cladding is thinned to ∼40 nm to maximize the evanescent coupling of the optical mode with the DSLG stack.The core of the modulators is the DSLG capacitor, comprising a SLG/hBN/Si3N4/SLG stack.The cross-section and a SEM image of a representative device is in Fig. 6a-b (see Methods for details).We prepare 30 SLG/hBN/Si3N4/SLG stacks on 30 WGs to fabricate 30 EAMs with different lengths (Fig. 6c-f).This allows us to benchmark the reproducibility of the fabrication process at wafer scale, through optoelectronic characterization of the devices.We test key performance parameters: static (DC-biased) and dynamic (DC-biased + RF) modulation depth, electro-optical (EO) BW, and eye diagram opening.We characterize the EAMs in static and dynamic (i.e.driven by a time varying electrical signal) mode, and collect the data to perform a statistical study of performance, Fig. 7.We first consider the transmission as a function of VG.Modulation is obtained by tuning EF of both SLG layers from complete optical absorption (EF <0.4 eV at 1550 nm) towards transparency (EF >0.4 eV). 34The static characterization on wafer scale shows modulation efficiency ∼0.25, 0.45, 0.75, 1dB V -1 for ∼30, 60, 90, 120 µm EAMs, respectively, Fig. 7a.We then characterize the EO BW, i.e. the BW of the conversion efficiency, defined as the ratio between the output and the input power, 17 from the electrical signal driving the modulator and the optical modulated signal at the output of the modulator. 17This parameter determines the maximum operating speed, and is typically affected by RC. 118 The EAM BW is mainly limited by its RC time constant, 118 i.e. the series resistance (R) of the device multiplied by the DSLG capacitance, C, given by the series of gate dielectric capacitance and quantum capacitance of the two SLGs, 119 with R=RC+RS of the SLG section between DSLG capacitor and metal contacts.As C is proportional to the device length, while R is inversely proportional to it, we would expect a length independent 3 dB electro-optical BW.However, Fig. 7b shows that the BW changes with length, with longer devices having lower BW.We get ∼11.5, 6.5, 7.4 GHz for 30, 60,120 µm, respectively.The reason is that a further contribution to R comes from the output 50 Ω impedance of the Vector Network Analyzer (VNA) used to perform the measurements (see Methods).This is the main limiting resistive contribution because of our low Rc ∼500 Ω µm at EF >0.2 eV.
We then test the DSLG EAMs using a non-return-to-zero (NRZ) electrical driving signal, 58 i.e.
a digital two-level sequence, generated with a pattern generator (PG) (Anritzu MP1800A).This instrument allows us to obtain pseudo-random binary sequences (PRBS), i.e. deterministic binary sequences of bits with statistical behaviour similar to a pure random sequence, 120 with adjustable lengths (up to 2 31 -1 bits).The signal is applied to the DSLG EAMs electrodes through a RF cable and a bias-tee.This generates a modulated optical signal, detected by a high-frequency (70 GHz)   photodetector (Finisar XPDV3120) connected to a sampling digital oscilloscope (Infinium DCA 83484A, BW ∼50 GHz).By doing so, we can visualize on the oscilloscope the resulting eye diagram, 121 Fig. 7c.This gives the frequency dependent ER and 3 dB EO BW as a function of device length, and 10/15/20 Gbps data-rate. 121The eye diagram measurement of the data stream along with ER and 3 dB EO BW demonstrate EAMs at 20 Gb s -1 on wafer scale.Our wafer scale fabrication approach may also be used on different photonic platforms, e.g.SOI.The smaller WG cross section, 480 nm × 220 nm, would reduce modulator stack capacitance improving EAM speed.The change from Si3N4 to SOI, as reported in Ref., 47 increases the EO BW to at least 30 GHz, and the data rate to 50 Gb s -1 in a 100 µm EAM.Improving the SLG quality, in terms of µ after Si3N4 encapsulation, can increase performance in terms of insertion loss per unit length.Assuming a maximum absorption ~0.1 dB µm -1 and <0.001 dB µm -1 in the transparency region for µ >3000 cm 2 V -1 s -1 at 0.4 eV, the EAM length can be reduced to 50 µm with a maximum ER =5 dB and a halved capacitance.By reducing the RC constant, we expect to approximately double its BW with respect to the 100 µm device, thus achieving ~60 GHz.This optimization, combined with a SOI WG, could result in EAMs competitive with present microring based SOI modulators 28,122 and SiGe EAMs. 29The extra value of SLG-based EAM is the broad operation spectrum, from O (1300 nm) to L-band (>1625 nm) and beyond, while SiGe modulators are restricted to the C band (1530 nm-1565 nm), 123 and the Si microring modulators are limited to the resonant wavelengths. 124

Conclusion
We presented the full process flow (from growth, to transfer, integration on WGs, and photonic devices fabrication) for SLG-based photonics on wafer-scale.Our approach yields high-quality highly-uniform SLG on wafer-scale, as indicated by statistical spectroscopic and electrical characterization.We used wafer scale hBN encapsulation to minimize damage during dielectric deposition.We applied this to realize double SLG electro-absorption modulators on the passive Si3N4 platform.Our approach is easier and more reproducible in terms of yield and uniformity compared to the transfer of a continuous SLG film over the full wafer area, because the process is based on individual crystal matrices.SLG single crystals have higher mobility than polycrystalline films, with high-quality top contacts, with a reproducible contact resistance ∼500 Ω µm.Our approach can be used for other photonics building blocks, such as photodetectors or mixers.

Methods
SLG crystal matrices are grown on 25 µm Cu foils (Alfa Aesar #46365).Prior to SLG growth, each foil is electropolished in an electrolyte consisting of water, ethanol, phosphoric acid, isopropyl alcohol and urea, as for Ref. 79 The Cu foil is patterned using UV lithography.Cu is spin-coated with a Shipley S1813 positive photoresist, baked at 110 °C for 1 min and exposed to UV light using a Cr mask containing the required seeding pattern (UV dose ∼ 200 mJ cm -2 ). 25 nm Cr is thermally evaporated (Sistec) at 1x10 -5 mbar, followed by liftoff in acetone.The samples are then rinsed in isopropyl alcohol.
Growth is performed in an Aixtron BM Pro cold-wall reactor at 25 mbar and 1060 °C.The samples are kept under Ar flow during the T ramp-up and are annealed for 10 min at the growth T.
Growth is performed by flowing 0.5 sccm CH4, 50 sccm H2 and 900 sccm Ar.Following the 20 min growth, the heating is switched off and the sample is cooled <120 °C under Ar flow.SLG on Cu is then coated with a support polymer (100 nm PMMA 950K and 1.5 µm PPC) and a PDMS frame is attached to the perimeter of the Cu foil.SLG electrochemical delamination is performed in 1M NaOH.Cu/SLG is used as the anode, and ∼2.4 V is applied with respect to a Pt counter electrode, Fig. 8a.The voltage is adjusted to maintain a current ∼3 mA, to avoid excessive formation of H2 bubbles, which may cause damage to SLG.The freestanding polymer/SLG membrane is then removed from the electrolyte and rinsed 3 times in DI water, then dried in air.
The lamination of SLG on the target wafer is performed in a transfer tool, Fig. 8a.The target wafer is placed on a micrometric stage with 3-axis translational and azimuthal rotational movement, Fig. 8b.Alignment of the WGs to the SLG SC matrix is performed exploiting the SLG contrast on the polymer membrane in transmission mode, Fig. 1d.The optical system of the transfer tool consists of a 0.58x-7x microscope objective with coaxial illumination and a DSLR camera with a 2x adapter tube, giving a final magnification∼1.16x-14x.Following alignment, the wafer is heated to 100 °C using the inbuilt stage heater with a Proportional-Integral-Derivative (PID) controller, and the membrane is brought into contact with the wafer to laminate the SLG.Heating the wafer reduces the adhesion of PDMS, and the frame can be then detached from the wafer, Fig. 7b.Depending on the geometry of the wafer, several cycles of the above procedure are performed to populate the wafer with SLG SCs.For a typical SLG SC matrix of 25×40 mm 2 , 16 cycles populate 90% of a 150 mm wafer.Finally, the wafer is placed in acetone to remove the support polymer, followed by a rinse in isopropyl alcohol.
The fabrication of the DSLG modulator stack is performed as follows.A matrix of SLG SCs is transferred on the target wafer, and aligned to the Si3N4 WG, Fig. 9a.The bottom layer SLG is spin-coated with PMMA 950 A4 (Micro-chem), patterned using EBL and etched using RIE, Fig. 9b.
Contacts to the bottom SLG are fabricated using EBL and thermal evaporation of 7 nm Ni and 60 nm Au, followed by lift-off in acetone, Fig. 9c.A 2×2.5 cm 2 polycrystalline 1L-hBN (Graphene Laboratories Inc) grown on Cu foil via CVD 125 is then electrochemically delaminated from Cu and transferred on the chips of the wafer via semi-dry transfer. 7617 nm Si3N4 is deposited using PECVD at 350 °C, Fig. 9e.The top layer of the modulator is fabricated following the same protocol of transfer (Fig. 9f), etching (Fig. 9g), and contacting (Fig. 9h).

Figure 1 .
Figure 1.Process flow.(a) Schematic cross-section of DSLG EAM.(b) Multiple tile stamping: i) schematic of SC-SLG matrix on Cu, ii) SC-SLG matrix on Cu covered with freestanding membrane and a frame, enabling aligned transfer, iii) delaminated SC-SLG matrix with freestanding membrane and frame, iv) transferred SLG on target wafer.(c) Photos of: i) as-grown SLG on Cu, ii) Cu with PDMS frame attached, iv) suspended polymer/SLG membrane and 150 mm photonic wafer with laminated SLG.(d) Optical micrographs of SC-SLG on Cu by dark field imaging, ii) suspended SLG-SCs on polymer membrane and iii) transferred SLG SC matrix on target wafer with photonic circuits.
Fig.2c is a statistical comparison of I(D)/I(G) in 800 spectra from 2 SLG SCs with Si3N4 on top (400 spectra each), one protected by 1L-hBN (orange), the other exposed to PECVD (dark cyan).98% of the spectra on hBN-encapsulated SLG have I(D)/I(G) < 0.1.100% of the non-encapsulated SLG have I(D)/I(G)>0.1,with an average I(D)/I(G) ∼0.48, corresponding to a defect concentration

Figure 2 .
Figure 2. Encapsulation of SLG thin film and protective 1L-hBN.(a) Schematic representation of PECVD deposition of Si3N4 on SLG without (top, dark cyan arrow) and with (bottom, orange arrows) intermediate 1L-hBN.(b) Typical Raman spectra on SLG SCs after transfer (black) after Si3N4 PECVD, with (orange) and without (dark cyan) 1L-hBN.The same colours are used in the correlation plots d-g.(c) Distribution of I(D)/I(G) from 800 spectra acquired on two SLG SCs, one protected (orange bars), the other exposed (dark cyan bars).Inset: optical micrographs of the two SCs, showing cracked areas in the exposed one.Scale bars 50 µm.(d) Pos(2D) as a function of Pos(G).Solid lines are linear fits of the data.e,FWHM(2D) as a function of Pos(G).(f) FWHM(G) as a function of Pos(G).(g) A(2D)/A(G) as
is representative of the variation of the Raman peaks within individual SLG SCs, while over the scale of the entire wafer SLG SCs have uniform properties.Small (10-20 µm wide) bilayer graphene (BLG) regions form at nucleation seeds during CVD (on 38/48 of the analysed crystals, see broad 2D peak central pixels in Fig. 4b 92 ).

Figure 4 .
Figure 4 .Wafer-scale Raman mapping at each fabrication step over different quadrants of the wafer.
Fig. 5h plots 3 representative traces of ρ as a function of VG, from Hall bars

Figure 5 .
Figure 5. Wafer-scale electrical characterisation.(a) Optical micrograph of TLM structures.(b) SEM image of representative TLM structure.(c) Estimation of RC via linear fit of TLM measurements.(d) Optical micrograph of Hall bars.(e) SEM image of representative Hall bar.(f) RC as a function of EF.(g) Statistics of e and h mobility from TLM and Hall measurements.Dashed lines represent the average µ.Shaded areas indicate the standard deviation.(h) Representative field effect curves for 3 Hall bars with µ ∼3500, ∼4600 and ∼5900 cm 2 V -1 s -1 .

Figure 6 .
Figure 6.DSLG modulators.(a) Cross-section of DSLG EAMs.The Si3N4 WG core is 1500 nm wide and 260 nm thick, the buried oxide is 15 µm, the distance of the metal electrodes from the WG edge is 700 nm (b) SEM image of DSLG EAM showing the overlap of the two SLG (blue and red) above the photonics WG (pink).(c-f) Optical micrographs of 4 chips with DSLG EAMs.

Figure 7 .
Figure 7. DSLG EAM characterization.(a) Modulation efficiency as a function of device length.(b) 3 dB EO BW as a function of devices length (c) Eye diagrams at: 10, 15, 20 Gb s -1 .

Figure 9 .
Figure 9. Process flow for DSLG EAM fabrication.(a) SC SLG transferred on WG.(b) SLG is patterned using EBL and RIE.(c) Ni/Au contacts are deposited using evaporation and lift-off.(d) 1L-hBN is transferred on top.(e) Si3N4 is deposited by PECVD.(f) Top layer SLG SC transfer.(g) Top SLG patterning.(h) Top contact deposition.