Solution-Processed Polymer Dielectric Interlayer for Low-Voltage, Unipolar n-Type Organic Field-Effect Transistors

The integration of organic electronic circuits into real-life applications compels the fulfillment of a range of requirements, among which the ideal operation at a low voltage with reduced power consumption is paramount. Moreover, these performance factors should be achieved via solution-based fabrication schemes in order to comply with the promise of cost- and energy-efficient manufacturing offered by an organic, printed electronic technology. Here, we propose a solution-based route for the fabrication of low-voltage organic transistors, encompassing ideal device operation at voltages below 5 V and exhibiting n-type unipolarization. This process is widely applicable to a variety of semiconducting and dielectric materials. We achieved this through the use of a photo-cross-linked, low-k dielectric interlayer, which is used to fabricate multilayer dielectric stacks with areal capacitances of up to 40 nF/cm2 and leakage currents below 1 nA/cm2. Because of the chosen azide-based cross-linker, the dielectric promotes n-type unipolarization of the transistors and demonstrated to be compatible with different classes of semiconductors, from conjugated polymers to carbon nanotubes and low-temperature metal oxides. Our results demonstrate a general applicability of our unipolarizing dielectric, facilitating the implementation of complementary circuitry of emerging technologies with reduced power consumption.


Measurement of the frequency behavior of the dielectric constant of the high-k polymers and of cross-linked PS.
The dielectric constant of the selected high-k polymers and of cross-linked PS (XLPS) was extracted by measuring the capacitance of metal-insulator-metal (MIM) capacitors (Figure SD1) with an Agilent 4294A Impedance Analyzer.
The capacitance (C) is: with and the vacuum permittivity and the relative permittivity of the layer and t is the thickness  0   of the layer.
For multi-layer dielectrics, the experimental data fit well with the theortetical capacitance calculated based on the model of two capacitors in series: From which: Which, for instance, for an XLPS (ε r = 2.6) layer of 40 nm and a CEP (ε r = 13) layer of 110 nm gives a total of ~6.3 and a C die of ~37.2 nFcm -2 .The experimental calculated value of the same multi-  layer is 37.5 nFcm -2 (see Figure S1 and Table 1).The results confirm that the crosslinking process for PS does not introduce non-idealities in the ε r -f curve, which remains ideally flat across the range of interest for frequencies and applied electric field.Moreover, the measured ε r = 2.6 does not deviate from pristine PS.All the high-k polymers exhibit dielectric relaxation above their respective relaxation frequencies, but some of them (in particular CEP, PVDF-TrFE, PVDF-TrFE-CFE) remain reasonably flat before the relaxation frequency, identifying an operational frequency range for the near-ideal operation of FET devices.Moreover, the majority of the investigated materials do not exhibit significant variation of ε r (due to e.g.ferroelectric effects) below 500 kV/cm, which is the range of interest for the applied electric field.The normalization of the extracted ε r to the value at a frequency of 1 kHz allows to determine the polymer with the flattest frequency response and the highest relaxation frequency (Figure SD2).By defining the relaxation frequency as the frequency where ε r is attenuated by 3 dB with respect to its value at 1 kHz, we have for CEP the best combination between a relaxation frequency of 1.73 MHz and the most reduced rolloff slope at lower frequency.Measurement of the magnitude of the electric field in the XLPS and CEP dielectric layers, within multilayer dielectric stacks of different thickness.
For bilayer capacitors: where the subscripts CEP and XLPS refer to the respective materials, E is the magnitude of the electric field, V is the voltage across the multilayer structure, t is the layer thickness, ε is the relative dielectric constant.With the measured dielectric constants ε XLPS = 2.6 and ε CEP = 13 (Figure SD1), with V = 10 V and for different thicknesses of the layers we calculated:   In order to exclude the possibility of pass-through pinholes in the cross-linked films, further analysis was carried out on the AFM maps of the dielectric layers.Both the as-spun and the rinsed samples have average surface roughness (R rms ) below 1 nm.Some slight changes are present.Specifically, prior to washing, some particle-like phases are present on top of the PS-crosslinked (XLPS) film, which are probably related to some aggregated Bis-PEG3-Az phases.We infer that the absence of these particles in the washed films are associated with the removal of such Bis-PEG3-Az aggregates.Importantly, both the as-spun and the rinsed samples present valleys with an average depth of 3.4 nm and maximum depth of 5 nm (Fig SD3 a,b).Considering the width of the observed depressions (≈ 150 nm) and the nominal apex radius of the tip used (<10 nm), such small variations in thickness cannot be ascribed to pass-through holes in a 40 nm film.In addition, the phase images (Fig. SD3  c,d) do not display any sharp contrast over the whole probed surface.If deep pinholes were present, the tip would not be able to touch the surface while scanning in correspondence of a deep pass-through hole, thus inducing a sudden jump in the phase.

Figure
Figure S2.a) Calculated mobility in the linear and saturation regimes for an OFET (W = 2 mm, L = 10 µm) based on P(NDI2OD-T2) and our bilayer dielectric with CEP (areal capacitance C diel = 32.9nF cm -2 ) and b) transfer curve for the same device operated with a maximum voltage bias of 5 V.

Figure
Figure S5.a) Transfer curve for the OFET (W = 2 mm, L = 10 µm) based on our bilayer dielectric with a CEP layer thickness of 80 nm (areal capacitance C diel = 41.9 nF cm -2 ) and b) superimposed capacitance-normalized transfer curves for devices with different thicknesses of the XLPS and CEP layers.

Figure
Figure S6.a) Extracted mobility for the realized OFET (W = 200 µm, L = 20 µm) based on CNTs and our bilayer dielectric with CEP and b) transfer curve (V d = 5 V) for the same device.

Figure
Figure S8.a) Extracted mobility for the realized OFET (W = 2 mm, L = 20 µm) based on IGZO and our bilayer dielectric with PVDF-TrFE and b) transfer curve (V d = 1 V) for the same device.
Figure SD3: a-b) Profile analysis of the dielectric layer as spun (a) and after rinsing with n-butyl acetate (b).c-d) AFM phase maps of the analyzed surfaces before (c) and after (d) rinsing.

Table SD1 :
Magnitude of E XLPS and of E CEP for different thicknesses of the dielectric layers in the multilayer stack.