This chapter presents circuit and design details for clocked circuits (latches and flip-flops) and clock-generating circuits (controlled delay lines and oscillators). We show how the basic circuit elements presented in Chapter 4 can be combined to produce robust timing and clocking elements to implement the timing and synchronization systems of Chapters 9 and 10.

LATCHES AND FLIP-FLOPS

In Section 9.3.4 we discussed the timing properties of clocked storage elements (latches and flip-flops). In this section we will explore various CMOS circuits that implement these elements. Flip-flops are often composed of pairs of latches that are transparent on opposite phases of a single clock; therefore, we will first describe the design of level-sensitive latches and then show how these are arranged into flip-flops.

Level-Sensitive Latches

A latch passes its input to its output (with a small delay) when its clock is asserted; when the clock is deasserted, the input is ignored, and the output presents the most recent value on the input sampled during a narrow window in time around the asserted-to-deasserted clock transition. The fundamental component of a latch is a storage device, and CMOS latches are generally built on the basis of one of two distinctly different storage techniques: capacitive and regenerative, as illustrated in Figure 12-1.

Latches that use capacitive storage are actually sample-and-hold devices that store a continuous (analog) value, and they are said to be “dynamic” because, if the input switch is left open for too long, parasitic leakage currents present in CMOS circuits will eventually corrupt the data stored on the capacitor.