Fabrication of two-dimensional in-plane gate transistors by focused ion beam doping

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Abstract

In-plane-gate (IPG) transistors have been fabricated using focused ion beam implantation doping of GaAs/In0.1Ga0.9As/Al0.35Ga0.65As heterostructures. At room temperature in the dark, the devices show good transistor characteristics and—in contrast to IPG transistors defined by insulation writing using ion implantation—the observed enhancement behavior is very good. For typical devices the source–drain current in the saturation region of 1.6μA at zero gate voltage could be increased by one order of magnitude to 16μA by a positive gate voltage of 8V. This improvement in the enhancement behavior with respect to IPG transistors defined by insulation writing is attributed to the higher electronic transport quality in the edge regions of the channel. The gate leakage current for typical operation parameters is below 350nA and at a gate voltage of −1V the channel is completely pinched off.

Introduction

Two-dimensional field effect transistors with source, drain, and gate within one plane, so called in-plane-gate (IPG) transistors, are known since 1990 [1]. In these devices, the channel conductance can be controlled by changing the channel width by the applied gate voltage and not by changing the electron density in the channel as in conventional field effect transistors [2]. Most of the IPG transistors fabricated so far have been prepared by writing insulating lines into semiconductor heterostructures, containing a two-dimensional electron gas (2DEG) using various methods [1], [2], [3], [4], [5]. Especially, the insulating writing using focused ion beam (FIB) implantation has been extensively used due to its good resolution and high writing speed [1], [2]. This negative mode pattern definition (insulation writing), employing FIB implantation resulted in IPG transistors with good depletion characteristics but rather poor enhancement behavior. This is due to the fact that for positive gate voltages the channel is extended to regions close to the insulating lines, where the electrical properties of the heterostructure are degraded due to the implantation process [6]. An approach to overcome this limitation of FIB implantation writing is to use positive mode pattern definition, i.e. writing the conducting areas of the IPG transistor instead of writing insulating lines between the terminals. Another advantage of positive mode writing would be the possibility to create n-type as well as p-type IPG transistors on the same chip, i.e. making a complementary logic based on IPG transistors feasible. So far positive FIB writing for IPG transistor fabrication was employed only by Hirayama [7]. He doped semi-insulating bulk GaAs creating regions with three-dimensional conductivity. Good transistor characteristics for n- and p-type devices were observed, but he had to sacrifice some advantages as given in a two-dimensional carrier system. The main disadvantage is that one cannot employ the higher carrier mobilities obtained in selectively doped heterostructures. Another drawback is that larger gate voltages are required to control the channel conductance, because the electrical field is not so effectively confined in the case of the three-dimensional IPG transistor [1], [7].

In this paper we present our approach to positive mode pattern definition by FIB implantation. We have prepared truly two-dimensional IPG transistors by creating patterned 2DEGs using FIB doping of initially undoped GaAs/InyGa1−yAs/AlxGa1−xAs heterostructures. In Section 2, we will present the experimental details before in Section 3 our results are presented and discussed. The paper will be concluded with a brief summary.

Section snippets

Experimental details

The GaAs/InyGa1−yAs/AlxGa1−xAs heterostructures used as base material for the implantation doping have been prepared by solid source molecular beam epitaxy (MBE) on GaAs(1 0 0) substrates and had the following layer sequence: After a 650nm GaAs buffer layer, 10nm In0.1Ga0.9As were deposited. This channel was followed by 10nm Al0.35Ga0.65As and 16 periods of a 2nm GaAs/1.1nm AlAs short period superlattice (SPS). After this SPS, 117nm Al0.35Ga0.65As were grown before the whole layer sequence was

Results and discussion

In Fig. 2, the source–drain current ISD as a function of the source–drain voltage VSD is shown for various gate voltages VG for an IPG transistor with dimensions as described above. It can be clearly seen that the device shows good transistor behavior: The channel conductance can be controlled well by the applied gate voltage VG. At VG=−1V, the channel is completely pinched off with a remaining source–drain current ISD of 30nA. For open-channel condition the source–drain current ISD increases

Summary

We have used the FIB implantation doping of GaAs/In0.1Ga0.9As/Al0.35Ga0.65As heterostructures to define truly two-dimensional in-plane gate transistors. The devices show good transistor characteristics, especially the channel conductance can be varied over a wide range by applying a gate voltage. In contrast to in-plane-gate transistors defined by insulation writing, the source–drain current in the saturation region of approximately 1.6μA at zero gate voltage can be increased by one order of

Acknowledgements

Two of the authors gratefully acknowledge the financial support by the GRK 384 (A.S.) and by the ‘Evangelisches Studienwerk Haus Villigst’ (C.M.).

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